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The Journal of Semiconductor Technology and Science (JSTS) is an international, peer-reviewed, and open-access journal that is published bimonthly.
- Scope: semiconductor processes, devices, circuits, and MEMS.
- Editor-in-Chief: Prof. Woo Young Choi (ECE, Seoul National University)
- Indexed within Science Citation Index Expanded (SCIE), SCOPUS, Korea Citation Index (KCI), and other databases.

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  3. 2023-08 (Vol.23 No.04)
  4. 10.5573/JSTS.2023.23.4.207
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References

1 
K. Gopalakrishnan, P. B. Griffin, and J. D. Plummer: I-MOS: A Novel Semiconductor Device with a Subthreshold Slope Lower than kT/q, IEEE International Electron Device Meeting (IEDM), San Francisco, USA, p. 289, 2002.DOI
2 
S. Cho, I. M. Kang, T. I. Kamins, B.-G. Park, and J. S. Harris: Silicon-compatible compound semiconductor tunneling field-effect transistor for high performance and low standby power operation, Appl. Phys. Lett., vol. 99, p. 243505, 2011.DOI
3 
T. Sakurai: Perspectives of low-power VLSI’s. IEICE Trans. Electron., vol. E87C(4), p.429, 2004.URL
4 
A. M. Walke, et al.: Fabrication and Analysis of a Si/Si0.55Ge0.45 Heterojunction Line Tunnel FET, IEEE Trans. Electron Devices, vol. 61, p. 707, 2014.DOI
5 
Y. S. Kwon, S. -H. Lee, Y. Kim, G. Kim, J. H. Kim, S. Kim: Surrounding Channel Nanowire Tunnel Field-Effect Transistor with Dual Gate to Reduce a Hump Phenomenon, J. Nanosci. Nanotechnol., vol. 20, p. 4182, 2020.DOI
6 
Kim, H.W., Sun, M.C., Kim, S.W. and Park, B.G.: Hump Phenomenon in Transfer Characteristics of Double-Gated Thin-Body Tunneling Field-Effect Transistor (TFET) with Gate/Source Overlap, IEEE 5th International Nanoelectronics Conference (INEC), Singapore, Singapore, pp. 364-366, 2013.DOI
7 
Lee, J.C. and Yu, Y.S.: Work-function engineering of source-overlapped dual-gate tunnel field-effect transistor, Journal of Nanoscience and Nanotechnology (JNN), vol. 44, pp. 90-101, 2018.DOI
8 
Prabhat Singh, Dharmendra Singh Yadav.: Impact of work function variation for enhanced electrostatic control with suppressed ambipolar behavior for dual gate L-TFET, Current Applied Physics, vol. 44, pp. 90-101, 2022.DOI
9 
Yun, C., Cho, S., Cho, I. H. and Kim, G.: Hump Phenomenon in Transfer Characteristics of Double-Gated Thin-Body Tunneling Field-Effect Transistor (TFET) with Gate/Source Overlap, 2022 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD), July 7-8, Busan, Korea, 2022, pp. 1-2.DOI
10 
Sentaurus Device, Synopsys, Version P-2019.03, Synopsys Inc.URL
11 
Kane, E., Theory of tunneling: Journal of Applied Physics, 32(1), pp. 83-91, 1961.DOI
12 
Biswas, A., Dan, S., Royer, C., Grabinski, W. and Ionescu, A.: TCAD simulation of SOI TFETs and calibration of non-local banc-to-band tunneling model, Microelectronic Enginnering, 98, pp. 334-337, 2012.DOI
13 
Shogo Fukami, Yoshihiko Nakagawa, Mel F. Hainey Jr., Kazuhiro Gotoh, Yasuyoshi Kurokawa, Masahiro Nakahara, Marwan Dhamrin and Noritaka Usam.: Epitaxial growth of SiGe on Si substrate by printing and firing of Al-Ge mixed paste, Japanese Journal of Applied Physics, vol. 58, no. 4, 2019.URL
14 
Takahiro Tsukamoto, Yosuke Aoyagi, Shouta Nozaki, Nobumitsu Hirose, Akifumi Kasamatsu, Toshiaki Matsui, Yoshiyuki Suda.: Increasing the critical thickness of SiGe layers on Si substrates using sputter epitaxy method, Journal of Crystal Growth, vol. 600, 2022.DOI
15 
X. Liu, K. Lim, Z. Wu, Z. Xiong, Y. Ding, H. Nong.: A Study of Inverse Narrow Width Effect of 65nm Low Power CMOS Technology, Incorporating Knowledge in Genetic Algorithms for Device Synthesis, pp. 1138-1141, 2008.DOI
16 
Cheung, K.T: On the 60 mV/dec@300 k Limit for MOSFET Subthreshold Swing, Symposium on VLSI Technology (VLSIT), Ap, Hsinchu, Taiwan, pp. 72-73, 2010.DOI
17 
Huang, Q., Huang, R., Zhan, Z., Qiu, Y., Jiang, W., Wu, C. and Wang, Y.: A Novel Si Tunnel FET with 36 mV/dec Subthreshold Slope Based on Junction Depleted-Modulation Through Striped Gate Configuration, IEEE International Electron Device Meeting (IEDM), San Francisco, CA, USA, pp. 187-190, 2012.DOI
18 
Choi, W.Y., Park, B.G., Lee, J.D. and Liu, T.J.K.: Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec, IEEE Electron Device Letters, 28(8), pp. 743-745, 2007.DOI
19 
Iman Chahardah Cherik, Saeed Mohammadi, Ali Asghar Orouji.: Switching Performance Enhancement in Nanotube Double-Gate Tunneling Field-Effect Transistor With Germanium Source Regions, IEEE Transactions on Electron Devices, vol. 69, pp. 364-369, 2021.DOI
20 
Faraz Najam, Sangwan Kim, Woo Young Choi, Yun Seop Yu.: Physically Consistent Method for Calculating Trap-Assisted-Tunneling Current Applied to Line Tunneling Field-Effect Transistor, IEEE Transactions on Electron Devices, vol. 67, pp. 2106-2112, 2020.DOI
21 
Chander, S., Sinha, S.K., Chaudhary, R.: Ge-Source Based L-Shaped Tunnel Field Effect Transistor for Low Power Switching Application, Silicon 14, pp. 7435-7448, 2022.DOI