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Title Optimization of Dual-workfunction Line Tunnel Field-effect Transistor with Island Source Junction
Authors (Chaewon Yun) ; (Sangwan Kim) ; (Seongjae Cho) ; (Il Hwan Cho) ; (Hyunwoo Kim) ; (Jang Hyun Kim) ; (Garam Kim)
Page pp.207-214
ISSN 1598-1657
Keywords Dual workfunction; line tunneling field-effect transistor (LTFET); junction underlap; TCAD device simulation; low-power operation
Abstract In this research, a novel dual workfunction (DWF) line tunnel field-effect transistor (LTFET) is optimized by using high WF gate-drain underlap and low WF gate-source underlap. Through numerical technology computer-aided design (TCAD) device simulations, it is confirmed that on-current (ION) can be increased by highly localized point tunneling while suppressing off-current (IOFF) by adjusting the distance between low-WF gate and source junction. Considering on-off current ratio (ION/IOFF) and the process variation, the distance between high-WF gate and source junction is optimized to be 3 to 5 nm.