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References

1 
A. E. Eshratifar, A. Esmaili, and M. Pedram, “BottleNet: A deep learning architecture for intelligent mobile cloud computing services,” IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 1-6, Jul. 2019.DOI
2 
W.-J. Chang et al., “iBuffet: A deep learning-based intelligent calories management system for eating buffet meals,” IEEE International Conference on Consumer Electronics (ICCE), pp. 1-2, Jan. 2021.DOI
3 
B. Fang et al., “FlexDNN: Input-Adaptive On-Device Deep Learning for Efficient Mobile Vision,” IEEE/ACM Symposium on Edge Computing (SEC), pp. 84-95, Feb. 2021.DOI
4 
J. Lee and H. -J. Yoo, "An Overview of Energy-Efficient Hardware Accelerators for On-Device Deep-Neural-Network Training," IEEE Open Journal of the Solid-State Circuits Society, vol. 1, pp. 115-128, Oct. 2021.DOI
5 
N. P. Jouppi et al., "In-datacenter performance analysis of a tensor processing unit," ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), pp. 1-12, Dec. 2017.DOI
6 
J. Wang, S. Park and C. S. Park, "Optimization of Communication Schemes for DMA-Controlled Accelerators," in IEEE Access, vol. 9, pp. 139228-139247, Oct. 2021.DOI
7 
DDR3 SDRAM JEDEC standard, JESD79-3C, Nov. 2008.URL
8 
S. M. JAFRI et al., “Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators,” ACM Transactions on Architecture and Code Optimization (TACO), Vol. 18, pp. 1-29, Dec. 2020.DOI
9 
F. Schuiki, M. Schaffner, F. K. Gürkaynak and L. Benini, "A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets," IEEE Transactions on Computers, vol. 68, pp. 484-497, April. 2019.DOI
10 
C. Sudarshan et al., “A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing,” Embedded Computer Systems: Architectures, Modeling, and Simulation. (SAMOS), Aug. 2019.DOI
11 
E. Mintarno and S. Y. Ji, "Bit-pattern sensitivity analysis and optimal on-die-termination for high-speed memory bus design," IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, pp. 199-202, Nov. 2009.DOI
12 
Performance Characteristics of IC Packages, 2000 Packaging Data book, Intel.URL
13 
G. Dong, Y. Biao, D. Xidong and L. Yuan,, "Research on the influence of vias on signal transmission in multi-layer PCB," 13th IEEE International Conference on Electronic Measurement & Instruments (ICEMI), pp. 406-409, Oct. 2017.DOI
14 
IBIS model of Micron MT41K512M16, 2016.URL
15 
DDR3L SDRAM description, MT41K512M16, Micron, 2015.URL
16 
S. Y. Ji, B. Loop, P. D. James and V. Paranjape, "An empirical study of performance and power scaling of low voltage DDR3," 19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems, pp. 9-12, Nov. 2010.DOI
17 
W. -C. Lee et al., "Parallel Branching of Two 2-DIMM Sections With Write-Direction Impedance Matching for an 8-Drop 6.4-Gb/s SDRAM Interface," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 9, no. 2, pp. 336-342, Feb. 2019.DOI