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Bandapati , Satish K., Scott C. Smith., 2007, Design and characterization of NULL convention arithmetic logic units, Microelectronic engineering 84, No. 2, pp. 280-287DOI
Parsan F. A., Smith S. C., Oct 2012, CMOS implementation of static threshold gates with hysteresis: A new approach, in Proc. IEEE/IFIP 20th Int VLSI and System-on-Chip (VLSI-SoC) Conf, pp. 41-45DOI
Smith , Scott C., Ronald F. DeMara, Jiann S. Yuan, Ferguson D., 2004, Optimization of NULL convention self-time circuits, INTEG-RATION, the VLSI Journal 37, No. 3, pp. 135-165DOI
Bandapati , Satish K., Scott C. Smith, Minsu Choi., 2003, Design and characterization of NULL convention self-timed multipliers., IEEE design & test of computers 20, Vol. no. 6, No. 6, pp. 26-36DOI
Bonam R., Chaudhary S., Yellambalase Y., Choi M., Aug 2007, Clock-free nanowire crossbar architecture based on null convention logic (ncl), in Proc. 7th IEEE Conf. Nanotechnology (IEEE NANO), pp. 85-89DOI
Bailey , Andrew D., Jia Di, Scott C. Smith, Alan Mantooth. H., 2008, Ultra-low power delay-insensitive circuit design, In 2008 51st IEEE Midwest Symposium on Circuits and Systems, pp. 503-506DOI
Smith , Christopher Scott, Demara. Ronald F., 2001, Gate and throughput optimizations for null convention self-timed digital circuits, Doctor of Philosophy, DissertationGoogle Search
Parsan F. A., Smith S. C., Aug 2012, CMOS implementation comparison of ncl gates, in Proc. IEEE 55th Int. Midwest Symp. Circuits and Systems (MWSCAS), pp. 394-397DOI
Mader , Roy , Eby G. Friedman, Ami Litman, Ivan S. Kourtev., 2002, Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits., In 2002 IEEE International Symposium on Circuits and Systems. Proceedings, Vol. 1, pp. I-IDOI
Morgenshtein , Arkadiy , Michael Moreinis, Ran Ginosar., 2004, Asynchronous gate-diffusion-input (GDI) circuits, IEEE transactions on very large scale integration (vlsi) systems, Vol. 12, No. 8, pp. 847-856DOI
Morgenshtein , Arkadiy , Alexander Fish, Israel A. Wagner., 2002, Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits, IEEE transactions on very large scale integration (VLSI) systems, Vol. 10, No. 5, pp. 566-581DOI
Morgenshtein , Fish A., Wagner A., 2001, Gate-diffusion input (gdi)-a novel power efficient method for digital circuits: a design methodology, in Proc. 14th Annual IEEE Int. ASIC/SOC Conf, pp. 39-43DOI
Morgenshtein , Fish A., Wagner I. A., 2002, Gate-diffusion input (gdi) - a technique for low power design of digital circuits: analysis and characterization, in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), Vol. 1, pp. I-477-I-480DOI
Morgenshtein , Shwartz I., Fish A., Nov 2010, Gate diffusion input (gdi) logic in standard CMOS nanoscale process, in Proc. IEEE 26-th Convention of Electrical and Electronics Engineers in Israel, pp. 776-000-780DOI
Morgenshtein , Yuzhaninov V., Kovshilovsky A., Fish A., 2014, Full-swing gate diffusion input logiccase study of low-power cla adder design, INTEGRATION, the VLSI journal, Vol. 47, No. 1, pp. 62-70DOI