Mobile QR Code QR CODE


Lin J., Chiu P., Chang Y., 2016, SAINT: Handling Module Folding and Alignment in Fixed-outline Floorplans for 3D ICs, Proc. ICCAD, pp. 1-7DOI
Lin J., Yang J., Nov. 2017, Routability-driven TSV-aware Floorplanning Methodology for Fixed-outline 3D ICs, IEEE Trans. Comput.-Aided Design Circuits Syst., Vol. 36, No. 11, pp. 1856-1868DOI
Adya S. N., Markov I. L., Dec. 2003, Fixed-outline floorplanning: enabling hierarchical design, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 11, No. 6, pp. 1120-1135DOI
Nakatake S., et al , Jun. 1998, Module packing based on the BSG-structure and IC layout applications, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., Vol. 17, No. 6, pp. 519-530DOI
Chan T., et al , 2006, mPL6: Enhanced multilevel mixedsize placement, Proc. ACM ISPD, pp. 212-214DOI
Kahng A. B., Wang Q., 2006, A faster implementation of APlace, Proc. ACM ISPD, pp. 218-220DOI
Wang Y., Yeo D., Shin H., 2013, An Effective Legalization Method Using Iterative Movement of Blocks, Proc. SoCGoogle Search
Zhan Y., Feng Y., Sapatnekar S., 2006, A Fixed-die Floorplanning Algorithm Using an Analytical Approach, Proc. ASP-DAC, pp. 771-776DOI