1. DPS

The DPS plays the role of supplying voltage and current to the DUT while also performing the function of measuring the output voltage and current from the DUT. This high performance device adapts to various testing environments, allowing for the adjustment of specific power values as needed and ensuring a stable power supply without any noise ^[11]. The DPS is composed of the DPS IC (Integrated Circuit) responsible for applying voltage and the PMU (Power Management Unit) IC responsible for supplying current, and it performs the following operations.

DPS applies constant voltage and current to the DUT to conduct DC parameter tests. By sequentially increasing and decreasing voltage and current, it allows for the observation of voltage and current outputs from the DUT, facilitating the characterization of its characteristics ^[12]. The overall configuration of the DC parameter test system is depicted in Figs. 2 and 3.

● VSVM (Voltage Source Voltage Measure): Voltage is applied by the OP-AMP until the voltage at the feedback connected to the DAC (Digital Analog Converter) equals the voltage flowing through the resistor network. The voltage across the PM resistor is then measured.

● VSIM (Voltage Source Current Measure): When voltage is applied by the DAC, it passes through the Range resistor via the OP-AMP, and feedback occurs through the voltage at DPS${}_{SENSE}$. The voltage across the Load resistor becomes equal to the voltage applied by the DAC, allowing for the measurement of current flowing through the Load resistor.

● VM (Voltage Measure): A different VM path is selected from the DPS IC, connecting SENSE to PMUPM power. The power supplied to the PMU is measured through DPS IC's DPS${}_{SENSE}$ and SYS${}_{SENSE}$.

● ISVM (Current Source Voltage Measure): After setting the desired current range, DAC applies voltage to the R${}_{SENSE}$ resistor. The current feedback loop operates through R${}_{SENSE}$, ensuring the output matches the specified current. The resulting voltage is applied to the Load resistor through the DPS IC. The voltage across the Load resistor is measured by the ADC, and the voltage across DPS IC's DPS${}_{SENSE}$ and SYS${}_{SENSE}$ paths is selected through the Measure Out Mux and Gain for ADC measurement.

2. SPI (Serial Peripheral Interface)

SPI (Serial Peripheral Interface) communication is a serial peripheral device interface. SPI is one of the serial communication methods, such as UART (Universal Asynchronous Receiver/Transmitter), I2C, and CAN (Controller Area Network), used for transmitting data between peripheral devices like microcontrollers, shift registers, and SD cards. The distinctive feature of SPI communication is its synchronous nature, supporting one-to-many (1: N) communication. Devices communicate in master-slave mode, where the master device initializes the data frame. Multiple slaves can be connected to one master using the SYNC line. The structure of SPI can be observed in Fig. 4, as detailed below.

● SCLK (Serial Clock): Serial clock signal generated by the master and transmitted to the slave, facilitating the synchronization of data in and out of the device.

● MOSI (Master Out Slave In): Serial data input pin where data is output by the master and input by the slave.

● MISO (Slave In Master Out): Serial data output pin for data read back, where data is input by the master and output by the slave.

● SYNC (Frame Synchronization Input): Signal used to select the slave (operates in an active-low format and is output by the master as a control signal).

The master selects the desired slave through SYNC and transmits synchronized signals to SCLK through MOSI. The selected slave is activated by the SYNC signal, receiving data synchronized to SCLK through its own MOSI. These synchronized MOSI signals are combined into meaningful data, typically in 8, 16, or more bits. While SPI communication offers fast transmission speeds, it requires a significant number of lines for multiple communications. Despite this drawback, SPI communication is characterized by faster transmission speeds compared to I2C communication. Considering the superior aspects of fast transmission speeds and data synchronization, the DPS board has adopted SPI communication. In this paper, SPI communication is implemented using FPGA. The data bits used in the paper are 16 bits, with a 7-bit address and 1 bit serving the purpose of indicating the mode. Additionally, the FPGA designed in this study operates as the master.

1. Configuration

In this paper, we aim to establish a versatile FPGA-based DPS control environment that can be universally applied when incorporating DPS with various specifications into the DPS Board development environment. The control of DPS IC & evaluation boards and the application of desired voltage values using digital signals have traditionally relied on PC software, which has limited the potential for system enhancements in areas other than speed and reliability. However, this paper introduces FPGA to propose a more widely applicable approach that effectively reduces the software dependency for all DPS ICs. This methodology enables dynamic reconfiguration of the DPS IC control logic, increasing system flexibility and providing adaptability across various models and applications. Thus, the FPGA-based control strategy presented offers a superior alternative to conventional methods, significantly reducing software dependency while maintaining high levels of performance ^[11]. The transition to an FPGA-based solution signifies a significant advancement in the development of the environment controlling DPS boards, heralding the evolution towards a more efficient and adaptable control mechanism ^[14]. The proposed system configuration is depicted in Fig. 5.

As illustrated in the above figure, the system configuration utilizing FPGA consists of an FPGA capable of controlling DPS, the DPS board, and an additional Measurement Unit for validation. The Measurement Unit plays a role in verifying the current and voltage applied to the test target, DUT. It communicates data necessary for DPS control through FPGA and, upon receiving this data, the DPS performs specific operations according to the instruction data, facilitated by the DAC. To transmit data to DPS through SPI, a dedicated SPI module was designed on FPGA. For the construction of the proposed environment, Analog Devices' AD5560, commonly used in actual mass-produced test equipment, was utilized. The aim is to validate the FPGA-based evaluation environment. The AD5560 is controlled through a 24-bit serial command comprising 1 bit of control signal, 8 bits of address data, and 16 bits of data bits. Depending on the input signals, the AD5560 generates and controls the desired signals. In this paper, to build the system configuration shown in Fig. 5, the Libertron FPGA Starter Kit, featuring the xc7z020-clg484-1 chip, was used as the FPGA board. For the DPS evaluation board, the EVAL-AD5560 (evaluation board) from Analog Devices was employed. Additionally, to measure the output signals generated by the AD5560 through FPGA control, the Rohde & Schwarz RTB 2002 oscilloscope was used as a Measurement Unit, setting up the experimental environment as shown in Fig. 6. DPS is not controlled through separate evaluation environments for each manufacturer such as Ana-log Devices, but it controls signals and data through an FPGA, and the resulting output is measured using an oscilloscope. Therefore, as DPS is changed, a new DPS is installed on the evaluation board, and in accordance with the data sheet and the specified protocol for the way of signaling, signals and data can be variably applied through the FPGA, enabling the control and evaluation of various DPS.

2. System

The characteristic of the SPI module implemented with the FPGA operates as a FSM (Finite State Machine). The operation flow is as shown in Fig. 6. Before explaining the state of SPI, the FSM can be said to be a finite automaton, that is, an abstract machine that can have a finite number of states. Such a machine only has one state at a time, and the current state refers to a state at any given time. Such a machine can change from one state to another by any event, which is called transition. A specific finite automaton is defined as a possible transition state from the current state and a set of conditions that cause such transition. The states for the SPI module were defined as follows:

● IDLE: Data initialization.

● READY: Data transmission preparation operation.

● SEND: Data transmission.

● DONE: Operation completed.

The IDLE state initializes all input and output values to 0, including SCLK, SYNC, and MOSI. In the READY state, the system is prepared for data transmission, and the SYNC signal is used to synchronize the operation between the FPGA and AD5560.

The SEND state involves the actual data transmission. When the SYNC signal, triggered by the falling edge (1 to 0 transition) in the READY state, toggles, the system transitions to the SEND state. In this state, the SCLK is timed to operate 24 times during data transmission. The code used in this paper utilizes the SCLK_Index variable to count each rising or falling edge of SCLK, resulting in a total of 48 counts per cycle, representing two cycles of SCLK operation.

In the DONE state, the operation is completed when the SYNC value toggles from 0 to 1 (rising edge), and all variables are reset. The system then transitions to the next state, IDLE, and the cycle repeats as described earlier. Our SPI performs a READ operation after a WRITE operation. Therefore, one cycle operates during WRITE, and another during READ.

The SPI protocol in this paper was designed based on a clock with a frequency of 100 MHz A variable named freqwas declared in the SPI module, where the value of freq represents the clock period. For example, if the freq value is 1, SCLK toggles with each clock cycle. Similarly, if the freq period is 2, SCLK toggles every two clock cycles. This flexibility in adjusting the frequency with simple input changes is a significant feature of our designed SPI_Master. It allows easy control of specifications through minor variable adjustments in software, providing adaptability to changes without altering the entire system when the DPS changes. Furthermore, in the final connection stage, a clock of 40 MHz was applied, and detailed explanations regarding this will be covered in Section 3, Connect.

3. Connect

In this paper, the FPGA Starter Kit from Libertron was utilized. To achieve this, the board-to-board connections were established by referring to the datasheet provided by Libertron.

To efficiently transmit signals and data to the SPI_Mas-ter, a configuration as shown in Fig. 8 was adopted. Within the Top module, it was designed to supply the SPI_Master clock and data. Additionally, signals such as SCLK and SYNC were configured.

In the Top module, a clock of 100 MHz was provided, which was subsequently divided from 100 MHz to 40 Hz before supplying the clock to the SPI_Master. This choice was influenced by the relationship between the frequency of SCLK, which is divided according to the number in the freq variable. For the AD5560, a clock frequency of around 20 MHz is desired. While it is possible to change SCLK to 50 Hz or 25 MHz with a 100 MHz input, achieving 20 MHz was challenging, so a clock of 40 MHz was applied. The system was controlled by configuring a simple additional circuit to match the specifications of the DPS. This ability to make the system operate according to DPS specifications by adding some logic without changing the entire logic block is another noteworthy feature.

Furthermore, Fig. 9 shows the Synthesis design I/O Port in XILINX's EDA (Electronic Design Automation) tool, Vivado, where I/O ports can be configured.

When configuring the I/O ports, SCLK was set to AB11 (JA7), SYNC to AB10 (JA8), and MOSI to AB09 (JA9) to verify through the FPGA Starter Kit's JA port. Subsequently, an oscilloscope was used to compare the signals coming out of the FPGA (Master) -- MOSI (AB9) -- with the signals input to the AD5560 (Slave) -- MISO.

1. Simulation

Simulation was conducted in the Vivado testbench. The testbench serves as an environment for testing, providing valuable insights into signal timing, FSM operation, and other module behaviors. While the results in the testbench may not perfectly match those in the actual environment, it is useful for verifying the operation of modules. Hence, in this paper, the goal was to validate the operation of the testbench system. The results from the testbench are identical to those shown in Fig. 10.

Implementing the FSM model and specifying each state is an important aspect of system design and programming, and the operation of each state has been explained earlier. In the module we have implemented, we use the m_state register to represent the state, mapping 0, 1, 2, 3 to IDLE, READY, SEND, DONE states, respectively. Therefore, we can verify that the system is operating correctly by observing the changes in the value of m_state in the test bench. At the end of the start sequence, we observe the transition from IDLE (0) to READY (1), then when SCLK operates, it transitions to the SEND (2) state, and finally, after the last SCLK operation, DONE (3) is activated before transitioning back to IDLE (0). Both write and read operations involve exchanging 24-bit signals, so the system operates in the sequence of 0, 1, 2, 3, 0.

In the Top module, the following data definitions were applied: data0 $=$ 23'h010200, data1 $=$ 23'h029950, data2 $=$ 23'h088000, data3 $=$ 23'h08E3EC. The testbench confirmed the application of the first data, data0 $=$ 23'h010200, among them. As a result, two glitches can be observed. The testbench, however, shows that there is no anomaly in the operation. Additionally, in the first cycle, data is transmitted, and in the second cycle, no data is received during the READ operation. This behavior is natural since this testbench is focused on verifying the operation of the SPI Master signal input. It is normal not to receive any data during the READ operation as there is no incoming signal from the Slave. Furthermore, examining the state parameter values reveals that the value of the state increases during system operation and then returns to 0. This indicates that the state is operating correctly. SCLK is operating below 20MHz, confirming that the simple logic addition mentioned earlier and the freq variable of the SPI Master module are functioning correctly. This signifies the validation of the operation of the general-purpose DPS evaluation environment.

2. SPI Interface Function Implementation

To verify normal operation, the method of transmitting signals from MOSI and checking the signals coming out from MISO was employed. Typically, in SPI, upon receiving a signal, the same signal is transmitted again to validate it. This process was confirmed using AD5560. Moreover, if the waveform of the signal coming out from MISO is not normal, it could be considered as an indication of an issue in the system. In other words, by confirming the waveform of the signal, it can be verified that communication between FPGA and DPS is occurring smoothly. As shown in Fig. 10, MOSI signal (D10) and MISO signal (D11) exhibit identical waveforms, confirming the successful communication.

Through the waveform in Fig. 11, it was confirmed that the results from both simulation and the real-world environment were consistent. As mentioned earlier, 23'h010200 was applied to the top module. Consequently, signal fluctuations can be observed in two bits. Additionally, the sections without signal changes in the middle indicate the execution of the read operation, and the noise-free part in the middle corresponds to the state of SYNC signal being 1, representing the initial write operation in the DONE and read operation in the IDLE state. Thus, the operation of the universal DPS evaluation environment can be considered verified.

3. Operation

The stored data values exactly match the settings described in the datasheet. Referring to Fig. 12(a), the register structure of the system control register can be examined, confirming that the MEASOUT Gain and offset DAC are configured to 1 and 0x8000 respectively, as indicated in Fig. 13. The value of data0, 23'h010200, aligns with the provided specifications. The MEASOUT Gain is controlled by the 12th and 13th registers of the 0x01 register. By adding the 00 value, the MEASOUT Gain was set to 1 MI gain 20. Additionally, the force amplifier block has been powered down as it is unnecessary for the experiment. Fig. 12(b) further illustrates that the offset DAC is also set to 0x8000.

The Fig. 13 below demonstrates sending the value 23'h088000 to the DAC register, followed by 23'h08E3EC, illustrating a 10V increase. The offset DAC with a value of 23'h08E3EC increases the output voltage by 10V for a data increase of 23'h0063EC compared to 23'h088000. After meeting the conditions of Fig. 13(b), experiments were conducted. As a result, the power voltage outputted 10V. The term "FORCE" is associated with channel 2. With a scale of 2V per block for channel 2, it can be inferred that each block represents an increase of 2V, resulting in a total increase of 10V across 5 blocks. After aligning the conditions in Fig. 13(b), we proceeded with the experiment. As a result, we set the force voltage to 10V. Subsequently, we observed that Fig. 13(a) and Fig. 13(b) matched, confirming the alignment of conditions. Voltage output at the DUT terminal on the Eval-board was measured.

Successfully achieved DC voltage output using the SPI interface of the ATE equipment and the DPS component.

4. Expanded Environments for Various DPS Evaluation

By establishing the system, we have confirmed the potential to utilize the AD5560 in an FPGA-based environment for the verification of various chips. This enables a universal evaluation of different DPS, and the constructed test environment is expected to be beneficial for testing new products in the future. The adopted approach, using Analog Devices' AD5560 with FPGA without the need for traditional PC software, contributes to the flexibility of applying changes to the DPS seamlessly. Even with alterations in the DPS specifications, modifying the Verilog-HDL code accordingly and synthesizing the Bitstream file allows the creation of a versatile DPS evaluation environment. This approach is anticipated to enhance the stability and performance of the system.