I. INTRODUCTION

In a battery management system (BMS), a voltage sensing integrated circuit (IC) is an essential block for monitoring the state of charge (SOC), which indicates the remaining power of the battery cells ^[1,2,3,4]. Fig. 1 illustrates the block diagram of the voltage sensing IC for BMS, which consists of a high voltage multiplexer (HVMUX) to select battery cells, a level shifter to scale down the high voltage of the battery cells, a voltage reference generator, and an analog-to-digital converter (ADC) ^[1]. Among these, the key building block is the ADC which requires high-resolution, and delta-sigma ADCs are well suited for the voltage sensing because they can achieve high accuracy through oversampling and noise shaping ^[5,6].

In the delta-sigma ADCs, an input feed-forward (FF) topology is widely used for high-resolution because it eases the design requirements of the integrators by processing the quantization noise only ^[7]. This allows for the reduction of quantization noise and the swing range of the integrators by employing a multi-bit digital-to-analog converter (DAC), and the DWA is used to correct the mismatch of unit capacitors in the DAC ^[8]. However, due to signal attenuation within the internal FF path, the comparator accuracy requirements become more challenging, and the load capacitance of the first integrator is affected by the quantizer, reducing power efficiency. Given these constraints, the modified FF topology ^[9,10], which removes the internal FF path, has emerged. The load capacitance of the first integrator is no longer affected by the quantizer, and simplified passive summing reduces signal attenuation.

In addition to the power efficient topology described above, the proposed architecture employs a modified 3-bit feedback DAC with data weight averaging (DWA). The modified DAC reduces the complexity of the DWA logic, thereby increasing power and area efficeincy. The proposed modulator is fabricated in a 180 nm CMOS process, and achieves a dynamic range (DR) of 102.4 dB and a Schreier figure-of-merit (FoM) of 165.3 dB.

The rest of this article is organized as follows: Section II explains the architecture of the proposed delta-sigma modulator. Section III discusses the details of the circuit implementation. The measurement results of the prototype modulator are presented in Section IV, and this article concludes with Section V.

Fig. 1. Block diagram of the voltage sensing IC for BMS.}

II. PROPOSED ARCHITECTURE

The architecture of the proposed delta-sigma modulator is shown in Fig. 2. The modulator employs the modified FF topology and consists of a first integrator, a second integrator with an analog signal processing block, $H_{A}({z})$, a 3-bit flash quantizer with a passive switched capacitor (SC) adder, and a feedback DAC with DWA. The output of the modulator, $D_{O}({z})$, and the outputs of two integrators, $V_{1}({z})$ and $V_{2}({z})$, are given by

where $V_{IN}({z})$ and ${Q}({z})$ indicate the input of the modulator and quantization noise, respectively. Thanks to the modified FF topology, integrators handle only quantization noise as shown in (2) and (3), which reduces the swing range of the integrators ^[9,10]. Also, due to $H_{A}({z})$ in the modified FF architecture, the design requirement of the comparators is relaxed, and power efficiency is increased.

For the feedback DAC, the proposed ADC adopts a modified 3-bit DAC with seven unit capacitors, removing one capacitor connected to ground, as shown in Fig. 3. In the modified DAC, all of the bottom plates of the capacitors switch only between $+ V_{REF}$ and $- V_{REF}$, which simplifies the DWA logic complexity. The DAC output ranges from $-7/7 V_{REF}$ to $+7/7 V_{REF}$ in steps of $2/7 V_{REF}$. To reduce the mismatch between unit capacitors, the conventional DWA technique is applied ^[8].

Fig. 2. Architecture of the proposed delta-sigma modulator.}

Fig. 3. The modified DAC with DWA and the output levels.}

III. CIRCUIT IMPLEMENTATION

1. Proposed Delta-Sigma Modulator

The overall schematic of the proposed delta-sigma modulator and its timing are shown in Fig. 4. The modulator is implemented in a fully differential structure and operates with two non-overlapping clocks, ${\phi} _{1}$ and ${\phi}_{2}$. In the first integrator, DWA is employed to minimize the capacitance mismatch, and its operation is as follows. In the ${\phi}_{1}$ phase, the flash quantizer determines the 3-bit digital output, and in the ${\phi}_{2}$ phase, the reference sampling capacitors are shifted according to the output code. Two additional clock signals ${\phi}_{3}$ and ${\phi}_{4}$ are employed to implement the transfer function $2-z^{-1}$of the second integrator.

Using the thermal noise analysis presented in ^[11], the sampling capacitance values for both integrators were determined. To reduce the degradation of modulator performance due to thermal noise, the total sampling capacitance of the first integrator is set to be 1.5 pF, that of the second integrator to 200 fF, and the input capacitance of the quantizer to 100 fF, since the thermal noise generated in the second integrator and the quantizer is shaped, allowing for smaller capacitor values ^[11].

A resistive-ladder (R-ladder) has been used on-chip to generate the reference voltage for the flash quantizer. Since static current is produced in the R-ladder, increasing the total resistance reduces power consumption. However, feedthrough caused by the input stage capacitance between the quantizer's input and the reference voltage leads to distortion in the ADC ^[12]. To address this, the maximum feedthrough at the midpoint of the R-ladder is limited to 0.1 LSB. The total resistance is determined by the following equation

(4)

$ R=\frac{4\phi }{\pi 2^nf_{in}C}, $

where $\phi $ is the feedthrough in LSB and $n$ is the resolution of the quantizer and $C$ is the total capacitance from the R-ladder, and $f_{in}$ is the input frequency of the quantizer ^[12]. As a result, the total resistance must be set below 1.18 M$\Omega$. Considering feedthrough and static current, a total resistance of 0.93 M$\Omega$ was chosen. This R-ladder occupies an area of 0.07 mm${}^{2}$.

Correlated double sampling (CDS) is employed in the first integrator to mitigate offset and flicker noise ^[13]. Furthermore, A system-level low-frequency chopping (CHL) technique suppresses the residual offset of the modulator by periodically inverting the polarity of the input and output ^[14]. Therefore, chopped switches are employed at the input and output paths. In this design, the chopped switch control clock, ${\phi}_{syschop}$, is used to enable one CHL transition in one conversion cycle. To match the polarity of the integration path between before and after the CHL transition, chopped switches are employed for the feedback capacitors. Additionally, the chopped switches are also employed in the sampling capacitors of the second integrator, except for the additional sampling capacitor, $C_{S2A}$, which is reset in the ${\phi}_{1}$ phase.

During the first reference sampling after the CHL transition, since the modulator output which provides feedback to the DAC has the same polarity as the previous state, a $\phi_{syschop\_d}$ clock signal is used to invert the output polarity of the feedback path to match the polarity of the input and feedback DAC ^[15]. This process modulates the systematic offset and removes it after passing through the decimation filter.

Fig. 4. The overall schematic of the proposed second-order modified FF delta-sigma modulator and its timing.}

2. Loop Filter

The schematic of the first integrator and its timing are shown in Fig. 5. Bootstrapped switches are employed to enhance input sampling linearity ^[16]. To reduce ADC gain error caused by the capacitance mismatch between the input sampling capacitor $C_{S1,1}[{k}]$ and the reference sampling capacitor $C_{S1,2} [{k}]$, a capacitor swapping technique is employed to average out the capacitance mismatch as follows: During one conversion cycle, the $C_{S1,1}[{k}]$ and $C_{S1,2} [{k}]$ arrays are swapped twice to ensure that the averaged capacitance is used for both input and reference sampling. The schematic of the second integrator with the transfer function, $2-z^{-1}$, and its timing are shown in Fig. 6. For the second integrator, three sampling capacitors are employed: two sampling capacitors $C_{S2,1}$, $C_{S2,2}$, and an additional capacitor $C_{S2A}$. During the following ${\phi}_{3}$ phase, $C_{S2,2}$ and $C_{S2A}$ are connected to integrate the output of the first integrator $V_{1}[{n}-{1}]$ without delay. At this time, the remaining $C_{S 2,1}$ samples the output of the first integrator. Then, during the subsequent ${\phi} _{1}$ phase, $C_{S2A}$ is reset. In the following ${\phi}_{4}$ phase, similar to the ${\phi}_{3}$ phase, the previously sampled $C_{S2,1}$ and $C_{S2A}$ are connected for integration. Finally, the output of the second integrator $V_{2} [{n}]$ becomes $2 \cdot V_{1} [{n}] - V_{1}[{n-1}]$, and this sequence of operations implements the transfer function $2-z^{-1}$.

Fig. 5. Schematic of the first integrator and its timing.}

Fig. 6. Schematic of the second integrator and its timing.}

IV. MEASUREMENT RESULTS

The prototype delta-sigma modulator is implemented in a 180 nm CMOS process. Fig. 7 shows the die micrograph of the proposed modulator. The core area is 0.53 mm${}^{2}$. Fig. 8 shows the power breakdown of the proposed modulator. From a 1.8 V supply, the modulator consumes 9.48 $\mu$W at 19.2 kHz sampling frequency. Fig. 9 shows the measured output spectrum of the proposed modulator with a 0.6 V DC input and input shorted, respectively. The measured DR is 102.4 dB and Fig. 10 shows the measured offset with and without CHL, and for this measurement, a sinc${}^{3}$ filter is implemented off-chip for decimation in MATLAB. The maximum offset from eight samples without CHL is 50 $\mu$V, and it drops below 6.86 $\mu$V with CHL. The measured performance of the proposed modulator is summarized and compared in Table 1.

Fig. 7. Die micrograph of the proposed modulator.}

Fig. 8. Power breakdown of the proposed modulator.}

Fig. 9. Measured output spectrum of the proposed modulator.}

Table 1. Performance summary and comparison table.

$^*$FoM$_{\rm s} =$ DR $+ 10\cdot\log_{10} ({\rm BW}/{\rm Power})$

V. CONCLUSION

This paper presents a second-order modified FF delta-sigma modulator for BMS DC measurement. The proposed modulator employs the modified 3-bit feedback DAC to reduce the complexity of the DWA logic, and a capacitor swapping technique is adopted to minimize the gain error from sampling capacitance mismatch. Additionally, the CDS and CHL techniques are applied to minimize offset and flicker noise. The prototype modulator, fabricated in a 180 nm CMOS process, achieved a DR of 102.4 dB, a resolution of 7 $\mu$V${}_{\rm rms}$, and an offset of 6.86 $\mu$V while consuming 9.48 $\mu$W.