Investigation of the Temperature Sensitivity and the Sensing Voltage Drift of the
Body Diode of SiC Power MOSFET
Kim,Taehyeon1,2
SongKinam1
KimKihyun1
LeeKyoungho1
KimJonghyun1
LeeSungsik2,*
KangInho1,*
-
(Power SoC Research Center, Korea Electrotechnology Research Institute (KERI), Korea)
-
(Department of Electronic Engineering, Pusan National University, Korea)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Power cycling test, SiC power MOSFET, body diode, junction temperature, temperature measurement
I. Introduction
In the recent years, the power cycling test (PCT) has been attracting attention to
evaluate the robustness of the chip and package assembly [1]. This applies thermal stress to a device under test (DUT) by continuously turning
it on/off as shown in Fig. 1. During this process, temperature changes occur as the DUT is turned on/off, which
creates thermal stress that can lead to major failure mechanisms such as cracking
and delamination of wire and chip bonding [2-6].
In the PCT, the mean temperature and the temperature swing of the power devices are
well known as the key parameters to make much impact on their lifetime [7]. To estimate the junction temperature (T$_{\mathrm{j}}$) of power device, the PCT
utilizes a Temperature Sensitive Electrical Parameter (TSEP) such as threshold voltage,
on-resistance, forward voltage drop of diode, and various transient-state parameters
[8-11]. Among these TSEPs, the forward voltage drop of body diode (sensing voltage, V$_{\mathrm{SENS}}$)
has been widely used for SiC MOSFET due to superior stability in relationship between
temperature and TSEP over long-term aging [5]. This means the forward voltage drop of body diode enables a consistent junction
temperature measurement over the lifetime of SiC MOSFET.
Fig. 2 shows the current flows in the SiC MOSFET during the PCT that employs the forward
voltage drop of the body diode as TSEP. The drain-source electrode is biased with
high constant current (heating current) in the turn-on time (powering cycle) and is
reverse-biased with a low constant current (sensing current, I$_{\mathrm{SENS}}$)
in turn-off time (sensing cycle). To guarantee an accurate measurement of T$_{\mathrm{j}}$
against the aging throughout the whole lifetime of SiC MOSFET, the sensing current
must flow through only body diode in the sensing cycle. However, the leakage current
through the channel beneath the gate oxide is known to be added and to affect the
current-voltage characteristic of the body diode of SiC MOSFET, which determines the
temperature sensitivity.
In the previous literatures that dealt with the forward voltage drop of body diode
as TSEP to precisely estimate T$_{\mathrm{j}}$, the sensing current is found to affect
the temperature sensitivity and linearity [12,13]. It is also found that the dynamic behavior of TSEP (TSEP drift over time) influences
accuracy of T$_{\mathrm{j}}$ because a long drift time makes over- or under-estimation
of T$_{\mathrm{j}}$ [6]. Therefore, an accurate estimation of T$_{\mathrm{j}}$ requires a thorough investigation
of the sensitivity of sensing voltage to temperature (or the sensitivity) and of the
sensing voltage drift over time with various sensing parameters.
In this paper, we will investigate the sensitivity and sensing voltage drift of commercial
SiC power MOSFET and develop a methodology to accurately estimate the temperature
of the MOSFET.
Fig. 1. Basic operation of power cycling test.
Fig. 2. Measuring junction temperature with a body diode in a SiC power MOSFET.
II. Experiment
Fig. 3 shows an in-house test setup used in this experiment. This setup is composed of three
components:
(a) an oven that adjusts the temperature of ambient surrounding DUT (T$_{\mathrm{a}}$).
In this work, it is assumed that DUT is in thermal equilibrium where T$_{\mathrm{j}}$
= T$_{\mathrm{a}}$ after another 3 minutes of the oven reaching target T$_{\mathrm{a}}$.
(b) a semiconductor parameter analyzer (Agilent 4156B) that measures the current-voltage
(I-V) curves and the voltage-time (V-t) curves of DUT.
(c) a PC that controls the oven and the Agilent 4156B and that acquires I-V and V-t
data.
To obtain the sensing voltage drift (${\Delta}$V$_{\mathrm{SENS}}$) and temperature
sensitivity ($S_{{T_{j}}}$), the experimental flow is as the follows. The V-t curves
were firstly measured at different I$_{\mathrm{SENS}}$ (80 ${\mu}$A, 40 mA, 80 mA)
and V$_{\mathrm{GS}}$ (0 V, $-$5~V, $-$10 V) to examine the effect of I$_{\mathrm{SENS}}$
and V$_{\mathrm{GS}}$ on V$_{\mathrm{SENS}}$ drift. Note that the reason why this
step is firstly executed is to determine a delay time for thermal equilibrium where
V$_{\mathrm{SENS}}$ is supposed to remain constant. Based on the V-t curves, the delay
time was determined. For the next step, the I-V curves of body diode were measured
at different V$_{\mathrm{GS}}$ from 0 V to $-$10 V with a step of $-$1 V after additive
delay time of the oven reaching a target temperature. This step was repeated at different
oven temperatures from 10$^{\circ}$C to 150$^{\circ}$C with a step of 20$^{\circ}$C.
Finally, the temperature sensitivity as a function of V$_{\mathrm{GS}}$ and I$_{\mathrm{SENS}}$
was calculated from the I-V curves of body diode. In this experiment, a commercially
available SiC MOSFET (C2M0080120D) was used as DUT.
Fig. 3. Setup for measuring I-V curves at various junction temperatures.
III. Results and Discussion
Aforementioned, the forward voltage drop of body diode was used as TSEP to estimate
the junction temperature in this work. In this case, the junction temperature can
be calculated from the forward voltage drop of body diode (V$_{\mathrm{DS}}$) or the
sensing voltage (V$_{\mathrm{SENS}}$) and the sensing current (I$_{\mathrm{SENS}}$)
based on the well-known diode equation [12,14]:
where k$_{\mathrm{B}}$ is the Boltzmann constant, q is the electron charge, I$_{\mathrm{SD0}}$
is the saturation current, a is a slope of T$_{\mathrm{j}}$-V$_{\mathrm{SENS}}$ curve,
and b is constant. Note that Eq. (1) is valid only within the range of sensing current where the log value of I$_{\mathrm{SENS}}$
is a linear function of V$_{\mathrm{SENS}}$. Otherwise, the estimation of T$_{\mathrm{j}}$
becomes inaccurate. This may be caused by (1) a resistance of diode that grows dominant when the diode operates in high-injection
level (I$_{\mathrm{S}}$> 10~mA) and (2) a leaky current path not through the body
diode at higher gate voltage [15].
Fig. 4 shows the source current (I$_{\mathrm{S}}$) versus drain-source voltage (V$_{\mathrm{DS}}$)
curves, which is the log-linear diode current of the DUT measured at room temperature
for V$_{\mathrm{GS}}$ from 0 V to -10 V. In Fig. 4, at higher gate bias (V$_{\mathrm{GS}}$ > -5 V), it is difficult to find a linear
region in the log-linear I-V curves. This is due to the persistence of leakage current
paths at higher gate biases (V$_{\mathrm{GS}}$ > -5 V). On the contrary, the log-linear
I-V curves for V$_{\mathrm{GS}}$ $\leq $ -5~V show a linear region in the range
of I$_{\mathrm{SENS}}$ from 10~nA to 1 mA and negligible change with respect to the
gate bias. The linearity with respect to gate bias, as discussed, can be examined
in greater detail in Table 1. To check the linearity, coefficient of determination (R$^{2}$) is used. R$^{2}$
is a statistical measure of the proportion of variance in the dependent variable that
is explained by the independent variables in a regression model. It has a value between
0 and 1. The closer it is to 1, the better the independent variable explains the dependent
variable [16]. As the gate bias decreases, it can be observed that R$^{2}$ approaches closer to
1. This indicates that the relationship becomes more linear. This means that the leakage
current path through the channel beneath the gate oxide is effectively quenched [17].
Fig. 5 and Table 2 show the sensing voltage over time and the sensing voltage drift at different sensing
currents and gate biases. The sensing voltage drift is defined as a difference between
sensing voltage at a measurement start and a sensing voltage at the moment of the
V-t curves showing no change, e.g., 3 minutes. The sensing voltage drift increases
with the sensing current for V$_{\mathrm{GS}}$ ${\leq}$ -5~V. Although a relatively
low I$_{\mathrm{SENS}}$ (80 mA) flows through DUT compared to the heating current
of 10 A, the sensing voltage decreased with the elapsed measurement time as shown
in Fig. 5. This means that the junction temperature also decreased with the elapsed measurement
time based on Eq. (1) and suggests that a self-heating generated by the sensing current still occurs, leading
to an inaccuracy of T$_{\mathrm{j}}$. For example, T$_{\mathrm{j}}$ error of 7.6$^{\circ}$C
is calculated if T$_{\mathrm{j}}$ is estimated for DUT biased at V$_{\mathrm{GS}}$
= -10~V and I$_{\mathrm{SENS}}$ = 80 mA. However, the change in ${\Delta}$V$_{\mathrm{SENS}}$
for different I$_{\mathrm{SENS}}$ and V$_{\mathrm{GS}}$ = 0 V (1.16 mV) is smaller
than those for V$_{\mathrm{GS}}$ = -5 V and -10 V (13.16~mV and 17.36 mV). This means
that the self-heating effect is reduced for V$_{\mathrm{GS}}$ = 0 V.
Fig. 6 shows investigation of the effect of the gate bias and the sensing current on the
linearity of T$_{\mathrm{j}}$-V$_{\mathrm{SENS}}$ curve and the sensitivity to T$_{\mathrm{j}}$,
the linear regression was carried out for sensing voltages measured at different junction
temperature from 10$^{\circ}$C to 150$^{\circ}$C.
In Fig. 6, R$^{2}$value extracted for higher gate voltage (0~V) and low sensing current (80
${\mu}$A) is so low that much error may occur if this condition is used to predict
T$_{\mathrm{j}}$. However, at higher sensing current (I$_{\mathrm{SENS}}$ > several
tens of mA), the influence of leakage current through the channel is negligible, resulting
in a high R$^{2}$value. This high R$^{2}$value indicates that a prediction model agrees
well with the experimental T$_{\mathrm{j}}$. Nevertheless, errors can occur at high
sensing currents due to self-heating, as discussed earlier. Therefore, it is noteworthy
that, unlike V$_{\mathrm{GS}}$ = 0 V, R$^{2}$ values extracted for I$_{\mathrm{SENS}}$
= 80 ${\mu}$A and 80~mA are nearly 1 for V$_{\mathrm{GS}}$ = -5 V. Therefore, the
channel of DUT must be quenched to achieve good linearity of T$_{\mathrm{j}}$-V$_{\mathrm{SENS}}$
curve that enhances an accuracy of T$_{\mathrm{j}}$.
Fig. 7 shows the dependency of the temperature sensitivity on the sensing current for different
gate biases. The temperature sensitivity ($S_{{T_{j}}}$) of is mathematically defined
by the following equation:
The temperature sensitivity at V$_{\mathrm{GS}}$ = 0 V increases with I$_{\mathrm{SENS}}$,
while these at lower V$_{\mathrm{GS}}$ (e.g. -5 V and -10~V) decreases with increasing
I$_{\mathrm{SENS}}$. Unfortunately, the origin of this opposing behavior has not been
identified. However, an increase in $S_{{T_{j}}}$ with I$_{\mathrm{SENS}}$ may be
related to a complex effect of self-heating and carrier detrapping in the channel
of SiC MOSFET with relatively higher interface trap density than Si MOSFET [18]. In this case, for V$_{\mathrm{GS}}$ = 0 V where the channel is still leaky, the
carrier (electron) trapped in the SiO$_{2}$/SiC interface can be released to promote
the conduction even for a small increase in junction temperature caused by self-heating.
Although sensitivity for higher V$_{\mathrm{GS}}$ are high, it is difficult to use
this bias condition (e.g. V$_{\mathrm{GS}}$ = 0 or near 0 V) to estimate the junction
temperature. This is because the conduction channel under the gate is still leaky
at higher V$_{\mathrm{GS}}$ ( > -5 V) for SiC MOSFET, leading to a degradation of
SiO$_{2}$/SiC interface and the I-V characteristics of body diode and therefore to
a change in T$_{\mathrm{j}}$-V$_{\mathrm{SENS}}$ characteristics.
Fig. 4. I-V curves of body diode of DUT measured at various gate biases (VGS).
Fig. 5. Sensing voltage over time at different sensing currents and gate biases: (a)
VGS = 0 V; (b) VGS = -5 V; (c) VGS = -10 V.
Fig. 6. Junction temperature versus sensing voltage along with a linear-fit curve
(red dotted line) and the coefficient of determination (R2) as a function of VGS and ISENS.
Fig. 7. Temperature sensitivity versus sensing current graph for VGS = 0 V, -5 V, and -10 V.
Table 1. R2 Values for body diode I-V curves at VGS = 0 V to -5 V (with range IS from 10 nA to 1 mA)
VGS(V)
|
R2
|
0
|
0.97459
|
-1
|
0.97908
|
-2
|
0.97918
|
-3
|
0.99156
|
-4
|
0.99955
|
-5
|
0.99993
|
Table 2. Sensing voltage drift (in mV) at different ISENS and different VGS
ISENS (mA) \ VGS (V)
|
0
|
-5
|
-10
|
0.08
|
3.68
|
0.68
|
0.48
|
40
|
4.24
|
7.98
|
7.72
|
80
|
4.84
|
13.84
|
17.84
|
IV. Conclusions
To accurately estimate the junction temperature of the power device, an experimental
methodology was developed by investigating the temperature sensitivity and sensing
voltage drift of the body diode of SiC power MOSFETs for different gate biases. The
sensing voltage drift increases with the sensing current for V$_{\mathrm{GS}}$ ${\leq}$
-5 V, while its change is small for V$_{\mathrm{GS}}$ = 0 V. The sensitivities and
the linearities of T$_{\mathrm{j}}$-V$_{\mathrm{SENS}}$ curve were improved for lower
sensing current and V$_{\mathrm{GS}}$ ${\leq}$ -5. This is attributed to reduction
in leaky current path through the channel of SiC MOSFET. Finally, it is concluded
that a precise Tj estimation requires a lower gate bias enough to close the channel
and a lower sensing current that must be in the linear region of I-V curve to enhance
sensitivity and accuracy.
ACKNOWLEDGMENTS
This work was supported by the Technology Innovation Program (or Industrial Strategic
Technology Development Program (CN#: 20017438) funded by the Ministry of Trade, Industry
& Energy (MOTIE, Korea)
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Taehyeon Kim received the B.S. degree in the department of semiconductor engineering
from Gyeongsang National University, Jinju, South Korea, in 2024. He is currently
pursuing the M.S. degree in the department of electronic engineering from Pusan National
University, Busan, Korea, through an academic-industrial cooperative program at the
Korea Electrotechnology Research Institute (KERI), Changwon, Korea. His research interests
include the electrical characterization and reliability evaluation of power semiconductor
devices.
Kinam Song received the B.S. and M.S. degrees in electronic engi-neering from
Gyeongsang National University, Jinju, South Korea, in 2008 and 2010, respectively.
From 2010 to 2016, he was an IC design engineer with Fairchild Semicon-ductor, Bucheon,
South Korea. From 2016 to 2019, he was a Principal Engineer with ON Semiconductor,
Bucheon, South Korea. From 2019 to 2023, he was a Sr. Principal Engineer with ON Semiconductor,
Phoenix, AZ, USA. Since 2023, he has been with the Korea Electrotechnology Research
Institute, Changwon, South Korea, where he is currently a Senior Researcher. His research
interests are wide-band gap gate drivers, digital isolators, galvanic isolation, smart
gate drivers, and diagnostic of a gate driver unit.
Kihyun Kim received the M.S. and Ph.D. degrees in electronic engineering from
Pusan National University, Korea, in 2004 and 2019, respectively. In 2004, he joined
Korea Electrotechnology Research Institute (KERI), Changwon, Korea, where he is currently
a principal researcher. His current research interests include high voltage IC and
power management IC for power converters.
Kyoungho Lee He received BS, MS, and Ph.D. degrees in electrical and electronics
engineering from POSTECH, Korea in 1997, 1999 and 2009 respectively. From 1999 to
2004 he worked at Hynix semiconductor. From 2008 to 2012 he was with Samsung electro-mechanics
as a senior engineer. In 2012 he joined KERI, and he has worked as a principal researcher.
He is interested in the design of PMIC for energy harvesting and the fully integrated
power converter.
Jonghyun Kim received a Ph.D. (1998) in Electrical Engineering from POSTECH, Pohang,
South Korea. From 1998 to 2002, He worked as a development engineer at Samsung Electro-Mechanics,
Korea. Since 2002, he has worked in the Korea Electrotechnology Research Institute
(KERI), Changwon, Korea. His current research interests include power electronics
based circuit and system design.
Sungsik Lee received the Ph.D. degree from University College London (UCL), London,
U.K., in 2013. From 2013 to 2017, he worked as a Research Associate with the University
of Cambridge, Cambridge, U.K. He has been a Professor with the Department of Electronics,
Pusan National University (PNU), Pusan, Republic of Korea, since 2017. His area of
expertise is semiconductor devices and physics for futuristic electronics. So far,
he has published over 80 articles in the related field, including the prestigious
journal ‘Science’ as the first author. In 2017, he was awarded the Best Teaching Prize
2017 from the Korean Society for Engineering Education (KSEE), Republic of Korea.
And he is currently the director of the Inter-university Semiconductor Research Center
(PNU-ISRC, called Ban-Gong-Yeon) for the regional semiconductor education and services.
Inho Kang received the M.S. and Ph.D degree in Electrical Engi-neering from Gwangju
Institute Science and Technology (GIST) in 1998 and 2004. He was senior researcher
in Samsung TECHWIN and developed a digital camera hardware and firmware for 2 years.
He has been with Korea Electrotechnology Research Institute (KERI) from 2005. His
current research interests include development of SiC power semiconductor devices
and electrical characterization and reliability estimation of them.