I. INTRODUCTION

The non-volatile memory (NVM) market has experienced consistent growth, driven by concurrent cost reductions. Additionally, the rapid expansion of mobile applications and the smartphone market has led to an increased demand for high-density NVMs. In particular, NAND flash memory has attracted considerable attention, thanks to its scalability, high reliability, and multilevel capabilities ^[1-5]. NAND flash memory consists of three dielectric layers: tunneling layer, charge-trapping layer (CTL), and blocking layer. The primary mechanism of NAND flash memory involves trapping and de-trapping channel electrons to the CTL through Fowler-Nordheim (FN) tunneling, effectively modulating the threshold voltage between the OFF and ON states ^[6-8].

Historically, NAND flash memory technology has utilized a poly-Si floating gate to store electrons ^[9-11]. However, electrons in the poly-Si floating gate exist as free electrons in the conduction band, leading to cell-to-cell interference when scaling down to around 1X nm technology. Moreover, the thickness of the floating gate is constrained by the gate coupling ratio ^[12,13]. In contrast, CTF memory, based on insulating films, has emerged as a potential replacement for the floating gate technology. This is attributed to its superior retention and endurance characteristics, as well as lower power consumption ^[14-19]. In particular, CTF technology has successfully addressed cell-to-cell interference issues in NAND flash applications. Furthermore, it has provided advantages by overcoming scaling limits through the application of a vertical stacked structure ^[20,21].

Recently, efforts have been directed towards enhancing the performance of CTF memory by incorporating various high-k materials (Si$_{3}$N$_{4}$, HfO$_{2}$, TiO$_{2}$, ZrO$_{2}$, Y$_{2}$O$_{3}$) as gate dielectric layers ^[22-27]. Among these materials, Si$_{3}$N$_{4}$ and HfO$_{2}$ are commonly employed. Si$_{3}$N$_{4}$ is preferred for its excellent electrical characteristics and reliability. However, its trapping efficiency decreases as the film thickness decreases, imposing limitations on scalability ^[28-31]. On the other hand, HfO$_{2}$ is considered a promising candidate due to its high permittivity and thermal stability ^[32-35]. Furthermore, HfO$_{2}$ demonstrates a higher trap density, leading to a larger memory window, yet it is accompanied by reliability issues. Research has also been conducted to enhance charge trapping efficiency by either doping Aluminum atoms into HfO$_{2}$ or stacking them with Al$_{2}$O$_{3}$ ^[36-38]. While physical scaling has been achieved through the vertical stacked structure, logical scaling encounters limitations due to constraints in the memory window and reliability issues.

Additionally, the blocking layer is crucial in preventing the loss of charges vertically in the charge trapping layer. The utilization of SiO$_{2}$ as the blocking layer provides excellent interface state properties, but requires incorporating high-k materials, such as Al$_{2}$O$_{3}$, so as to address gate leakage during the programming process ^[39-42]. Al$_{2}$O$_{3}$ also has the advantage of good chemical stability and large band offset with Si -^[43]. Nevertheless, Al$_{2}$O$_{3}$ exhibits inferior interface state properties when compared to SiO$_{2}$, containing a notable quantity of traps within the thin film. Consequently, ongoing endeavors to optimize the layer stack remain imperative.

In this study, we conducted a thorough analysis of the characteristics of a TiN/Al$_{2}$O$_{3}$/HfO$_{2}$/SiO$_{2}$/Si (TAHOS) stack capacitor, which is most commonly used gate stack in flash memory technologies, under various post-deposition annealing (PDA) and forming gas annealing (FGA) conditions. We compared eight different conditions to investigate the impact of temperature and the type of annealing. Firstly, we examined the trends in memory window and flat band voltage (V$_{\mathrm{fb}}$) based on various PDA conditions, focusing on oxide trap behavior. Secondly, we assessed the influence of interface traps by analyzing the C–V characteristics at different frequencies. Finally, we compared the results of PDA + FGA with those obtained from only PDA case. The goal of this study was to identify the optimal conditions for the TAHOS stack based on the annealing parameters.

II. DEVICE CHARACTERISTICS

Fig. 1 illustrates the fabrication process and top-view optical image of a capacitor with the TAHOS stack. Firstly, a 4-nm-thick SiO$_{2}$ layer was formed on a 6-inch p-type Si wafer by dry oxidation process. Subsequently, 6-nm-thick HfO$_{2}$ and 10-nm-thick Al$_{2}$O$_{3}$ layers were sequentially deposited using atomic layer deposition (ALD). After that, the wafer was divided into several dies to accommodate different annealing conditions. PDA was carried out for 10 seconds using N$_{2}$ gas in the temperature range of 900 $^{\circ}$C to 1050 $^{\circ}$C. The samples subjected solely to post-deposition annealing (PDA) were designated as S1 to S4 based on temperature conditions. A shadow mask with a diameter of 200 ${\mu}$m was affixed, and a 50-nm-thick layer of TiN was deposited using sputtering. Subsequently, a 25-nm-thick layer of Pt was deposited for the top electrode contact using an e-beam evaporator to prevent potential scratching or abrasion of the TiN. Finally, FGA was conducted for 10 minutes using H$_{2}$ (5%) at 450 $^{\circ}$C. The devices subjected to both PDA and FGA were designated as S5 to S8, corresponding to PDA temperature conditions. Table 1 provides the summary of the samples employed in this study along with their respective annealing conditions.

The electrical characteristics of the fabricated TAHOS capacitor were measured at 100 kHz using the B1520A (Multi Frequency Capacitance Measurement Unit, MFCMU) and a source measure unit (B1517A having maximum slew rate of 0.2 V/${\mu}$s) of Keysight B1500A semiconductor parameter analyzer.

Fig. 1. Schematic of fabrication process and optical microscopic image of TAHOS (TiN/Al2O3/HfO2/SiO2/Si) capacitor.

III. POST DEPOSITION ANNEALING (PDA)

To assess the impact of PDA on the TAHOS capacitor, C–V characteristics of cells in their pristine state were measured. Fig. 2(a) shows the normalized pristine C-V measurement results of the fabricated capacitors using different PDA temperatures under N$_{2}$ atmosphere (S1 ~ S4). The capacitance values were normalized using the accumulation capacitance (C$_{\mathrm{ox}}$). Measurements were carried out with the gate voltage (V$_{\mathrm{g}}$) sweeping from -3~V to 1 V to suppress the potential charge trapping effect. The AC signal frequency was set to 100 kHz, and the AC voltage was maintained at 0.03 V. All C-V curves exhibited the typical high-frequency MOS capacitor characteristics. In Fig. 2(b), to analyze temperature trends comprehensively, measurements were conducted on 10 devices for each condition, and V$_{\mathrm{fb}}$values for 10 devices were extracted based on various annealing temperature conditions. V$_{\mathrm{fb}}$ was determined at the point where C/C$_{\mathrm{ox}}$reached 0.6 to extract exact V$_{\mathrm{fb}}$. As the annealing temperature increased, V$_{\mathrm{fb}}$ shifted in the positive direction. This observation suggests that with increasing temperature, the positive oxide charge contributing to the negative shift in V$_{\mathrm{fb}}$ of the TAHOS capacitor tends to decrease. As a consequence of high-temperature annealing, there was a reduction in oxide charge, leading to a positive shift.

Fig. 2(c) presents the C-V characteristics of S1 sample at various V$_{\mathrm{g}}$values. The measurements involved sweeping the voltage from positive to negative and then back to positive, revealing a counterclockwise hysteresis loop indicative of charge trapping occurring. The memory window exhibited a rapid increase with higher V$_{\mathrm{g}}$. Specifically, when the sweeping voltages range from ${\pm}$3 V to ${\pm}$10 V, the measured memory window was changed from 0.15 V to 5.1 V. As the sweeping voltage exceeds 10 V, the memory window starts to saturate, reaching its maximum value at 15 V. The memory window values were extracted from points where the C/C$_{\mathrm{ox}}$ value was 0.6 at each voltage. The memory window increases linearly and saturates after a certain voltage, as depicted in Fig. 2(d). This suggests the occurrence of charge trapping and de-trapping within the HfO$_{2}$ layer during the V$_{\mathrm{g}}$ sweep.

Fig. 3(a) shows the C-V hysteresis, swept from V$_{\mathrm{g}}$ of - 10 V to +10 V and then back to -10 V. In Fig. 3(b), the distribution of memory windows is depicted, measured across 10 devices. The memory window in the C-V curve was defined as the difference between V$_{\mathrm{fb}}$ of the program and erase states. These values were obtained by double sweeping V$_{\mathrm{g}}$ from -10 V to 10 V. As the annealing temperature increases, there was a gradual decrease in the memory window. This phenomenon can be attributed to the reduction in charge trap density with the elevation of temperature. To verify this decrease in charge trap density, the formula for charge trap density (N$_{\mathrm{t}}$) was utilized. N$_{\mathrm{t}}$ for the fabricated capacitor can be estimated using the following equation ^[44-49]:

where C$_{\mathrm{ox}}$ denotes the capacitance value of the accumulation region, A represents the effective device area (gate electrode area was 10,000${\pi}$ ${\mu}$m$^{2}$), and $\Delta $V$_{\mathrm{fb}}$ corresponds to the memory window value obtained through hysteresis. The charge trap density in the TAHOS capacitor was measured for four samples under an applied voltage of ${\pm}$10 V. Utilizing the provided Eq. (1), the estimated charge trap density was 2.24 ${\times}$ 10$^{13}$ cm$^{-2}$ and 4.95 ${\times}$ 10$^{12}$ cm$^{-2}$ for S1 and S4, respectively. These results suggest a decreasing trend in charge trap density with increasing annealing temperature. Additionally, the calculated values for S2 and S3 were 1.05 ${\times}$ 10$^{13}$ cm$^{-2}$ and 7.12 ${\times}$ 10$^{12}$ cm$^{-2}$, respectively. This implies that a broader memory window becomes evident when the charge trap density is higher, facilitating the storage or release of charge in the capacitor. The memory window was most extensive in S1, characterized by the highest charge trap density, and was the narrowest in S4.

Fig. 2. (a) Measured C-V characteristics of 4 samples (S1 ~ S4) in their pristine states; (b) Distributions of Vfbextracted from 10 devices per each condition; (c) C-V curves of S1 sample with respect to the gate voltage sweep range; (d) Extracted memory window according to gate sweep voltage.

Fig. 3. (a) C-V curves for samples (S1 ~ S4) measured under the same Vgsweep range from −10 V to 10 V; (b) Memory window distributions extracted from 10 devices per each sample.

IV. FORMING GAS ANNEALING (FGA)

To investigate the impact of forming gas annealing, an additional annealing step was performed using H$_{2}$ gas at 450 $^{\circ}$C for 10 minutes. C-V characteristics of the fabricated capacitors under various PDA + FGA conditions were measured. In Fig. 4(a), the pristine C-V characteristics are presented for samples after forming gas annealing (S5 ~ S8). Fig. 4(b) shows V$_{\mathrm{fb}}$ distributions of each sample, comparing V$_{\mathrm{fb}}$ before and after FGA. It was consistently observed that V$_{\mathrm{fb}}$ increased in all samples after performing FGA following PDA. This can be attributed to the passivation of fixed oxide charge and interface trapped charge by FGA. Due to the decrease in interface traps, the slope of the C-V graph increases in depletion region, and additional annealing at 450 $^{\circ}$C leads to defect passivation, resulting in the flat band voltage shifting in a more positive direction.

Fig. 4(c) shows the C-V hysteresis measured through a double sweep of V$_{\mathrm{g}}$ from -10 V to 10 V, and the memory window distributions of each sample were extracted in Fig. 4(d), comparing the results with and without FGA. With an increase in the PDA temperature, the reduction in the memory window remained consistent, irrespective of whether FGA was conducted. The annealing at elevated temperatures resulted in a decrease in trap density as the temperature rose, gradually diminishing the memory window at the same sweep voltage.

To see the effect of the interface trap, various measurements were made while increasing the frequency from 1 kHz to 1 MHz. Fig. 5(a) and (b) depict the C-V characteristics of sample S1 and S5, respectively, depicting the cases where the FGA process was not performed and where it was performed. Without FGA process, the C-V curve exhibited a pronounced hump in the transition region below 100 kHz, introducing inaccuracies in the extraction of V$_{\mathrm{fb}}$. This inaccuracy led to a negative V$_{\mathrm{fb}}$ shift, significantly deviating from the ideal C-V characteristic. The presence of this hump is attributed to the behavior of TAHOS capacitors with defective interfaces, where interface traps capture or emit electrons, forming interface trap capacitance particularly at lower frequencies. At high frequencies, the interface trap remained unresponsive to small AC signals, rendering its effect less apparent. Nevertheless, after FGA, it became evident that the hump phenomenon was mitigated, attributed to a reduction in interface traps. Consequently, the variation in V$_{\mathrm{fb}}$ across different frequencies was minimized. The hump phenomenon induced by interface traps at low frequencies was found to occur irrespective of the PDA temperature. As seen in Fig. 6(a), all samples (S1 ~ S4) at 1 kHz, each annealed at different PDA temperatures, exhibited the hump phenomenon. However, in Fig. 6(b), as observed in the measurements for samples (S5 ~ S8), these hump phenomena consistently decreased upon performing FGA -^[50]. The reduction of interface traps stands out as one of the key failure mechanisms influencing charge loss in capacitors. To assess whether the reduction of interface traps enhances retention characteristics, retention tests were conducted on samples S1 and S5. The program and erase operations were executed at 20 V (pulse width of 1 ms) and -15 V (pulse width of 2 ms), respectively. Fig. 7 illustrates the retention characteristics of S1 and S5 measured at room temperature (300 K). When HfO$_{2}$ is employed as a charge trapping layer, as in previous studies, the retention characteristics are suboptimal due to shallow traps. However, with the implementation of FGA, it is evident that charge loss was improved by nearly 20%.

Fig. 8 illustrates C-V characteristics of the pristine state under different annealing conditions. As annealing progresses, two distinct characteristics emerge. Firstly, the slope of the C-V graph increased in comparison to the cell without any annealing process (denoted as As Dep.). This phenomenon is attributed to the presence of interface traps, causing fluctuations in capacitance due to the capture and emission of electrons, resulting in a lowered slope. Also, as PDA proceeded, V$_{\mathrm{fb}}$ gradually increased due to the reduction of positive oxide charge and interface traps. Lastly, V$_{\mathrm{fb}}$ affected by positively charged interface traps was passivated after FGA, leading to a further positive shift.

Fig. 4. (a) C-V curve for samples (S5 ~ S8) in pristine states; (b) Changes of Vfbdistributions before and after FGA; (c) C-V curve for samples (S5 ~ S8) measured under the same gate sweep voltage range from −10 V to 10 V; (b) Changes of memory window distributions before and after FGA.

Fig. 5. C-V characteristics with respect to various frequencies: (a) without FGA (sample S1); (b) with FGA (sample S5).

Fig. 6. C-V characteristics at 1 kHz: (a) with and (b) without FGA, demonstrating the passivation effect of interface traps.

Fig. 7. Retention characteristics of samples with PDA (S1, black) and PDA+FGA (S5, red) conditions.

Fig. 8. C-V characteristics of samples in pristine states (As Dep., PDA, and PDA+FGA conditions).

V. CONCLUSIONS

In this study, TAHOS stacked MOS capacitors were fabricated under various annealing conditions. A total of 8 splits were conducted, varying gas types and temperature conditions, and the basic characteristics were systematically analyzed. Specifically, in the PDA condition, variations in V$_{\mathrm{fb}}$ and memory window were investigated with respect to different annealing temperatures through charge trap density analysis. The impact of the FGA was assessed by examining the reduction in interface traps through C-V characteristics at various frequencies. Furthermore, V$_{\mathrm{fb}}$ and memory window characteristics were measured and analyzed both before and after FGA implementation. Consequently, performing FGA in conjunction with PDA at an appropriate temperature can lead to enhanced memory characteristics.