1. Proposed Approximate 4-2 Compressor with Error Recovery Logic

The Momeni compressor is an approximate 4-2 compressor that simplifies its design by eliminating one input C$_{in}$ signal and one output C$_{out}$ signal of an exact 4-2 compressor ^[24]. This simplification leads to reduced logic complexity and lowers hardware costs, requiring only three NOR gates for Carry generation and two XNOR gates, along with one OR gate, for Sum computation. Additionally, Seok et al. have further optimized the Momeni compressor, enhancing hardware efficiency by leveraging compound gates, known for their cost-effectiveness compared to regular gate combinations ^[28]. To achieve this, De Morgan’s law was employed to minimize the expressions of the Carry and Sum signals, leading to the Seok compressor necessitating only two compound gates along with a NOT gate (i.e., inverter). Although the Momeni and Seok compressors provide a hardware-efficient implemen-tation of approximate multipliers, they suffer from a significant drawback related to poor accuracy. Table 1 presents the truth table for the Momeni compressor, considering all possible input combinations. This compressor exhibits output errors when the input X$_{\mathrm{4\colon 1}}$ is either 0000, 0011, 1100, or 1111. The compressor's inputs are derived from the partial products of the two multiplier operands, and due to the nature of partial products involving AND operations, each bit's probability of being 0 or 1 is 3/4 or 1/4, respectively. This implies that the likelihood of each input case for the compressor, under uniformly distributed input patterns of the multiplier, depends on the count of zeros and ones. For instance, considering the input pattern X$_{\mathrm{4\colon 1}}$ = 0101, the probability of occurrence is calculated as 3/4 ${\times}$ 1/4 ${\times}$ 3/4 ${\times}$ 1/4 = 9/256, equivalent to 3.5%, as shown in Table 1. Certainly, in this context, our primary observation is that the Momeni compressor introduces an error in its Sum signal in the most likely input pattern X$_{\mathrm{4\colon 1}}$=0000, with an occurrence probability of 81/256, representing 31.6%, thereby substantially degrading the overall accuracy of approximate multiplications.

In this regard, to improve the accuracy by rectifying the output for the input pattern X$_{\mathrm{4\colon 1}}$=0000, we introduce a specialized error recovery logic designed for this compressor. The proposed recovery logic ensures that the compressor output Sum is adjusted to 0 from 1 when the input pattern X$_{\mathrm{4\colon 1}}$ equals 0000, correcting the Sum signal while keeping the Carry signal unchanged. Therefore, the truth table of the proposed compressor is identical to that of Momeni, except for the input X$_{\mathrm{4\colon 1}}$ = 0000. The proposed compressor is characterized by the following equations:

To realize these equations in digital logic, the proposed compressor design demands a few additional logic gates compared to the conventional counterpart. Fig. 1 illustrates the implementation of the proposed compressor design. In contrast to the traditional compressor, which employs two compound gates (AO221 and OA22) along with an inverter, the proposed design integrated an additional compound gate (OA21) and a three-input OR gate for the error recovery, as depicted in Fig. 1. Additionally, it is noteworthy that our error recovery logic can also be realized using a four-input OR gate and a two-input AND gate. In the following sections, we particularly used the former design of the two error recovery logic configurations. Consequently, the proposed compressor yields identical Sum and Carry outputs to the conventional design for all input patterns as listed in Table 1, except in the case of X$_{\mathrm{4\colon 1}}$=0000. In this specific case, the proposed compressor generates the accurate Sum and Carry values, both being 0, thereby enhancing the overall accuracy.

Fig. 1. Proposed approximate 4-2 compressor.

2. Proposed Approximate Multiplier Architecture

To build an N${\times}$N approximate multiplier using compressors, two primary schemes for partial product reduction, namely the C-N and C-FULL configurations, are commonly employed. These reduction schemes aim to reduce the partial product matrix height to two rows, which are then summed up by an adder to produce the final multiplication output. The C-N configuration incorporates approximate 4-2 compressors solely in the N least significant columns of the partial product matrix to minimize errors. On the other hand, the C-FULL configuration utilizes compressors across all columns in the matrix to optimize hardware efficiency at the expense of reduced accuracy.

Fig. 2 shows the proposed architecture of approximate multipliers designed for 8${\times}$8 multiplications, employing two distinctive partial product reduction schemes. In the C-N configuration, illustrated in Fig. 2(a), the higher-order N-1 columns employ exact 4-2 compressors, full adders, and half adders to yield accurate N most significant bit (MSB) multiplication outputs. Simultaneously, the lower-order N columns utilize approximate alternatives along with half adders to produce N least significant bit (LSB) approximate outcomes. Importantly, the proposed compressors are exclusively deployed in the most significant column of the N least significant columns of the partial product matrix while the remaining columns adhere to the conventional compressor designs. This proposed configuration enhances overall accuracy while maintaining hardware efficiency. In the C-FULL configuration, as depicted in Fig. 2(b), we replace the traditional compressors with the proposed alternatives in the N-1 most significant columns to enhance accuracy while the traditional compressors remain unchanged in the N least significant columns. Consequently, in the proposed multiplier architectures, three and eight conventional compressors are replaced with the proposed compressors equipped with error recovery logic in the C-N and C-FULL configurations, respectively. It is noteworthy that our multiplier architecture is rather scalable and can be readily applied to wider multiplications beyond the 8${\times}$8 scale.

Fig. 2. Proposed approximate multiplier architecture using two partial product reduction schemes for 8×8 multiplication: (a) C-N configuration using the proposed compressor only in the most significant columns of the N least significant columns in the partial product matrix; (b) C-FULL configuration using the proposed compressor in the N-1 most significant columns.

1. Computation Accuracy Performance Analysis

The normalized mean error distance (NMED) and mean relative error distance (MRED) serve as standard error metrics for evaluating the accuracy performance of approximate multipliers. These metrics were calculated for all considered multipliers across the entire range of possible input combinations, as defined by the following equations:

where n represents the number of bits of the multiplier and the error distance is defined as ED$_{i}$={\textbarM}$_{i}$-M’$_{i}${\textbar}, in which M$_{i}$ and M’$_{i}$ correspond to the exact output and the approximate output for the (i)$^{th}$ input data, respectively ^[23].

Fig. 3 shows the NMED and MRED values of various multipliers under both the C-N and C-FULL configurations. Under the C-N configuration, our proposed multiplier demonstrates superior performance in NMED compared to the other five approximate alternatives while the Pei multiplier exhibits the worst NMED performance.

Fig. 3. Accuracy performance comparison: (a) NMED of multipliers with C-N configuration; (b) MRED of multipliers with C-N configuration; (c) NMED of multipliers with C-FULL configuration; (d) MRED of multipliers with C-FULL configuration.

Moreover, the MRED of the proposed multiplier is comparable to that of the Akbar1 multiplier, falling between the values for Momeni/Pei and Akbar2/Venka multipliers. Specifically, when compared to the Pei multiplier, which exhibits the worst NMED and the second-worst MRED performance, our proposed multiplier achieves a remarkable reduction of 79.94% and 49.27% in NMED and MRED, respectively. Moreover, it achieves reductions of 23.84% in NMED and 49.94% in MRED when compared with the Momeni multiplier. A similar trend is found in the multipliers under the C-FULL configuration, with our proposed multiplier surpassing the other counterparts in NMED performance, while the Pei multiplier exhibits the least favorable performance. Additionally, our multiplier aligns with those of the Akbar2 and Venka multipliers, demonstrating the best MRED performance, while the Momeni multiplier exhibits the least favorable MRED value. Remarkably, the proposed multiplier achieves notable reductions of up to 89.81% and 97.10% in NMED and MRED, respectively, compared to the other five counterparts considered in this paper.

Overall, the observed trend indicates that the proposed multiplier performs notably better under the C-FULL configuration than the C-N alternative. As depicted in Fig. 2, while the NMED of our multiplier is comparable to that of the Akbar2 and Venka multipliers under the C-N configuration, it exhibits a substantial reduction of 51.40% and 48.26% in NMED, respectively, when compared to those under the C-FULL configuration. In summary, the proposed error recovery logic effectively enhances the accuracy performance of the multiplier by rectifying output errors from the compressor.

2. Hardware Performance Analysis

Table 2 shows the hardware performance of the exact and approximate compressors. The hardware performance metric includes area, power, critical path delay, and PDP. The proposed compressor outperforms the exact compressor in each metric by 59.50%, 73.13%, and 52.50%, respectively. Additionally, the PDP achieved a reduction of up to 87.39%. When compared to the Momeni compressor, the compound gate decreases area and power by 34.75% and 39.22%, even with error recovery logic incorporated.

Table 3 provides an overview of the hardware performance of the approximate multipliers, considering the aforementioned four hardware metrics. It is worth noting that the proposed multiplier adopts the proposed C-N and C-FULL configurations, as shown in Fig. 2, while the existing multipliers employ the conventional C-N and C-FULL alternatives in ^[17]. In the C-N configuration, our proposed multiplier demonstrates the most efficient performance in terms of area and the second-best performance in power and PDP. On the contrary, the Momeni multiplier consistently performs least favorably across all hardware metrics. This result indicates that the compound gates are more hardware-efficient than the regular logic gate combinations ^[28]. Specifically, our multiplier achieves notable reductions of up to 12.72%, 10.78%, and 10.78% in area, power, and PDP, respectively, compared to the other five designs. Under the C-FULL configuration, a similar trend persists, with our multiplier occupying the smallest area and showcasing the second-best perfor-mance in power and PDP. The Venka multiplier exhibits the least favorable performance in terms of area and PDP, while the Momeni multiplier consumes the highest power. Notably, the Pei multiplier excels in power and PDP, demonstrating the most efficient performance in these aspects.

Furthermore, for a comprehensive evaluation of the accuracy and energy efficiency tradeoff in the approximate multipliers, we utilize a figure of merit (FOM) that takes into account energy, area, delay, and NMED, as defined in ^[29]. The FOM is defined by:

The FOM values are presented in Table 3, where a lower FOM value indicates a more favorable tradeoff performance. Notably, upon analysis, our proposed multiplier stands out as the most efficient design when considering both accuracy and hardware aspects. In contrast, the Pei multiplier demonstrates the least favorable tradeoff performance under both configurations. Specifically, the proposed multiplier exhibits an 80.52% and 91.26% reduction in FOM factor under the C-N and C-FULL configurations, respectively, compared to the Pei alternative. Overall, these results underscore the well-balanced nature of the proposed multiplier in achieving accuracy while maintaining hardware efficiency.