1. The Proposed LED Driver Circuit
Top diagram of the proposed driver is shown in Fig. 1. First, NMOS resistor array (NRA) generated LED current I$_{\mathrm{LED}}$ whose
dc quantity is defined by the control signal B$_{\mathrm{I \_ LED}}$ and whose duty-cycle
is defined by the control signal B$_{\mathrm{D \_ LED}}$. The current control is performed
in all-digital way by adjusting the number of NMOS resistors in the array. The current
calibration code (CLB) is provided by the NRA calibrator which detect the process
variation of the circuit.
Fig. 1. Top structure of the proposed LED driver.
The PWM based boost convertor keeps V$_{\mathrm{LED \_ C}}$ to V$_{\mathrm{ref}}$
by the closed loop operation and generates V$_{\mathrm{OUT}}$which is determined by
the I$_{\mathrm{LED}}$and the LED’s I-V characteristics. The control loop consists
of a comparator, counter, digital loop filter (DLF) and pulse-width modulation (PWM)
signal (SW) generator. PW predictor initializes PWM control code (PW$_{\mathrm{SW}}$)
by calculating its initial code (PW$_{\mathrm{PRD}}$) with control inputs (B$_{\mathrm{I
\_ LED}}$, B$_{\mathrm{D \_ LED}}$, B$_{\mathrm{V \_ LED}}$, and B$_{\mathrm{R \_
LED}}$) with proposed PW prediction technique. B$_{\mathrm{V \_ LED}}$ and B$_{\mathrm{R
\_ LED}}$ are turn on voltage and equivalent resistance of LED, respectively, which
are typically obtained from the LED datasheet.
2. NMOS Resistor Array & Calibrator Circuit
Conventional current control circuit adopts digital-to-analog converter (DAC) [9] and reduces power consumption of current DAC by taking high current amplification
ratio with large output driving transistor. However, the output transistor experiences
a larger V$_{\mathrm{GS}}$ change with wider output current range, and necessarily
needs a high V$_{\mathrm{DS}}$ to remain in a saturation region. In addition, the
duty-cycling of the current sources needs additional settling time for analog node
voltages.
In this work, we use NMOS transistor as a resistor for direct output driving current
generation. The unit cell of NRA is shown in Fig. 2. The unit cell consists of k+1$^{\mathrm{th}}$ stacked NMOS transistors and control
logics. Stacked transistor minimizes the area consumption while achieving high resistance
for a precise current control. The calibration code CLB[0:k] adjusts the number of
NMOS transistors turned on so that the current flowing from each unit cell is 1 mA.
DUTY signal is LED duty-cycling signal based on B$_{\mathrm{D \_ LED}}$ input, and
collectively turns on and off all the NMOS resistors selected with CLB. One digit
of T$_{\mathrm{I \_ LED}}$ controls one unit cell, and a total of 100-unit cells are
used to generate 1-100 mA current.
Fig. 2. Unit cell of NMOS resistor array.
The proposed all digital control not only eliminates static power consumption for
LED current generation but also facilitate accurate duty-cycle control. In addition,
since the V$_{\mathrm{LED \_ C}}$ is fixed to V$_{\mathrm{ref}}$, the power efficiency
is maximized by minimizing the V$_{\mathrm{DS}}$ of the transistors regardless of
the change in I$_{\mathrm{LED}}$ or LED turn-on voltage.
The NRA calibrator circuit and its timing diagram are shows in Fig. 3 and 4. V$_{\mathrm{LED \_ C}}$ is sampled in the C$_{\mathrm{CLB}}$ with SPL signal and
discharged through NRA replica with DSC signal. NRA replica is designed to draw five
times smaller current than NRA unit cell to reduce power consumption. Then the capacitor
voltage V$_{\mathrm{CLB}}$ and V$_{\mathrm{CLB \_ REF}}$ are compared with the rising
edge of SEN with a clocked comparator. Therefore, RC-discharging time defined by C$_{\mathrm{CLB}}$
and NRA replica is compared to the half clock period(1/2${\cdot}$T$_{\mathrm{CLK}}$$_{\mathrm{IN}}$),
and the NRA resistance variation can be extracted.
Fig. 4. Timing diagram of NRA calibrator.
However, the comparison result also includes the impact of process variation of C$_{\mathrm{CLB}}$.
We adopt the look-up table (LUT) to remove it. First, the comparator output is integrated
to up/down counter and its k+1 most significant bits (MSBs) are used for CNT$_{\mathrm{CLB}}$.
Then, LUT translates CNT$_{\mathrm{CLB}}$ to final NRA calibration code CLB. Fig. 5 shows the CNT$_{\mathrm{CLB}}$-CLB transfer curve for the LUT. It was designed by
linearly approximating each of the 5 process corners simulation results.
Fig. 5. Fitting curve for LUT design.
3. Boost Converter
Fig. 6 shows designed inductor-based boost converter circuit. The CMOS controlled rectifier
(CCR) and level shifter are used to increase power efficiency of the converter [10]. External inductor of 5 ${\mu}$H is used for L$_{\mathrm{S}}$ whose series resistance
is 18.4~m${\Omega}$ (Bourns, SRR6040A5R0Y). External capacitor of 200 ${\mu}$F is
used for C$_{\mathrm{OUT}}$ to minimize the change in I$_{\mathrm{LED}}$ due to V$_{\mathrm{OUT}}$
ripple to within 1%. Therefore, since the minimum average I$_{\mathrm{LED}}$ is 1
${\mu}$A at 1 mA output current and 0.1% duty, the required DLF bandwidth for stability
should be very low, because of the low frequency output pole at V$_{\mathrm{OUT}}$,
which significantly increases the settling time.
Fig. 6. Circuit diagram of the boost converter.
The circuit diagram of the DLF is shown in Fig. 7 The proposed PW predictor, which will be described in the next section, provide calculated
target pulse width (PW$_{\mathrm{PRD}}$) for the fast settling. Since the integrator
value of DLF should be overwritten with PW$_{\mathrm{PRD}}$ only when there is a difference
from the target value, whether to update the integrator value is determined by comparing
the current and past PW$_{\mathrm{PRD}}$. Loop filter output PW$_{\mathrm{SW}}$ has
8-b resolution and the period of the PWM switching signal SW (T$_{\mathrm{SW}}$) is
256${\times}$T$_{\mathrm{CLKIN}}$.
Fig. 7. Circuit diagram of the digital loop filter.
The proportional gain ${\alpha}$ and the integral gain ${\beta}$ of the DLF can be
determined as follows. First, the control-to-output transfer function G$_{\mathrm{vd}}$(s)
can be obtained by setting the input voltage change $\widehat{v_{in}}\left(s\right)$
to zero and solving the transfer function from the change $\hat{d}\left(s\right)$of
the duty cycle of SW$_{\mathrm{OUT}}$ to the output voltage change $\widehat{v_{out}}\left(s\right)$[11].
In (2) and (3), D is the duty cycle of SW$_{\mathrm{OUT}}$, R$_{\mathrm{LED}}$ is the load resistance,
and R$_{\mathrm{e}}$ is the effective resistance of M$_{\mathrm{SW}}$. The designed
boost converter operates in discontinuous conduction mode (DCM). In DCM, the voltage
conversion ratio of the boost converter is a function of the switch's operating duty
ratio, switching period, inductance, and load resistance [11]. The relationship between the current and voltage of an LED can be expressed by the
following equation [13]:
To derive the load resistance, LED is modeled as a resistor R$_{\mathrm{LED}}$ with
a turn-on voltage V$_{\mathrm{on}}$ as follows.
In (4), I$_{\mathrm{S}}$, V$_{\mathrm{F}}$ and I$_{\mathrm{F}}$ are the reverse bias saturation
current, forward voltage and forward current specified in the LED’s datasheet, respectively.
Lastly, due to the large capacitance of the output stage, it is considered as a 1-pole
system, and the pole frequency ($\omega _{p})$ can be calculated by the following
equation.
Therefore, the parameters ${\alpha}$ and ${\beta}$ can be obtained by taking the bilinear
transform [12] in the continuous time Eq. (1).
4. PW Predictor
The M$_{\mathrm{SW}}$ turn-on time (T$_{\mathrm{SW,on}}$) for the PWM control of the
boost converter is determined by the load current (I$_{\mathrm{LED}}$) and the output
voltage V$_{\mathrm{out}}$. I$_{\mathrm{LED}}$ are obtained from the control input
B$_{\mathrm{I \_ LED.}}$V$_{\mathrm{OUT}}$ is derived as
V$_{\mathrm{LED \_ C}}$ is converged to V$_{\mathrm{ref}}$ with the loop operation,
and V$_{\mathrm{ON}}$ and R$_{\mathrm{LED}}$ are obtained from the control input B$_{\mathrm{V
\_ LED}}$ and B$_{\mathrm{R \_ LED}}$. Therefore, by analyzing the boost converter
operation, target T$_{\mathrm{SW,on}}$ at a given operating point can be calculated
and used for the fast settling of the loop.
T$_{\mathrm{SW,on}}$ calculation process is as follow: First, since the voltage across
the inductor when the switch is turned on in the boost converter operation is input
supply voltage V$_{\mathrm{IN}}$, the maximum current i$_{\mathrm{L,max}}$ flowing
through the inductor is derived as follows.
In (9), L$_{\mathrm{S}}$ is the inductance of the inductor. If the voltage across
the inductor when the switch is off is V$_{\mathrm{OUT}}$-V$_{\mathrm{IN}}$, and the
time taken for the inductor to be completely discharged when the switch is off is
T$_{\mathrm{sw,off}}$, the following equation can be derived.
Combining (9) and (10), we get:
The switch M$_{\mathrm{SW}}$ operates only when the LED is turned-on, which is defined
by NRA turn on time (T$_{\mathrm{DUTY,on}}$) for LED duty-cycling defined by the control
input B$_{\mathrm{D \_ LED}}$. Therefore, during one cycle of DUTY, the M$_{\mathrm{SW}}$
operates n times, The n should be integer and is calculated as follows.
Therefore, the input average power (P$_{\mathrm{IN,avg}}$) is derived as:
And the output average power (P$_{\mathrm{OUT,avg}}$) is:
In (14), I$_{\mathrm{LED}}$ is the LED current and is defined by the control input B$_{\mathrm{I
\_ LED}}$. I$_{\mathrm{DC}}$ is a dc biasing current for CCR and level shifter in
the boost converter, which is obtained from SPICE circuit simulations. T$_{\mathrm{DUTY}}$
is the period of the LED duty-cycling (12${\times}$256${\times}$T$_{\mathrm{CLK}}$$_{\mathrm{IN}}$).
Finally, assuming that the average power supplied through the inductor L$_{\mathrm{S}}$
and the power dissipated from V$_{\mathrm{OUT}}$ are the same, (13) and (14) are equal, we obtain T$_{\mathrm{SW,on}}$ as follow
PW predictor performs digital signal processing of the Eq. (15) from control input (B$_{\mathrm{I \_ LED}}$${\rightarrow}$I$_{\mathrm{LED}}$, B$_{\mathrm{D
\_ LED}}$${\rightarrow}$ T$_{\mathrm{DUTY \_ ON}}$, B$_{\mathrm{V \_ LED}}$and B$_{\mathrm{R
\_ LED}}$${\rightarrow}$V$_{\mathrm{OUT}}$) and circuit design parameters (L$_{\mathrm{S}}$,
V$_{\mathrm{IN}}$, I$_{\mathrm{DC}}$, T$_{\mathrm{DUTY}}$, T$_{\mathrm{SW}}$). Processed
output is 8-b PW$_{\mathrm{PRD}}$ code, which generates T$_{\mathrm{SW,on}}$ of PW$_{\mathrm{PRD}}$
$\times $T$_{\mathrm{CLK}}$$_{\mathrm{IN}}$.