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  1. (Department of Electronics Engineering, Korea National University of Transportation, Chungju 380-702, Korea)
  2. (Department of SK Hynix NAND PI, 2091 Gyeongchung-daero, Bubal-eup, Icheon-si, Gyeonggi-do, Korea )
  3. (Next Generation Semiconductor Convergence and Open Sharing System, Seoul National University, Seoul 151-747, Korea)

3D NAND flash memory, channel profile, electric field, cell current, threshold voltage


Since three-dimensional (3D) NAND flash memory [1-5] was first commercially introduced, the production of vertical NAND flash memory has continued to scale, making it a mainstream data-storage device in several applications. Owing to the scaling limitations of two-dimensional (2D) NAND flash memories, 3D vertical NAND flash memories have emerged. Consequently, the continuous stacking of 3D NAND flash memories is expected to reach 500 stacks. However, as the stacking height increases, channel-hole dry-etching control becomes more difficult [6,7]. This leads to tapering issues, where the top and bottom of the process are etched to different degrees, and achieving a perfect circular profile during the etching process becomes difficult [8,9]. This study aimed to analyze the factors and characteristics of cell current degradation owing to channel profile variation in 3D NAND flash memory through technology computer-aided design (TCAD) simulation [10,11]. To obtain a varied channel profile, the traditional 2D NAND structure was transformed into a cylindrical shape to provide flexibility for different channel designs.


Fig. 1 shows a schematic of the 3D NAND flash memory designed in TCAD. The word-line (WL) stack consisted of seven layers alternating between oxide and nitride, each with a thickness of 30 nm. Additionally, Sentaurus process (SPROCESS) was used in 3D TCAD simulation to implement the fabrication process. The hole was fabricated using a plug etch process and was filled with oxide-nitride-oxide (O/N/O) and a polysilicon channel. The detailed process flow is as follows: Selective etching was performed to remove the nitride layer and form the WL. The tunnel oxide, charge-trap nitride, and blocking oxide layers were deposited to refine the memory-cell structure. Finally, the control gate was formed, enabling the manipulation of the charge storage and retrieval processes in the NAND flash memory [12,13]. Doping Dependent Mobility (DDM), Enormal and High-field saturation were applied for modeling charge mobility. Also Shockley Read Hall (SRH), Auger and Hurkx were used. Five WLs with a 30/30 O/N pitch were used for the simulation, as shown in Fig. 1. The detailed specifications are listed in Table 1.

Fig. 1. Schematic of 3D NAND flash memory string.

Fig. 2 shows the four types of cross-sectional profiles fabricated using the Sentaurus simulation: (a) circle, (b) ellipse, (c) spike, and (d) double spike. The cell current characteristics, including the Vth target, ID-VDS curve, and E-field, were analyzed for the program state (Vth=1.7 V).

Fig. 2. Cross-sectional channel profiles of select WLs in 3D NAND flash memory: (a) circle; (b) ellipse; (c) spike; (d) double-spike.
Table 1. Physical And Material Parameters

Physical Parameter


Gate Length

30 nm

Gate Spacer Thickness

30 nm

Tunneling Oxide Thickness

4 nm

Nitride Thickness

8 nm

Blocking Oxide Thickness

8 nm

Polysilicon Channel Thickness

15 nm

Filler Oxide Thickness

Trap energy level (Et)

Trap density (Nt)

23 nm

2.5 eV

3e19 cm-3


Fig. 3(a) shows the operating conditions for measuring the cell current. Fig. 3(b) shows the ID-VDS curve depending on the WL shapes for the programmed cell. The bit-line (BL) current in Fig. 3(b) was divided by the circumferential length for each shape to normalize the current. When applying the program voltage to each channel profile, the Vth target was set at 1.7 V using Incremental Step Pulse Programming (ISPP) slope. Vth The ID-VDS characteristics of the programmed cell were analyzed at VREAD=6 V, 7 V, and 8 V. Based on this result, the circular profile showed the largest cell current among all the channel profiles. The cell currents of the double-spike and spike profiles were similar. The elliptical profile showed the smallest current, which decreased by 21 % compared with that of the circular profile. This indicates that the elliptical profile mainly affects the cell current characteristics of the plug structures.

Fig. 3. (a) Vthtarget condition; (b) Normalized ID-VDScurve for each channel profile in the program state.

The difference in cell currents can be explained as shown in Fig. 3. Fig. 4 shows the E-field along the cut-line of the Y positions for the circular and elliptical profiles at VREAD=7 V. Fig. 4(a) and (b) show the E-field applied to the tunneling and blocking oxides. The E-field of the circular shape was higher than that of the elliptical shape during the read operation. As shown in the cut-line E-field profile in Fig. 4(a), the reason for the decreased E-field during programming was that the number of trapped electrons increased in the nitride layer of the elliptical profile [14,15]. Fig. 4(b) shows that the E-field difference at the tunneling oxide was similar for the circular and elliptical profiles.

Fig. 4. E-field along the cut-line of the Y positions for the circular and elliptical profiles at VREAD=7 V: (a) major axis region; (b) region adjacent to the major axis.

Fig. 5 shows the E-field along the cut-line of the Y positions for the spike and double-spike profiles at VREAD=7 V. Fig. 5(a) and (b) show the E-fields applied to the tunneling and blocking oxides. As shown in Fig. 5(a), the double-spike profile exhibited a higher E-field than the spike profile along the cut line. This was because a significant number of traps existed in the nitride layer of the spike profile, resulting from the high E-field during programming. This can be explained by the same reason for the E-field difference between the circular and elliptical profiles shown in Fig. 4. The average E-fields for the spike and double-spike profiles were similar, which is the primary reason for the negligible difference in the cell current, despite the substantial variation in the E-field at the spike end point in Fig. 5(a).

Fig. 5. E-field along the cut-line of the Y position for the spike and double-spike profiles at VREAD=7 V: (a) Sharp protrusion regions for the spike and double-spike profiles; (b) Sharp protrusion region corresponding to the double-spike profile.

Fig. 6 shows the linear and log scales of the ID-VG curve for each channel profile after the program (Vth target=1.7 V). The Gm of the elliptical profile was lower than that of the circular profile in Fig. 6(a). The subthreshold swing of the elliptical profile was worse than that of the circular profile, which can be explained by the difference in the effective radius (Reff) in Eq. (1) [16].

Fig. 6. Normalized Vthtarget for each channel profile in the program state: (a) linear scale; (b) log scale.
$ R_{eff}\approx \frac{ab}{\sqrt{\left(a^{2}+b^{2}\right)/2}} $

where $a$ represents the major axis of the ellipse, and $b$ represents the minor axis. The Reff of the elliptical profile was 13.2 nm (a=25 nm and b=10 nm), which is larger than that (1 nm) of the circular profile. In Fig. 6(b), there is no difference in the subthreshold slope between the spike and double-spike profiles, which was because Reff did not differ owing to their similar shapes, except for the number of spikes.


The abnormal channel profiles of the 3D NAND flash memory were analyzed using 3D TCAD simulation. The analysis focused on the Vth target in the programmed state and the cell current for each channel profile, specifically examining the E-field applied to the tunneling oxide. The cell current during the read operation was directly proportional to the E-field applied to the tunneling oxide. Therefore, by studying the E-field characteristics, the performances of different channel profiles can be analyzed. Through the analysis, it was observed that the trends of the E-field average and the ID-VDS curves aligned consistently. This indicates that the E-field played a significant role in determining the cell current behavior. Furthermore, the analysis revealed a reduction in cell current owing to an E-field bottleneck in the elliptical profile. This suggests that the elliptical profile may have limitations in achieving the desired cell current, likely owing to the lower concentration of the E-field in certain regions. To achieve optimal performance in terms of cell current during the manufacturing process, it is suggested to avoid utilizing the elliptical profile, as it demonstrates the lowest cell current.


This study was supported by SK Hynix Inc.


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Jaewoo Lee

Jaewoo Lee received B.S. degree in the department of electrical engi-neering, Korea National University of Transportation, Korea, in 2022. From 2016 to 2022, He is currently a master student at Korea National University of Transport. His current research interests include operation conditions, reliability and cell characteristics of 3D NAND Flash Memory.

Yungjun Kim

Yungjun Kim received the M.S. degree in physics from Korea University, Seoul, in 2010, He has been working as a Device and Process Integration Engineer in the field of 2D/3D NAND flash memory at SK hynix, Icheon-si, South Korea, since 2010, and he is currently working on Ph.D, degree from Korea Advanced Institute of Science and Technology(KAIST) Graduate School of Semiconductor Technology. His current research interests include Ferroelectric and 3D NAND.

Yoocheol Shin

Yoocheol Shin received the M.S degree in physics from Seoul National University, Seoul, in 1995. From 1995 to 2017, he worked at Samsung Electronics Company Ltd., Yongin-si, South Korea, where he was in charge of developing 2D/3D NAND flash as a Fail Analysis Principal Engineer. In 2018, he joined SK hynix, Icheon-si, South Korea. He is in charge of developing 3D NAND flash process integration as Process Principal Engineer.

Seongjo Park

Seongjo Park has worked at SK hynix, Icheon-si, South Korea since 1995. He was the manager of 2D/3D NAND process integration and product management office. He is vice president of NAND develop-ment in charge of developing NAND products.

Daewoong Kang

Daewoong Kang received the Ph.D. degree in electrical engineering from Seoul National University, Seoul, in 2009. From 2000 to 2015, he worked at Samsung Electronics Company Ltd., Yongin-si, South Korea, where he was in charge of developing 2D/3D NAND flash as a PI Principal Engineer. From 2015 to 2019, he worked as Senior Technologist (Principal) in Western Digital Corporation (WDC), San Jose, U.S. From 2019 to 2022, he worked as a NAND Product Vice President (VP) at SK-Hynix Semiconductor, Icheon-si, South Korea, and developed the vertical NAND flash product with 128 layers for the first time in the world. His current research interests include the NAND process integration, cell characteristics, and reliability of 3D flash memory.

Myounggon Kang

Myounggon Kang received Ph.D. degree in the department of electrical engineering, Seoul National University, Seoul, Korea, in 2012. From 2005 to 2015, he worked as a senior engineer at Flash Design Team of Samsung Electronics Company. In 2015, he joined Korea National University of Transportation as a professor of Department of Electronics Engineering. His current research interests are CMOS device modeling and circuit design of memory.