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  1. (Department of Electronic Engineering, Kyung Hee University, Yongin, Korea )

Low-pass filter, negative capacitance, negative group delay, negative inductance, non-Foster resonator


A low-pass filter (LPF) is a paramount component in communication systems. It has to provide low in-band loss and high out-of-band attenuation. Furthermore, modern systems require active LPFs to have both a small size for integration and low DC power dissipation. One of the important characteristics of an LPF is the flat group delay (GD) across the band. The GD indicates the relative delay at different frequencies between the input and output ports. It is defined as the rate of change of the total phase shift (${\theta}$) through a system with respect to angular frequency (${\omega}$); $-$ d${\theta}$/d${\omega}$. By having flat group delay characteristic, the LPF can ensure that different frequency components of a signal are delayed equally, thus preserving the integrity of the signal. This is important to minimize distortion and maintain accurate timing in systems where signal synchronization is critical, such as in high-speed data communication or audio processing.

Generally, LPFs with cut-off frequencies around the gigahertz region have been designed with transmission lines and implemented in the printed-circuit board (PCB) technology. PCB LPFs show superior performance at the cost of huge size and substantial GD around the cut-off frequency. Plus, there is a trade-off between the out-of-band attenuation roll-off rate and GD variation [1,2]. Hence, LPFs for CMOS IC technology were proposed to have a miniature size as well as suppress bonding parasitics [3]. Linear phase filters with a Gm-C topology have been widely used for the CMOS active LPFs, which require DC power dissipation and show a worse roll-off rate than PCB LPFs counterparts [4,5]. For years, circuits generating a negative GD (NGD) have been used to establish critical foundations [6,7] and applied diversely, to flatten GD in-vehicle radars [8], improve the efficiency of feedforward linear amplifiers [9], and remedy the beam-squinting issue in series-fed antenna arrays [10], etc.

In this paper, we present a CMOS lumped-element (LE) LPF employing non-Foster element circuits of negative inductance (NIND) and negative capacitance (NCAP) to generate NGD, which serves for GD cancellation to equalize GD within the operating frequency band.


An LE LPF (Fig. 1) was designed to demonstrate the proposed GD cancellation technique. The Chebyshev topology was chosen for better roll-off rate performance. Each component’s value was calculated as per the given design specification [7]. The 5th order configuration was chosen to meet the following specifications: the cut-off frequency of 1.5 GHz, a ripple of 0.5 dB in the passband, and an attenuation of 20 dB at 2 GHz. With the system characteristic impedance (Z0) of 50 ${\omega}$, the value of each component in Fig. 1 was found as C1 = C5 = 3.6 pF, C3 = 5.4 pF, L2 = L4 = 6.5 nH. In the simulation, the GD was 0.4 ns at low frequencies, increased rapidly starting from 1.2 GHz and reached 0.9 ns at 1.5 GHz.

Fig. 1. Proposed GD cancellation technique with non-Foster elements.

1. Group Delay Cancellation

Fig. 1 shows the proposed GD cancellation technique. The NGD is generated by a parallel non-Foster resonator (NFR) consisting of a negative inductor (NIND or Ln) and a negative capacitor (NCAP or Cn). When the NFR is connected in shunt to the center node of the LPF, the inherent positive GD (PGD), generated from the LEs of the LPF, is neutralized by the NGD, which results in the relative GD cancellation. Additionally, in terms of implementation, the NFR is configured such that it provides a high impedance path (good matching) to the ground in the vicinity of the filter cut-off frequency as the first concern.

The second essential design step is optimizing NFR to mitigate the filter pass-band loss, return loss, and roll-of-rate.

The NGD comes from the NFR, and the resonant frequency (fres) of the NFR directly affects the characteristics of the LPF. Therefore, fres must be chosen carefully. When it was chosen to be 1.43 GHz (the input matching of the LPF was very good at this frequency), the NFR's influence on the LPF characteristics was little. The Ln and Cn values affects admittance of an NFR and thus the return loss and roll-off-rate (Fig. 2(a)); therefore, the Ln was chosen to keep fres to be 1.43 GHz with the variation of Cn. Fig. 2(b) shows the simulated GD cancellation of the LPF with the variation of Ln and Cn. With given fres, an increase in the magnitude of Cn impairs the return loss and improves the roll-of-rate. The Ln and Cn were chosen to achieve the required GD cancellation while minimizing the impact on the performance of the LPF. In this study, the Ln and Cn were chosen as ${-}$1 nH and ${-}$12 pF, respectively, to obtain an NFR return loss of more than 22 dB and insertion loss of less than 2.1 dB simultaneously at 1.43 GHz (Fig. 3(a)).

Fig. 2. (a) Admittance of resonator with ideal non-Foster elements; (b) Simulation results of GD with ideal shunt NFR.
Fig. 3. (a) Insertion loss and return loss of NCAP and NIND circuits; (b) NGD simulation results with one and two-sectional NFR.

2. Non-Foster Resonator Circuit Co-design with LPF

The correlation between non-Foster behavior and NGD was studied and generalized for both transmission and reflection types [7]. In this section, we mathematically formulated the NGD property of NCAP, and NIND, confirm the NGD capability of the NFR by simulation and gave some highlights on LPF design. Fig. 4 shows the schematic of the NIND and NCAP circuits. The circuits have a 2-port floating topology. By using the small-signal equivalent circuit analysis and assuming two NMOS devices are identical and the intrinsic gain of NMOS (M1-4) is sufficient, the equivalent inductance and capacitance can be regarded as -LL and -CL, respectively [11,12]. With the same approach, we figured out the admittance matrix of NCAP and then transformed it into S-parameter format using formulas provided in [13]. Finally, employing the obtained transmission phase S21, the group delay of NCAP in Fig. 4(a) can be approximated by: $-\frac{\partial \angle S_{21}}{\partial \omega }$

$ \tau _{gNCAP}\left(\omega \right)\approx -\left[\frac{1}{1+\left(\frac{2\omega C_{k}+\frac{Y_{0}\omega }{\omega _{u}}}{\frac{2\omega ^{2}c_{k}}{\omega _{T}}+Y_{0}}\right)^{2}}\frac{\left(2C_{k}+\frac{Y_{0}}{\omega _{u}}\right)\left(Y_{0}-\frac{2\omega ^{2}C_{k}}{\omega _{T}}\right)}{\left(\frac{2\omega ^{2}c_{k}}{\omega _{T}}+Y_{0}\right)^{2}}~ \right]\\ ~ < 0 $

with a note that: $0< \omega < \sqrt{\frac{Y_{0}\omega _{T}}{2C_{k}}},$ $\omega \ll \omega _{T},$ $\omega _{\mathrm{u}}=$ $\frac{g_{m}}{2C_{k}+C_{gs}};\,\,\,\omega _{T}=\frac{g_{m}}{C_{gs}}$, $Y_{0}=\frac{1}{Z0}$; Ck = CL + 2Cgd.

Likewise, (2) is regarded as NGD generated by NIND:

$ \tau _{gNIND}\left(\omega \right)\approx -\left[~ \frac{1}{1+\left(\frac{-\frac{2}{\omega L}+\frac{Y_{0}\omega }{\omega _{u}}}{Y_{0}-\frac{2}{\omega _{T}L}}\right)^{2}}\frac{\left(\frac{2}{\omega ^{2}L}+\frac{Y_{0}}{\omega _{u}}\right)}{Y_{0}-\frac{2}{\omega _{T}L}~ }\right]< 0 $

when $L> \frac{2}{Y_{0}\omega _{T}}$

Stability is the most important design issue because negative inductor and negative capacitor circuit uses a positive feedback technique. To insert the NCAP and NIND into the LPF under NFR topology, we applied the condition of bias current source: Rp/Rn ${\geq}$ 4/3 (P1-2, N1-2 in Fig. 4), which stems from [11], to preserve the stability of overall LPF circuit. Plus, to prevent the NFR from impairing LPF’s pass-band loss, the gm had to be chosen as high as possible (> 80 mS) to optimize NCAP, NIND losses. Fig. 3(a) shows the S-Parameters of NCAP and NIND with insertion loss lower than 0.7 dB and 1.1 dB, respectively, while their return losses are lower than 10 dB between 0.5 and 2 GHz. As a result, the NFR maintains its loss of approximately 2.1 dB and achieves a good matching of over 22 dB at 1.43 GHz. Hence, it should be noted that once it is joined in the LPF circuit, the procedure starts by synthesizing the lumped elements by the conventional method [13]. After inserting NCAP/NIND, LEs should be adjusted slightly to meet the given specifications. In this study, we employed the tuning feature in the ADS tool to optimize the NFR LPF performance.

Herein, the design parameters of the NCAP circuit in Fig. 4(a) are VDD = 2 V, bias current of 12 mA, (W/L)1 = (W/L)2 = 1100, CL = 3.5 pF, and C1 = C2 =10 pF. As for NIND in Fig. 2(b), VDD = 2 V, bias current of 20 mA, (W/L)1 = (W/L)2 = 4100, LL = 0.5 nH, and C1 = C2 = 10 pF. The size of the MOS devices were chosen to minimize parasitics (specially Cgs and Cgd) which affect the values of NCAP and NIND. Simulations with the variation of cornor parameters were performed. There was little influence below the cut-off frequency of 1.5 GHz. Unlike ideal non-Foster elements, the impedance of the NFR circuit is so high at low frequencies that the NFR circuit affects the LPF mildly. This occurs because of the DC blocking capacitors (C1, C2) at two terminals in the NIND and NCAP circuits.

The simulation exhibited that the one section NFR can provide up to about -400 ps NGD (Fig. 3(b)) conforming to NCAP/NIND in LPF GD cancellation. Nevertheless, LPF LEs without NFR underwent a GD of approximately 900 ps, requiring single-section NFR to yield corresponding NGD for cancellation. Because the parasitic capacitive components in the NFR circuit impair the magnitude of the NGD (maximum -400 ps in Fig. 3(b) - dashed line), a two-section NFR (two parallel NFRs connected in series) was proposed to increase the magnitude of the NGD. The two-section NFR generates NGD reaching -1ns, which is 2.5 times larger than that of the one-section counterpart (Fig. 3(b) - solid line) allowing the proposed NFR to cancel the PGD produced by the inherent passive LPF. However, the use of two NFRs results in larger loss, noise, and size. Hence, further optimization is needed to satisfy the filter requirements.

Fig. 4. Schematic (without bias circuit) of (a) NCAP; (b) NIND circuit.


The LPF with the NFR circuits was fabricated using the Global Foundry 8SF 130-nm RF CMOS technology. When the NIND and NCAP circuits were employed instead of ideal non-Foster elements, the components of the LPF in Fig. 1 were chosen as C1 = C5 = 1.9 pF, C3 = 6 pF, and L2 = L4 = 4.6 nH, to meet the specification for the return loss and attenuation. The spiral octagonal inductors and metal-insulator-metal capacitors were used for the LPF once layout. The NIND circuits included double-layer symmetric inductors to reduce loss and size. The size of the core chip excluding the pads for measurement is 1135 ${\mathrm{\mu}}$m ${\times}$ 475 ${\mathrm{\mu}}$m (Fig. 5). Fig. 6 shows the simulated and measured results for the S-parameters and the GD of the fabricated LPF chip. Below 1.5 GHz, the filter’s in-band loss is 0.8${-}$2.4 dB, and the return loss is more than 10 dB while the out-of-band roll-off rate reaches 41.5 dB/GHz. The GDs are 0.32${\pm}$0.01 up to 1~GHz. As the frequency increases, the GD decreases starting from 1 GHz and approaches zero at 1.51 GHz. When compared with the LPF without NFR, GD is reduced by approximately 0.9 ns at 1.5 GHz. The noise figures in the passband are 13.4$-$17.7 dB, measured by using a noise figure analyzer (N8975A, Agilent) and a smart noise source (N4002A, Agilent).

Table 1. Comparison With Previously Reported CMOS Low Pass Filters


CMOS Tech.


Max. op Freq.


Max. in-band loss


DC Power



roll-off rate


GD variation


Filter Type

























This work








Table 1 compare CMOS LPFs in the literature. [3] showed a modest roll-off rate, LPF in [4] presented a flat GD but a poor roll-off rate, whereas the LPF in [5] provided a good roll-off rate but large GD variation. The LPF proposed in this work consumed the lowest DC power and showed the smallest GD variation with the best roll-off-rate characteristic among the CMOS LPFs.

Fig. 5. Photograph of implemented LPF chip with dual sections NFR.
Fig. 6. Measurement results of (a) magnitude of S-parameters; (b) GD of implemented LPF (using a vector network analyzer PNA E8361C, Agilent).


The study presented an LE LPF with a GD cancellation property. The PGD was canceled by the NGD generated from parallel NFRs comprising the NIND and NCAP circuits. The LPF provided small GD variation with other performance indicators preserved. To the best of our knowledge, this is the first report of a CMOS on-chip LE LPF using GD cancellation by the NGD from the NCAP and NIND circuits.


This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. 2022R1A2C1007712). The EDA tool were supported by the IC Design Education Center (IDEC), Korea.


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Quang-Huy Do

Quang-Huy Do received the B.S. degree in Mechatronics Engineering from Hanoi University of Science and Technology (HUST), Hanoi, Vietnam, in 2020. He is currently pursuing the Master degree at the High-Speed Semiconductor Circuit Laboratory, Department of Electronic Engineering, Kyung Hee University, Yongin, South Korea. His current research interests include high-frequency IC design.

Tan-Binh Ngo

Tan-Binh Ngo received the B.S. degree in electronics telecommuni-cations engineering from the Ho Chi Minh University of Technology, Ho Chi Minh City, Vietnam, in 2016. From 2016 to 2018, he was an analog mix-signal circuit designer with Uniquify Inc., where he worked on SRAM and IO interface circuits for high-speed DRAM product. As of march 2018, he has been pursuing the Master-Ph.D. degree at the High-Speed Semiconductor Circuit Laboratory, Department of Electronic Engineering, Kyung Hee University, Yongin, South Korea. His current research interests include high-speed memory interface designs, RF circuits for wireless power transfer system and non-foster elements as well as non-reciprocal circuits for RFIC applications.

Sang-Woong Yoon

Sang-Woong Yoon received the B.S. degree from Yonsei University, Seoul, South Korea, in 1998, the M.S. degree in electrical engineering from the Korea Advanced Institute of Science and Technology, Daejeon, South Korea, in 2001, and the Ph.D. degree in electrical and computer engineering from the Georgia Institute of Technology, Atlanta, GA, USA, in 2004. From 2005 to 2006, he was a Senior Design Engineer with RF Micro Devices, Billerica, MA, USA. From 2006 to 2007, he was with Marvell Semiconductor Inc., Santa Clara, CA, USA. In 2007, he joined Kyung Hee University, Yongin, South Korea, as a Faculty Member. He has authored or coauthored over 48 papers in refereed international journals and conference proceedings. His current research interests include solid-state device characterization, analog/RF IC design, power amplifier design, microwave component/module design, and RF front-end-module design in advanced integration technologies.