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  1. ( School of Electrical Engineering and Computer Science, Gwangju Institute of Science and technology, Gwangju, 61005, Korea)

Adaptive biasing, analog-to-digital converter, CMOS image sensor, incremental delta-sigma


With the increasing demand for high-speed, high-resolution image sensors with low power consumption, column read-out designs, particularly analog-to-digital converters (ADCs), have become increasingly challenging. An incremental delta-sigma ADC (IADC), with its relatively high speed, low noise, and low-power characteristics, is a good candidate to meet these requirements [1-10, 15, 16].

Single-slope (SS) ADCs are widely used as column-parallel readouts in complimentary metal-oxide semiconductor (CMOS) image sensors (CISs) owing to their simplicity and low-power consumption [12]. However, the conversion time of an SS ADC increases exponentially with ADC resolution, which limits the frame rate of a CIS. Two-step conversion schemes have been proposed to reduce the conversion time [13]; however, they are not widely adopted in industry because of linearity degradation. In contrast, an IADC requires much less time for conversion than an SS ADC and it does not compromise the linearity performance. For example, an IADC configured with a second-order delta-sigma modulator requires only approximately 100 clock cycles to achieve a 12-bit resolution, whereas an SS ADC requires approximately 40 times as many clock cycles to achieve the same resolution. However, IADCs consume more power than SS ADCs because they require a power-hungry amplifier. The amplifier, particularly the one used in the first integrator, consumes the most amount of power in the circuit design. This is because, while the non-idealities introduced in the second integrator are greatly attenuated by the noise shaping provided by the loop filter, those of the first integrator directly influence the overall device performance [11].

The bias current of the amplifier is generally determined based on the worst-case slewing condition because the amplifier output must settle to a desired value within a limited time span. Therefore, unnecessary power consumption can occur if the amplifier is not switched off. If only the power consumption of the amplifier is considered, a class-AB amplifier may be a better choice than a class-A amplifier. However, in a column-parallel readout circuit, it is crucial to reduce the transistor count and keep the amplifier circuit as simple as possible, particularly when the pixel pitch is exceedingly small. Therefore, a class-A amplifier was chosen for this study, and an adaptive biasing technique is proposed to reduce the power consumption of the amplifier.

The proposed adaptive biasing technique exploits a distinct feature found in the amplifier employed in the readout circuit of a CIS. In other words, it reduces power consumption by predicting the settling condition and eliminating the redundant biasing current of the amplifier.

The remainder of this paper is organized as follows: Section II explains the adaptive biasing technique, and Section III describes the implementation details of the proposed IADC with adaptive biasing. The measurement results and conclusions are presented in Sections IV and V, respectively.


Fig. 1 depicts the circuit diagram of the switched-capacitor integrator (SCI) employed in an IADC with a two-phase non-overlapping clock signal. During the sampling phase (${\phi}$$_{{1}}$), the input signal is sampled from the sampling capacitor (C$_{S}$). The charge on C$_{S}$ is then transferred to the integrating capacitor (C$_{I}$) in the integration phase (${\phi}$$_{{2}}$). During ${\phi}$$_{{2}}$, the bottom plate of C$_{I}$ is connected to either of the reference voltages (+V$_{R}$ or -V$_{R}$) depending on the digital output of the modulator, and the SCI performs both charge integration and digital-to-analog conversion. To make the SCI output settle to the expected voltage within a half-clock cycle, which is often called a settling time, the amplifier needs to consume a considerable amount of power during ${\phi}$$_{{2}}$. The required power of the amplifier depends on the input amplitude and digital output of the modulator. The amplifier exhibits the worst-case settling error when it experiences a large-signal behavior called ``slewing.'' During slewing, the bias current only flows through one of the input transistors, and the amplifier output behaves nonlinearly. The required bias current is derived as a function of the input amplitude (V$_{IN}$) and reference voltages. At the rising edge of ${\phi}$$_{{2}}$, the initial voltage at the input node of the amplifier, represented by Vx in Fig. 1, can be derived as

$$ \left|V_X\left(t_0\right)\right|=\left|\Delta V_D\right| \frac{C_S C_I+C_S C_L}{C_S C_I+C_S C_L+C_I C_L} $$
where $\Delta V_D=D V_R-V_{I N}$

In the above equations, ${\Delta}$V$_{D}$ indicates a quantization error and D denotes the 1-bit digital output of the modulator and has a value of either +1 or -1. In (1), the on resistance of the switch is ignored based on the assumption that the resistance is much smaller than the reciprocal of the transconductance of the input transistor. The amplifier slews until the {\textbar}V$_{X}${\textbar} reduces down to the following voltage as explained in [17]

$ \left| V_{X}\left(t_{1}\right)\right| =\frac{I_{T}}{gm} $

where I$_{T}$ denotes the tail current of the amplifier and g$_{m}$ denotes the transconductance of the input transistor. During slewing, the amplifier input voltage changes with time as follows

$ \left| V_{X}\left(t_{0}\right)-V_{X}\left(t\right)\right| =\frac{I_{T}C_{I}}{C_{S}C_{I}+C_{S}C_{L}+C_{I}C_{L}}t $

From Eqs (1) to (3). the change in V$_{X}$ during the amplifier slewing (\ul{V}$_{slew}$) and slewing time (T$_{slew}$) can be respectively derived as follow

$ V_{Slew}=\left| \Delta V_{D}\right| \frac{C_{S}C_{I}+C_{S}C_{L}}{C_{S}C_{I}+C_{S}C_{L}+C_{I}C_{L}}-\frac{I_{T}}{g_{m}} $
$_{\mathrm{}}$$\begin{array}{ll} T_{slew} & =\frac{C_{S}C_{I}+C_{S}C_{L}+C_{I}C_{L}}{I_{T}C_{I}}\left(V_{X}(t_{0})-V_{X}(t_{1})\right)\\ & =\left| \Delta V_{D}\right| \frac{C_{S}C_{I}+C_{S}C_{L}}{C_{I}I_{T}}-\frac{C_{S}C_{I}+C_{S}C_{L}+C_{I}C_{L}}{C_{I}gm} \end{array}$

After slewing, the amplifier enters the normal operation regime and exhibits a linear settling behavior. Therefore, settling time (T$_{settle}$) of the amplifier having a single dominant pole can be obtained by adding the slewing time and linear settling (T$_{lin}$) time as follows [14]

$ T_{settle}=\underset{T_{slew}}{\underbrace{\frac{V_{slew}C_{o}}{I_{T}}}}+\underset{T_{lin}}{\underbrace{\ln \left(\frac{V_{lin}}{V_{E}}\right)\cdot \tau }} $


$\begin{array}{ll} C_{o} & =\frac{C_{S}C_{I}+C_{S}C_{L}+C_{I}C_{L}}{C_{S}+C_{I}},\hspace{0pt}\hspace{0pt}\\ \,\,\tau & =\frac{C_{S}C_{I}+C_{S}C_{L}+C_{I}C_{L}}{C_{I}}\frac{1}{g_{m}} \end{array}$

In Eq. (6), V$_{E}$ denotes the settling error of the integrator output and V$_{lin}$ is the change in the amplifier output voltage during the linear settling, which can be expressed as

$ V_{lin}=\frac{I_{T}}{g_{m}}\frac{C_{S}+C_{I}}{C_{I}} $

By using the Eqs. (4) to (7), V$_{E}$ can be derived as

$ V_{E}=\frac{I_{T}}{gm}\frac{C_{I}}{C_{S}+C_{I}}\exp \left(-\frac{T_{lin}}{\tau }\right) $

where T$_{lin}$=T$_{settle}$-T$_{slew}$.

Fig. 2 illustrates the simulation results of I$_{T}$ with respect to ${\Delta}$V$_{D}$ for a given V$_{E}$. In the simulation, V$_{E}$ was set to 0.1e-7, which is sufficient for 12-bit accuracy, and T$_{settle}$ was set to 20 ns. The capacitance values for C$_{S}$, C$_{I}$, and C$_{L}$ were chosen as 50, 200, and 23 fF, respectively. As shown in Fig. 2, the required I$_{\mathrm{T}}$ is almost proportional to ${\Delta}$V$_{D}$. When ${\Delta}$V$_{D}$ is relatively small, the settling of the amplifier output can be accomplished with a much smaller current than that required by considering the maximum slewing (which, in this case, is 8.7 ${\mathrm{\mu}}$A).

Note that ${\Delta}$V$_{D}$ can be calculated before the integration phase begins owing to two reasons. First, the input of the IADC employed in the readout circuit of the CIS can be considered as a DC voltage because the pixel output remains constant while the analog-to-digital conversion of the pixel output is being processed. Second, the modulator produces a digital output before the integration phase begins, which is denoted as D in Fig. 1. Consequently, the required current of the amplifier can be determined for each integration in advance, and the power consumption of the amplifier can be optimized by adjusting the bias current according to ${\Delta}$V$_{D}$. This distinct feature of the IADC in the readout circuit of the CIS can be exploited to reduce power consumption by adaptively controlling the bias current.

Details of the adaptive biasing circuit is explained in the subsequent section.

Fig. 1. Circuit diagram of switched-capacitor integrator.
Fig. 2. Required amplifier bias current (I$_{T}$) with ΔV$_{D}$.


Fig. 3 shows a simplified circuit diagram of the IADC with the proposed adaptive biasing circuit and its control signals. It comprises a 2nd-order delta-sigma modulator, 1-bit quantizer, digital filter, and adaptive biasing circuit. The proposed adaptive biasing technique was only applied to the 1st integrator because it consumes most of the ADC power. The modified cascaded-of-integrator feedforward (CIFF) modulator architecture presented in [8] was adopted for the high linearity performance and low-power active summation of 1st integrator output and 2nd integrator output signals. The number of conversion cycles, known as the oversampling ratio (OSR), of the IADC is 100, which is sufficient for 12-bit accuracy.

The adaptive biasing circuit, illustrated in Fig. 3 by the dashed box, consists of additional NMOS transistors and digital logic. The transistors operate as switched current sources, whose gate terminals are controlled by the digital logic output (A_CON).

In this study, I$_{T}$ consisted of one constant current source (I$_{B}$) for the minimum bias current and four unit current sources that could be turned on or off by A_CON. The digital logic generates A_CON using ${\Delta}$V$_{D}$ for each conversion cycle and the least four significant bits of the decimation filter output (V$_{IN\_ D}$), which represents the quantized V$_{IN}$ with 4-bit resolution. If D is high, A_CON is set as the inverted V$_{IN\_ D}$, otherwise A_CON is set as V$_{IN\_ D}$. Adaptive biasing can be enabled or disabled using the ADAP_EN control signal. If ADAP_EN is high, adaptive biasing becomes active, and V$_{IN\_ D}$ and D determine which NMOS transistor is turned on to make I$_{T}$ proportional to ${\Delta}$V$_{D}$. On the other hand, if ADAP_EN is low, all the NMOS transistors are turned on, and the I$_{T}$ of the amplifier is set to its maximum value to meet the worst-case settling condition.

presents the variations in the I$_{T}$ with V$_{IN\_ D}$ and D. It is clearly indicated in that I$_{T}$ varies significantly with V$_{IN}$ and the amount of average power saving depends on the value of V$_{IN}$.

Fig. 4(a) shows the simulated I$_{T}$ values for each conversion cycle for different DC input values. The larger the V$_{IN}$, the longer the required I$_{T}$ remains low during conversion, and the greater the effect of power saving. Fig. 4(b) shows the amount of power saved by applying adaptive biasing. In this simulation, V$_{IN}$ was swept from ${-}$0.4 V to 0.4 V and I$_{T}$ was averaged over 100 conversion cycles. Depending on V$_{IN}$, adaptive biasing reduces the average current by 33%-62%.

Fig. 3. Circuit diagram of the proposed IADC with adaptive biasing circuit and clock signals.
Fig. 4. Simulated I$_{T}$ for each cycle with different values of DC input (a) and average of IT with V$_{IN}$ (b).
Table 1. Various IT values with VIN_D and D






0.4 (1111)




8.7 uA

0.4 (1111)




2.3 uA

0 (1000)




5.6 uA

0 (1000)




5.6 uA

-0.4 (0000)




2.3 uA

-0.4 (0000)




8.7 uA


The ADC was fabricated using a 0.18 ${\mathrm{\mu}}$m 1P6M standard CMOS process. The ADC occupies an area of 0.0063 mm$^{2}$. A photograph of the ADC is shown in Fig. 5. To verify the effectiveness of adaptive biasing for CIS applications, an ADC was employed as the readout circuit in a CIS with a 312 ${\times}$ 144 pixel array. As the standard CMOS process does not provide a dedicated photodiode (PD), the source region of the NMOS transistor was modified and used as the PD. The quantum efficiency of the modified PD is very low; therefore, its source region was enlarged to increase the amount of photocurrent generated by the incident light. This increases the pixel size and width of the ADC layout to match the pixel pitch. If the pixel size is reduced, the ADC size can be designed to be smaller, and there is no special limitation preventing the size of the ADC from being reduced compared to other works [1].

Fig. 6 shows the measured dynamic performance for a 100 Hz sinusoidal input signal with a sampling frequency of 25 MS/s. The measured signal-to-noise distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 65 dB and 78 dB, respectively. The resulting effective number of bits (ENOB) were calculated as (SNDR-1.76)/6.02, which is 10.5 bits.

Fig. 7 shows the measured SNDR as a function of the average current drawn by the ADC for a sinusoidal input at 100 Hz.

To evaluate the effect of the adaptive-biasing scheme, the total bias current of the integrators was swept by externally controlling the gate voltage of the tail transistors. As shown in Fig. 7, the SNDR was maintained at a lower current level with adaptive biasing. Based on the measurement results, the adaptive biasing technique reduced the total power consumption by approximately 40%. The measured static performances with and without adaptive biasing are depicted in Fig. 8(a) and (b), respectively. With the adaptive biasing, the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are less than +0.31/-0.42 LSBs and +0.62/-0.75 LSBs at a 12-bit accuracy, respectively.

These values are comparable to those measured without the adaptive biasing. This result indicates that the adaptive biasing technique effectively reduces ADC power consumption while maintaining performance. Although the power consumption of the ADC has been greatly reduced by the adaptive biasing, the ADC still consumes a bit more power than the one employing an inverter-like amplifier [4]. However, this work does not require additional circuitry for controlling a quiescent current of the amplifier. The ADC draws an average current of 19 ${\mathrm{\mu}}$A from a 1.8 V supply, resulting in a power consumption of 34.2 ${\mathrm{\mu}}$W.

compares the performance of the ADC with those of state-of-the-art IADCs fabricated using similar technologies. The ADC achieves a figure of merit (FOM), which is calculated as Power${\cdot}$conversion time/2$^{\mathrm{ENOB}}$, of 84 fJ·mm$^{2}$/Conv-step, and the FOM of this work is comparable to the FOMs of IADCs fabricated using advanced processes. The measured ADC performances are summarized in .

Fig. 5. Microphotograph of the ADC.
Fig. 6. Measured dynamic performance.
Fig. 7. Measured SNDR versus total current of the ADC.
Fig. 8. Measured static performances: (a) without adaptive biasing; (b) with adaptive biasing.
Table 2. Performance comparison








This work









Technology [um]








Sampling Frequency [MHz]








Conversion Time [µs]








Supply Voltage [V]








SNDR [dB]/ENOB [bit]








Power Consumption [µW]








Active Area [mm2]








*FoM [fJ/Conv.step]








* FoM=power∙conversion time/2ENOB)
Table 3. Performance summary


0.18 mm CMOS


1.8 V


12 bit

Sampling Frequency

25 MHz

Conversion Time

4 us (OSR=100)

SNDR @ Fin=100Hz

66 dB


10.7 bit





Power Consumption

34.2 µW

ADC Area

14 mm × 450 mm


A low-power IADC was designed and fabricated for application in a column-parallel readout of the CIS using a 0.18-${\mathrm{\mu}}$m, standard CMOS. An adaptive biasing technique was proposed, applied to a prototype IADC, and the performance was verified through measurements. Owing to the adaptive biasing technique, the ADC achieves an approximately 40% reduction in ADC power consumption without compromising performance.


This work was supported in part by the National Research Foundation of Korea (NRF) Grant through the Korean Government (MSIT) under Grant 2021R1A2 C22013480 and by Nano·Material Technology Development Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT under Grant NRF-2022M3H4 A1A01009658.


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Dong-Hwan Seo

Dong-Hwan Seo received the B.S. degree in Electronic Engineering from Konkuk University, Seoul, South Korea, in 2011, and the M.S degree from the School of Mechatronics, Gwangju Institute of Science and Technology, Gwangju, South Korea, in 2013. He is currently pursuing his PhD degree with the School of Electrical Engineering and Computer Science. His research interests include CMOS image sensors, dynamic vision sensors, and analog-to digital converters.

Jung-Gyun Kim

Jung-Gyun Kim received the B.S. degree in Electrical Engineering and Computer Science from Gwangju Institute of Science and Technology (GIST), Gwangju, Korea, in 2017, where he is currently pursuing his PhD degree. His main subject is the development of a neuromorphic processor for an event-based vision sensor. His research interests include neuromorphic systems and vision application.

Byung-Geun Lee

Byung-Geun Lee (S’04-M’08) received the B.S. degree in Electrical Engineering from Korea University, Seoul, Korea, in 2000. He received the M.S. and PhD degrees in Electrical and Computer Engineering from the University of Texas at Austin in 2004 and 2007, respectively. From 2008 to 2010, he was a senior design engineer at Qualcomm Incorporated in San Diego, CA, where he was involved in the development of various mixed-signal ICs. Since 2010, he has been with the Gwangju Institute of Science and Technology (GIST) and is currently a professor at the School of Electrical Engineering and Computer Science.