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Title A Low-power Incremental Delta-sigma ADC with Adaptive Biasing for CMOS Image Sensors
Authors (Dong-Hwan Seo) ; (Jung-Gyun Kim) ; (Byung-Geun Lee)
Page pp.314-321
ISSN 1598-1657
Keywords Adaptive biasing; analog-to-digital converter; CMOS image sensor; incremental delta-sigma
Abstract This paper presents the design and fabrication of a low-power incremental delta-sigma analog-to-digital converter (ADC) with an adaptive bias technique suitable for complimentary metal-oxide semiconductor (CMOS) image sensors (CISs). The adaptive biasing circuitry provides the amplifier with a predicted minimum current value required for the integrator output to settle; this optimized current flows through the amplifier and reduces power consumption by 40%. A prototype ADC fabricated using a 0.18 μm CMOS process, achieves an SNDR of 65 dB at a sampling frequency of 25 MHz and consumes 13.5 μW from a 1.8 V power supply. The measured differential and integral nonlinearities are +0.31/-0.42 and +0.62/-0.75 at a 12-bit accuracy, respectively.