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  1. (School of Electrical and Computer Engineering, University of Seoul, Korea)

P3HT, Parylene-C, biocompatible, organic thin-film transistor, cyclic olefin polymer


With the development of organic thin-film transistors (OTFTs), researchers are now actively investigating various organic materials for fabricating the substrate, channel, gate dielectric, and passivation layer of OTFTs [1]. OTFTs are relatively easy to fabricate and inexpensive devices, which are compatible with the complementary metal-oxide-semiconductor fabrication process. Some organic materials exhibit good electrical and physical properties such as low leakage currents, high dielectric constants, transparency, and flexibility [2]. In particular, Parylene-C is widely used because of its simple coating method, high chemical resistance, biocompatibility, transparency and flexibility [3-5]. In this study, we developed biocompatible OTFTs on a Parylene-C substrate and gate dielectric layer using poly(3-hexylthiophene) (P3HT), which has a relatively high electron mobility. When P3HT is exposed to moisture and oxygen, the off current increases, whereas the on/off ratio (I$_{\mathrm{on}}$/I$_{\mathrm{off}}$) decreases, resulting in unstable properties. In a humid environment, the moisture (water molecules) is adsorbed on the P3HT surface and increases the charge carrier density because of the relatively large dipole momentum of the adsorbed water molecules. In addition, upon exposure to oxygen, the oxygen molecules infiltrate the P3HT thin film and generate reversible P3HT-oxygen adducts. These adducts can trap photogenerated electrons and form charge transfer complexes, which induce p-doping in the polymer. This phenomenon increases the on and off currents, especially the off current, and as a result, the on/off ratio decreases [6-12]. Therefore, it is important to prevent the P3HT layer from exposure to oxygen and moisture. In this study, we formed a cyclic olefin polymer (COP) passivation layer to achieve this goal. The COP has many advantages such as easy patterning, flexibility, and high water resistance, and for these reasons, it was chosen as the passivation layer. In addition, the effect of the COP passivation layer on the P3HT channel was also analyzed by comparing the OTFTs with and without the COP passivation. The transfer and output curves of the fabricated OTFTs were measured and analyzed for performance verification.


Fig. 1(a) and (b) show the schematic and device structure of a P3HT channel bottom-gated OTFT fabricated on a Parylene-C substrate. First, we formed a 10-${\mu}$m-thick Parylene-C thin film on a 4-inch Si wafer by chemical vapor deposition. The gate metal was patterned using the image reversal method with AZ5214E as a negative photoresist (PR). The soft and post exposure bake temperatures were 95 $^{\circ}$C and 115 $^{\circ}$C, respectively. The gate metal, Ti, and Au were deposited using an electron-beam (e-beam) evaporator at room temperature and patterned using the lift-off process. For the gate dielectric layer, a 300-nm-thick Parylene-C thin film was deposited. Because Parylene-C requires an etching process to open the contact pad, we prepared a PR etch mask for opening the contact pad and etched the Parylene-C gate dielectric by reactive ion etching. The source and drain metal patterns were formed by the same method as that used for the gate-metal pattern. Before the channel formation, O$_{2}$ plasma treatment was performed to improve the adhesion between the gate dielectric surface and P3HT. Then, we formed a PR pattern for the P3HT lift-off. For the channel formation, a P3HT dispersion was synthesized by the following method: First, we dissolved P3HT in monochloro-benzene via heating at 70 $^{\circ}$C for 30 min. Then, we filtered this solution using a polytetrafluoroethylene filter and applied the filtered solution to the wafer. The solution was spin-coated to form a thin film, cured at 90 $^{\circ}$C for 30 min, and finally, slowly cooled to room temperature. Because P3HT is vulnerable to oxygen and moisture, performance degradation may occur under atmospheric conditions. Therefore, we performed the dispersion synthesis and deposition in an N$_{2}$ glove box. Finally, a passivation layer was formed by spin-coating the COP; the spin-coating was performed inside the glove box to prevent degradation of P3HT, and resulting COP passivation layer was finally patterned by photolithography. After forming the COP passivation layer and etching the Parylene-C substrate, we expect the device to undergo minimal damage in a water bath [13].

Fig. 1. P3HT OTFTs: (a) Schematic of a long-channel P3HT OTFT array; (b) device structure of the P3HT OTFTs; (c) microscopy image of the P3HT OTFTs.
Fig. 2. Fabrication process of the P3HT OTFTs.


The characterization of the fabricated P3HT OTFT was performed using a probe station and Keithley 4200 semiconductor parameter analyzer. We measured the device parameters under different conditions. The transfer curves of the P3HT device were measured with a V$_{\mathrm{G}}$ sweep from -80 V to -80 V. The output curves were measured with a V$_{\mathrm{D}}$ sweep from 0 V to 80 V and V$_{\mathrm{G}}$ sweep from -10 V to -50 V [14,15]. All the measurements were conducted in air.

1. P3HT OTFTs without COP Passivation

For a higher I$_{\mathrm{on}}$/I$_{\mathrm{off}}$ ratio with a secured bandgap, an OTFT with a P3HT channel was fabricated and characterized. Further, we compared the P3HT OTFTs with and without the COP passivation layer to examine the channel passivation effect. Fig. 3(a) and (b) show the transfer and output curves of the P3HT OTFT device without any passivation layer. The device exhibits P-type characteristics and functions as a depletion-mode transistor (i.e., normally turned on at V$_{\mathrm{GS}}$= 0). As evident from Fig. 4(a), V$_{\mathrm{th}}$ = 7.8 V, the subthreshold swing (SS) is 33.3 V/decade, and the average leakage current is 89.1 nA. At V$_{\mathrm{DS}}$ = 30 V, the calculated I$_{\mathrm{DS,on}}$, I$_{\mathrm{DS,off}}$, and I$_{\mathrm{DS,on}}$/I$_{\mathrm{DS,off}}$ ratio are 11.2 ${\mu}$A, 188 nA, and 5.97 ${\times}$ 10, respectively. The extracted parameters of the P3HT OTFT without COP passivation are summarized in Table 1.

Table 1. Parameters of P3HT OTFT without COP passivation

Threshold Voltage (Vth)

7.8 ± 3.47 V

Drain on current (IDS,on)

1.12 × 10-5 ± 3.34 × 10-6 A

Drain off current (IDS,off)

1.88 × 10-7 ± 9.7 × 10-9 A

On/Off ratio (IDS,on/IDS,off)

5.97 × 10 ± 1.85

Subthreshold Swing (SS)

33.3 ± 5.4 V/decade

Average leakage current (IGS)

8.91 × 10-8 ± 2 × 10-8 A


1.9 × 10-2 ± 7 × 10-3 cm2/Vs

Fig. 3. P3HT OTFT without COP passivation: (a) Transfer curves; (b) output curves.
Fig. 4. P3HT OTFT with COP passivation: (a) Transfer curves; (b) output curves.

2. P3HT OTFTs with COP Passivation

Fig. 4(a) and (b) depict the transfer and output curves of the P3HT OTFT containing a COP passivation layer. Fig. 5(a) shows that V$_{\mathrm{th}}$ = 18.5 V, SS = 10 V/decade, and the average leakage current is 49.2 nA for the COP-passivated P3HT OTFT. Further, for this device, we obtain I$_{\mathrm{DS,on}}$ = 4.26 ${\mu}$A, I$_{\mathrm{DS,off}}$ = 3.14 nA, and I$_{\mathrm{DS,on}}$/I$_{\mathrm{DS,off}}$ = 1.36 ${\times}$ 10$^{3}$. The extracted parameters of the COP-passivated P3HT OTFT are summarized in Table 2.

These results indicate that the Parylene-C gate dielectric layer can successfully function as a gate dielectric, and the Parylene-C layer is not damaged during the device fabrication, such as upon exposure to UV light [16,17]. Further, the formation of a stable P3HT channel on the Parylene-C gate dielectric layer was verified. A comparison between the performances of the devices with and without the COP passivation revealed that the COP-passivated transistor showed a better performance than its counterpart (no COP passivation). In addition, the output and transfer curves of the COP-passivated P3HT OTFTs showed a more stable and flat saturation region compared to that observed in the case of the transistor without COP passivation.

Specifically, the I$_{\mathrm{DS,on}}$/I$_{\mathrm{DS,off}}$ ratio increased from 5.97 ${\times}$ 10 to 1.36 ${\times}$ 10$^{3}$, as the off current of the P3HT OTFTs without COP passivation increased. Further, the on current of the P3HT OTFTs without COP passivation showed a slight increase. However, this increment is negligible in comparison to the decrease in the off current and is thus insufficient to increase the I$_{\mathrm{DS}}$,on/I$_{\mathrm{DS}}$,off ratio. Because all the measurements were conducted in air, the P3HT layer without the COP was severely damaged by oxygen and moisture. Moreover, the SS decreased from 33.3 V/decade to 10 V/decade. These results indicate that the characteristics of the COP-passivated and without COP devices were similar to those of the devices analyzed in vacuum and air, respectively [10].

These results indicate that the device fabrication and COP passivation processes do not damage the P3HT channel and gate dielectric layers. In addition, the observed improvement in the device performance upon COP passivation implies that the deterioration of the P3HT channel can be effectively prevented by COP passivation.

Although the COP passivation layer improved the performance of Parylene-C OTFTs, the mobility of device is still lower than the commonly known value (approximately 0.1 cm$^{2}$/ V s). However, it is expected that it can be improved by process optimization through future research.

Fig. 6 presents the leakage current of the P3HT OTFTs with a 300-nm-thick Parylene-C gate dielectric layer. As shown in Fig. 3(a), 4(a) and 5, even when a high voltage from -80 to 80 V is applied to the gate, the increase in the leakage current is minor compared to that in the drain current. Tus, it is evident that the 300-nm Parylene-C gate dielectric layer exhibits a good insulation performance for V$_{\mathrm{GS}}$ in the range from -80 to 80 V.

Fig. 5. Leakage current of the P3HT OTFT containing a 300-nm-thick Parylene-C gate dielectric layer.
Table 2. Parameters of P3HT OTFT with COP passivation

Threshold Voltage (Vth)

7.4 ± 5.6 V

Drain on current (IDS,on)

4.26 × 10-6 ± 2.51 × 10-6 A

Drain off current \(IDS,off)

3.14 × 10-9 ± 1.45 × 10-9 A

On/Off ratio (IDS,on/IDS,off)

1.36 × 103± 7.8 × 10-2

Subthreshold Swing (SS)

10 ± 3.27 V/decade

Average leakage current (IGS)

4.92 × 10-8 ± 4.59 × 10-9 A


5.5 × 10-2 ± 3.8 × 10-3 cm2/Vs


In this study, P3HT OTFTs were fabricated on a biocompatible Parylene-C substrate, and the device performance was characterized. It was confirmed that the P3HT channel functions well on the Parylene-C-based OTFTs. The organic materials used in this study can be readily applied to other TFTs, especially those used in flexible devices. In addition, we verified that the COP passivation layer can protect the channel layer from oxygen- and moisture-induced damages. We anticipate that Parylene-C and COP-based TFTs will be used in diverse applications in various fields such as biosensor technology.


This work was supported by the National R&D Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (grant no. 2021R1F1A1056996, 2021M3H2A1038042), and partly supported by Korea Institute for Advancement of Technology(KIAT) grant funded by the Korea Government (MOTIE) (P0017011, HRD Program for Industrial Innovation). The EDA tool was supported by the IC Design Education Center (IDEC), Korea.


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KyungMin Kim

KyungMin Kim received the B.S. degrees in the School of Electrical and Computer Engineering (ECE), University of Seoul, in 2021. He is currently pursuing the M.S. degree in the School of Electrical and Computer Engineering, University of Seoul. His research interests include the design, fabrication, and characterization of organic thin film transistor and oxide thin film transistor.

Sookyeong Kim

Sookyeong Kim received the B.S. degrees in the Devision of Information, Major in Information Telecommunications Engineering, University of Suwon, in 2021. She is currently pursuing the M.S. degree in the School of Electrical and Computer Engineering, University of Seoul. Her reaserch interests include the design, fabrication, and characterization of bio-sensor such as 2D-material based electrochemical sensors.

Ah-Hyun Hong

Ah-Hyun Hong received the B.S. degrees in the School of Electrical and Computer Engineering (ECE) at the University of Seoul. in 2022. She is currently pursuing the M.S. degree in the School of Electrical and Computer Engineering, University of Seoul. Her research interests include the design, fabrication, and characterization of organic, oxide thin film transistor and biocompatible devices.

Yoojeong Ko

Yoojeong Ko received the B.S. degrees in the School of Electrical and Computer Engineering (ECE), University of Seoul, in 2022. She is currently pursuing the M.S. degree in the School of Electrical and Computer Engineering, University of Seoul. Her research interests include the design and manufacturing of fully transparent and flexible organic thin film transistor.

HyoWon Jang

HyoWon Jang is a Ph.D. student under the supervision of Prof. Hyeok Kim at the School of Electrical and Computer Engineering, University of Seoul (UoS). His research interests are fabrication and characterization of ferroelectric organic thin film transistor

Hyeok Kim

Hyeok Kim is an Associate Professor at the School of Electrical and Computer Engineering, University of Seoul (UoS). He performed the research focused on organic electronic devices, such as field-effect transistors and diodes, during his Ph.D from University of Paris 7 with Prof. Gilles Horowitz. Afterwards, he joined Samsung Advanced Institute of Technology (SAIT) then had led sensor research team in Korea Institute of Industrial Technology (KITECH). Prior to join UoS, he was with the department of electrical engineering in Gyeongsang National University in Jinju, Korea. His research interests include flexible optoelectronic devices and nanogenerators.

Dong-Wook Park

Dong-Wook Park is an Associate Professor at the University of Seoul in the School of Electrical and Computer Engineering. He received his Ph.D. degree at the University of Wisconsin-Madison and got a postdoctoral training at Stanford University where he studied implantable neural electrodes and biosensors. Prior to his Ph.D., he was at Samsung SDI and Samsung Display as an AMOLED circuit design engineer from 2007 to 2011. His current research centers on emerging biomedical devices and flexible electronics based on novel materials and nanotechnology.