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  1. (Department of Electric Engineering, Gangneung-Wonju National University, Gangneung, 25457, Korea )

Refresh time, gate induced drain leakage (GIDL), buried cell array transistor (BCAT), select word-line driver (SWD)


Dynamic random access memory (DRAM), which is used as a main memory device, comprises a capacitor and an access transistor. As big data advances, demands for high-storage capacity and high-performance memory in DRAM has increased. Consequently, DRAM manufacturing process technology has achieved high density, enabling high-performance and high-storage capacity DRAM [1]. However, in the process of scaling-down, the short channel effect (SCE) is caused by a decrease in the channel length [2,3]. SCE results in poorer performance and reliability issues in DRAM because of an increase in the leakage current. To solve this problem, the cell transistor is developed from the planar to a buried cell array transistor (BCAT) structure, which has a buried gate for suppressing the leakage current by extending the effective channel length [4-7]. Punch through and DIBL were suppressed using the BCAT structure, but the gate induced drain leakage (GIDL) was not. GIDL is a tunneling effect that occurs mainly in regions where the drain and gate overlap. It occurs when the band gap is thinned owing to an abrupt voltage difference between the drain and the gate in the off state. The oxide thickness has been continuously decreasing due to scaling, it can easily lead to GIDLs. Therefore, the DRAM performance, especially refresh time (T$_{\mathrm{ref}}$) [8], is significantly influenced by GIDL [9]. To prevent tunneling, it is important to reduce the electric field formed in the drain region.

In this study, we propose a multi gate BCAT structure and modified SWD circuit to suppress GIDL. The dual-gate BCAT, which is a type of multi-gate BCATs, has two metal gates placed up and down. The upper gate, referred to as the bump gate (B-gate), adjusts the work-function (WF) of the gate by applying an appropriate voltage that is different from the lower gate [10]; therefore, the electric field formed in the drain region is alleviated. To operate the dual-gate BCAT, two SWD circuits are required that apply different voltages to the two gates. Here, we present a circuit that operates by adding only one PMOS to the conventional SWD circuit.

The multi-gate BCAT structure and proposed SWD circuit were verified using TCAD and SPICE simulations.


A simulation was performed considering the terminologies and parameters of the BCAT structure at the 1y-nm technology nodes.

The depth of the gate trench was 150 nm, the gate oxide thickness along the sidewall of the trench was 8~nm, and the bottom of the trench was 5 nm. The drain/source doping depth was 56 nm. To evaluate the GIDL, we applied 4 V to the drain and -2 V\textasciitilde{}2 V to the lower gate, which is more severe than the actual DRAM operating conditions. In the TCAD device simulations, we incorporated the following models: 1) doping dependent Shockley-Read-Hall recombination; 2) band-to-band tunneling (BTBT), 3) and continuously variable transmission (CVT).


The most important aspect of reducing the GIDL is to suppress the electric field in the drain region [11]. When turned off, a positive voltage is applied to the drain, and a negative voltage is applied to the gate. Therefore, the electric field formed in the drain region becomes stronger, especially between the drain region and the gate. This electric field can be reduced in the developed BCAT structure by using poly-Si, as shown in Fig. 2, 3 The poly-Si structure can alleviate the abrupt WF difference between the gate and the drain by placing the doped poly-Si on the gate. By adjusting the silicon’s WF to an appropriate value, the electric field of the drain region is decreased, and the GIDL is also reduced alongside the electric field. Fig. 5 showed that the WF of silicon was optimized around 4.0 eV. The WF of silicon is determined by the doping concentration, but theoretically, the reachable WF of silicon is 4.05 eV. Additionally, owing to the out dopant diffusion occurring in the fabrication process [12], the WF of silicon is significantly different from the optimized value. Therefore, optimization is impossible in a BCAT structure using doped poly-Si.

Fig. 1. 2-D view of dual-gate BCAT structure.
Fig. 2. 2-D view of Poly-Si BCAT structure.
Fig. 3. I-V characteristic comparison between BCAT and Poly-Si BCAT.
Fig. 4. GIDL generation region of BCAT structure.
Fig. 5. Results showing the optimization and actual reachable values when adjusting the WF of Poly-si in the off state (V$_{\mathrm{g}}$ = -2 V and V$_{\mathrm{d}}$ = 2 V).


1. Dual-gate BCAT Structure

As can be observed from the simulation of poly-Si BCAT, to effectively alleviate GIDL, a material with a WF value of approximately 4.0 is necessary between the gate and the drain. Therefore, another material is needed to overcome the limitations of the WF range of silicon. Fig. 1 shows the proposed dual-gate BCAT structure, which is a type of multi-gate BCAT. In this structure, the electric field is reduced by the B-gate instead of the doped poly-Si. The BTBT current can be expressed as (1)

$ I_{BTBT}=A\times w\times \frac{E_{S}}{B}\exp \left(\frac{B}{E_{S}}\right) $

B : tunneling constant

W : width of the device

A : constant depletion depth

E$_{s}$: large electric field

To minimize the leakage current, the electric field formed in the A and B regions should be made uniform so that any one region is not excessive. To achieve this, it is necessary to adjust the WF by applying an appropriate voltage to the B-gate. We proceeded with the optimization by changing the voltage of the B-gate in the presented simulation environment. Fig. 6(a) shows the electric field changes in regions A and B when an optimized voltage was applied, compared with poly-Si BCAT. Fig. 7 shows the GIDL current according to the voltage. As shown in the graph presented, when a voltage of approximately 1.7 V at the B-gate is applied in a given environment, it was confirmed that the electric field is uniformly distributed to regions A and B, and the GIDL current is minimized. The optimized values are reduced by approximately four orders compared with the conventional values.

And we also optimized by changing the upper gate and depth in dual-gate structure from 44 nm to 75 nm. As a result, there was no significant difference as the optimization voltage Therefore, the same 1.7 V was applied regardless of the change in the gate length. However, when the ratio of the lower gate is decreased, it may be seen that the GIDL value increases. Conversely, if the upper gate(B-gate) is increased, the GIDL decreases, and from about upper gate length of 68 nm, the region where the GIDL occurs dominantly changes from A to B, and at this time, it is confirmed that the drain current of off state increases again. Fig. 8 shows the result of the gate length change. however, an upper gate length of 44 nm, top-bottom ratio of 5:5 was selected for the simulation to be applied to all cell transistors in the simulation. This is because when the gate area decreases, the sheet resistance increases, and a voltage cannot be properly applied to all DRAM transistors.

Fig. 6. The simulation result of GIDL in dual-gate BCAT structure: (a) E-field plot along the cut line in the drain region compared to Poly-Si; (b) Conduction band energy plot along the cut line in the drain region compared to Poly-Si.
Fig. 7. I-V characteristic of dual-gate BCAT and Poly-Si BCAT.
Fig. 8. Drain Current graph with off according to depth change in upper gate.}

2. Three-gate BCAT Structure

We conducted a simulation by changing the number of gates to determine the effect of gate numbers on GIDL mitigation. In the three-gate BCAT structure shown in Fig. 9 strong electric fields were formed in regions A, B, and C and the electric fields were uniformly distributed like in the dual gate structure. The structure was optimized by applying a voltage of 0.5 V to B-gate1 and 2.6 V to B-gate2. Fig. 11 shows that the GIDL of the three-gate was reduced by approximately two orders compared with the dual-gate structure. It was confirmed that the larger the number of gates, the better the GIDL.

Fig. 9. 2-D view of three-gate BCAT structure.
Fig. 10. The simulation result of three-gate BCAT in off state. E-field plot along the cut line in the drain region compared to dual-gate BCAT.
Fig. 11. Simulation results from 3-gate BCAT in off state.


In this study, we evaluate the GIDL current in the DRAM cell transistor. The structure has two metal gates which are arranged vertically and reduce GIDL by applying different voltages to the gates. Applying an optimized voltage to the upper gate alleviates the electric field that causes tunneling between the drain and the gate. In the TCAD simulation, GIDL was reduced by approximately four orders in the proposed structure compared with the poly-Si BCAT structure. To operate the proposed BCAT structure, we modified the conventional SWD circuit by adding one pass transistor. The pass transistor transmits an input signal to the output node, when the gate is turned on, and to enter the high Z state when the gate is off to maintain the previous state. However, there is a problem in transmitting voltage. A pass transistor using NMOS has no problem in transmitting 0 V (low), but if V$_{\mathrm{dd}}$ (high) is applied to an input node (drain), the output node (source) voltage gradually increases, and if V$_{\mathrm{gs}}$<V$_{\mathrm{th}}$, the device shuts off. Thus, the output voltage becomes V$_{\mathrm{dd}}$-V$_{\mathrm{th}}$. In contrast, PMOS has no problem in transmitting V$_{\mathrm{dd}}$, but the lowest voltage that the output node can reach is |V$_{\mathrm{th}}$|. Fig. 12 shows the configuration and output according to the input of the NMOS and PMOS pass transistors, and at this time, both gates are applied with Vdd. Fig. 13. Fig. 14 shows the operation of the proposed SWD circuit, in which different voltages are supplied depending on the Vth of the pass transistor in the off state and the same voltage is supplied in the on state.

The conventional SWD circuit consists of one PMOS and two NMOSs. When in the on state, the NWEIB and PXIB are in the low, and the PMOS connected to the V$_{\mathrm{pp}}$ is turned on and the V$_{\mathrm{pp}}$ is delivered to the WD. Conversely, when it is off, NWEIB and PXIB become high, and the NMOS connected to V$_{\mathrm{bb2}}$ is turned on, and V$_{\mathrm{bb2}}$ is delivered to WD.

In order to operate the proposed scheme, it is important to apply the same V$_{\mathrm{dd}}$ voltage in the on state and to apply the different optimized voltage to each gate in the off state. Therefore, we propose a new SWD circuit.

We constructed a new circuit that adds a pass transistor using PMOS to the conventional SWD circuit. The circuit transmits the same V$_{\mathrm{pp}}$ voltage to WD1 and WD2 in the on state. In the off state, V$_{\mathrm{bb2}}$ is transmitted to WD1, but a V$_{\mathrm{bb2}}$+V$_{\mathrm{th}}$ voltage is applied to WD2 while passing through the pass transistor.

Additionally, the effect of the number of gates on GIDL was evaluated. As the number of gates increased, GIDL decreased. However, owing to the decrease in the area of the gate, the resistance of the word-line increases; thus, a close additional review is required before use in an actual process. Finally, the multi-gate BCAT structure and modified circuit are compatible with the existing CMOS process and are also available for 3D stacked and vertical DRAM.

Fig. 12. Configuration of NMOS and PMOS pass transistors.
Fig. 13. The modified select-word line driver circuit diagram.
Fig. 14. Output characteristic of SWD circuit as shown in Fig. 12.


In this study, we evaluate the GIDL current in the DRAM cell transistor. A multi-gate BCAT structure was proposed to minimize the GIDL current. The multi-gate BCAT is a structure in which two metal gates are placed, which reduces the GIDL by applying different voltages to the gates. Applying an optimized voltage to the upper gate alleviates the electric field that causes tunneling between the drain and the gate. In the TCAD simulation, GIDL was reduced by approximately four orders in the proposed structure compared with the poly-Si BCAT structure. To operate the proposed BCAT structure, we modified the existing SWD circuit by adding one transistor.


This paper was supported by research funds for newly appointed professors of Gangneung-Wonju National University in 2021 and the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (2021R1G1A1093786). This research was supported by the National R&D Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (NRF-2022M3I7A1078936). This research was supported by "Regional Innovation Strategy (RIS)" through the National Research Foundation of Korea(NRF) funded by the Ministry of Education (MOE)(2022RIS-005)


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Chang Young Lim

Chang Young Lim has been studying in the Department of Electronic Engineering at Gangneung-Wonju National University (GWNU, Korea) from 2018 to 2022, His current research interests include MOS devices for DRAM memory at the Intelligent Semiconductor Device & Circuit Design Laboratory (ISDL) according to Professor Min-Woo Kwon.

Min-Woo Kwon

Min-Woo Kwon received B.S. and Ph. D. degrees in department of Electrical and Computer Engineering from Seoul National University (SNU) in 2012 and 2019, respectively. From 2019 to 2021, he worked at the Samsung semicon-ductor Laboratories, where he contributed to the development of 1x nm DRAM cell transistor and its characterization. In 2021, he joined Gangneung-Wonju National University (GWNU) as an assistant professor in the Department of Electric Engineering, where he is currently a professor. His current research interests include the design and fabrication of neuromorphic device (memristor synaptic device, Neuron circuit), steep switching device (FBFET), DRAM cell transistors and 2-dimensional nano-materials.