SeongKiho^{1}
HanJaeSoub^{1}
KimSungEun^{2}
ShimYong^{1,*}
BaekKwangHyun^{1,*}

(School of Electrical and Electronics Engineering, ChungAng University, Seoul 06974,
Korea)

(Electronics and Telecommunications Research Institute (ETRI), Daejeon 34129, Korea)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Analogtodigital converter, successive approximation register, oversampling, noise shaping, mismatch error shaping
I. INTRODUCTION
Modern IoT devices demand high resolution, power efficient ADCs for sensor interfaces
such as human body communication, edge computing, and biomedical sensors. Successive
approximation register (SAR) ADCs are architectures that are well known for their
technology scalability. They are also recognized for their power and area efficiency
due to their digitally based building blocks. However, realizing high resolution while
maintaining the advantages of SAR ADCs is problematic due to thermal noise such as
kT/C and comparator noise. This is because in order to mitigate such noise, the resolution
of the CDAC must be increased. Additionally, a lownoise comparator that consumes
a lot of power is also required. In the case of CDAC, total capacitance increases
exponentially with resolution, which occupies a large area while increasing the power
consumption of the driving buffer as well. Given these factors, the benefits of SAR
ADCs tend to diminish with increasing resolution.
On the other hand, deltasigma modulation (DSM) architectures are traditionally regarded
as the most promising candidates for highresolution ADCs due to their oversampling
and noise shaping (NS) characteristics. While these noise reduction effects do indeed
improve SNR performance by suppressing overall noises, the disadvantage is that DSM
architectures require powerhungry op amps, which occupy large areas and cannot easily
scale with technology. Furthermore, flash ADC used as a multibit quantizer in DSM
architectures typically offers lower resolutions, which in turn require a higher oversampling
ratio (OSR) to achieve high SNR. It leads to a decrease in power efficiency.
Therefore, NSSAR ADC, a hybrid architecture that combines DSM and SAR ADC to achieve
high SNR while maintaining both advantages, has become a promising candidate for highresolution
ADCs in recent years ^{[1}^{41]}. In this hybrid architecture, the SAR ADC is used as a multibit quantizer and concurrently
as a feedback DAC which processes the residue to achieve noise shaping performance.
Fig. 1 compares the NSSAR ADCs with conventional SAR and DSM ADCs, which have been published
in major conferences ^{[42]}. The solid line and dashed line indicate 180 dB of Schreier FigureofMerit (FoM$_{\mathrm{S}}$
as shown in Eq. (1)) and 5 fJ/c.s of Walden FoM (FoM$_{\mathrm{W}}$ as shown in Eq. (2)), respectively. It shows that NSSAR ADCs are pioneers in terms of power efficiency,
as compared with conventional architectures. Reference ^{[36,}^{37]} have reviewed the NSSAR ADC to show the development of this architecture.
In this paper, the fundamentals of the NS and the advances in noise reduction techniques
for NSSAR ADCs are reviewed. In particular, the loop filter implementations have
been described in depth. The rest of this paper is organized as follows. Section II
provides the basic concept of NSSAR ADCs including oversampling and NS mechanisms.
Section III outlines the noise reduction techniques employed to realize NS characteristics
with residue processing loop filters while Section IV introduces kT/C noise cancellation
and CDAC mismatch error shaping (MES). Finally, Section V presents the advanced architectures
employed to overcome the limitations of NSSAR ADCs and Section VI concludes this
paper.
Fig. 1. Power efficiency comparison between NSSAR ADCs with conventional architectures[42].
II. BASIC OF NOISESHAPING (NS) SAR ADCS
1. Oversampling
Oversampling is a common method of improving the SNR by reducing quantization noise.
The oversampling ADC samples and quantizes the input signal at a much higher sampling
rate than the signal band. Therefore, a small fraction of quantization noise falls
into the signal band making it possible to filter the outband noise as shown in Fig. 2. The reduction of quantization noise by oversampling can be quantified as Eq. (3). For better understanding, the signaltoquantization noise ratio (SQNR) is considered
rather than SNR.
where $P_{signal}$ and $P_{q,noise}$ denote signal and quantization noise power, respectively.
The OSR is the ratio between the signal band ($f_{B}$) and Nyquist range ($f_{S}/2$).
According to the above equation, there is only a 3dB improvement in SQNR when OSR
is doubled. Therefore, a very high OSR is required for highresolution ADC designs,
which has the effect of degrading power efficiency. To overcome this limitation, NS
schemes are widely used along with oversampling.
Fig. 2. Quantization noise and noise transfer function (NTF).
2. Noise Shaping (NS)
Noise shaping is an essential technique and a basic concept of oversampling ADCs to
enhance noise reduction effects. This is achieved by attenuating inband noise through
a highpass noise transfer function (NTF) as shown in Fig. 2. The 1storder DSM can be an example for presenting the NS mechanism.
The 1storder DSM consists of a quantizer, a feedback DAC, and an integrator as described
in Fig. 3. The quantizer digitizes analog input with feedback DAC converting this digitized
data to an analog signal and subtracting from input, making residue voltage that contains
quantization noise. Eq. (4) shows a transfer function including quantization noise, $Q\left(z\right)$.
If the $H\left(z\right)$ is a simple discretetime integrator, $H\left(z\right)=z^{1}/\left(1z^{1}\right),$
then $D_{OUT}\left(z\right)$ can be expressed as follows.
Eq. (5) shows a simple delay signal transfer function (STF), $z^{1}$, and a highpass NTF,
$1z^{1}.$ Therefore, the SQNR including inband noise attenuation by NTF can be
expressed as Eq. (6).
Note that IBNG denotes inband noise gain, which is $IBNG=~ \int _{0}^{f_{B}}\left(\left
NTF\left(f\right)\right ^{2}/f_{B}\right)df$. If NTF is assumed to be $1z^{1}$,
Eq. (6) can be approximated as follows.
Eq. (7) shows that the SQNR increases 9dB when OSR is doubled. Fig. 4 compares the SQNR improvement between oversampling with and without NS.
Fig. 3. (a) Block diagram of the 1storder DSM; (b) signal flow diagram.
Fig. 4. SQNR improvement by oversampling with and without NS.
3. Noiseshaping (NS) SAR ADCs
NSSAR ADCs have been proposed as a means to overcome the shortcomings of DSM ADCs
while obtaining similar NS characteristics ^{[1]}. The proposed architecture replaces a quantizer and a feedback DAC of CIFFDSM as
a SAR ADC as shown in Fig. 5(a). And it realizes the NS using a finiteimpulseresponse and infiniteimpulseresponse
(FIRIIR) loop filter. The switchedcapacitor FIR filter samples the residue and IIR
filter integrates this residue. The signalflow diagram including the FIRIIR loop
filter can be modeled as in Fig. 5(b). Therefore, the overall transfer function is given by Eq. (7).
Even though ^{[1]} achieves a sharp NTF as shown in Fig. 6, the SNDR is limited due to additional noise generated by the FIRIIR filter. Furthermore,
a powerconsuming amplifier is still required. To overcome these limitations, various
noise reduction techniques have been proposed. In this paper, the NSSAR ADCs are
classified into active and passive topologies based on the loop filter implementations,
which are reviewed in more detail in the following section.
Fig. 5. (a) Block diagram of NSSAR ADC; (b) signal flow diagram[1].
Fig. 6. NTF comparison between NSSAR[1]and 1storder DSM ADC.
III. NOISE REDUCTION TECHNIQUES WITH RESIDUE PROCESSING
The most important factor of NSSAR ADCs is how to extract the residue and sum it
with the following input signal. There are thus two concerns 1) how to process the
residue and 2) how to implement the loop filter. With regard to residue processing,
both cascadedintegratorfeedforward (CIFF) and errorfeedback (EF) are common implementations.
In general, the CIFF structures have a feedforward path to process the residue and
sum it to the following input using a multiinput comparator, whereas the EF structures
have a feedback path and sum the residue to the input voltage directly on CDAC. Note
that the multiinput comparator introduces extra noise in CIFF and the chargesharing
summation in EF induces signal attenuation.
Fig. 7(a, b) and Fig. 8(a, b)shows signal flow diagrams and circuit implementations of CIFF and EF structures,
respectively. The corresponding transfer functions are as follows.
From the circuit implementation of each structure, Eq. (8) and (9) can be translated to Eq. (10) and (11), respectively.
Note that, the CIFF structure needs a highgain integrator to achieve ideal highpass
NTF. On the other hand, the EF structure does not require a high gain integrator but
requires a high accuracy opamp. This is because the gain of opamp directly controls
the zero of NTF.
Thus, while there are many efforts to alleviate the burden of high gain integrator
and multiinput comparator in CIFF structure such as passive integration and capacitor
stacking, gain calibrations are introduced to precisely control the gain of opamp
in EF structures. Table 1. summarizes and compares the CIFF and EF structures.
In terms of loop filter implementation, the loop filter for realizing the NTF of each
structure is implemented in two ways, namely active and passive topologies. Generally,
an active strategy uses op amps whereas the passive strategy uses simple switches
and capacitors to process the residue. More details of these loop filters are provided
in the following sections.
Fig. 7. (a) Signal flow diagram; (b) circuit implementation[1]of CIFF structures.
Fig. 8. (a) Signal flow diagram; (b) circuit implementation[13]of EF structures.
Table 1. Comparison between CIFF and EF
Structure

Residue Summation

Gain

Gain
Sensitivity

Limitation

CIFF

Multiinput comparator

High

Low

Extra noise

EF

Chargesharing

Medium

High

Signal attenuation

1. Active Loop Filter
Active loop filters show flexible and sharp NTF because the amplifier provides sufficient
gain. However, the active amplifier consumes large amounts of power which degrades
the efficiency of NSSAR. Therefore, much effort has been expended in a bid to reduce
the power consumption of active strategies.
As discussed in the previous section, the first implementation of NSSAR ADC is an
active strategy using the FIRIIR loop filter proposed in ^{[1]}. The switchedcapacitor FIR filter and the activeamplifierbased IIR filter samples
and integrates the residue, respectively. However, the proposed architecture presents
only moderate SNDR performance, even though it has sharp NTF, because the passive
residue sampling introduces considerable kT/C noise, with the active amplifier also
introducing more noise. Improving noise performance requires the addition of large
capacitors for residue sampling, while highgain, powerconsuming amplifiers are required
in the IIR filter if the additional noise is to be mitigated.
To relieve the tradeoff between kT/C noise and gain loss due to charge sharing in
switchedcapacitor FIR filter, an input buffer, implemented as an openloop amplifier
between CDAC and residue sampling capacitor, is required ^{[6]} as shown in Fig. 9. Although it provides a gain of 2 alleviating kT/C noise in the FIR filter, the input
buffer and active amplifier in the IIR filter together consume 37% of the total power.
In ^{[10,}^{11]}, the openloop dynamicamplifierbased FIRIIR filter is proposed as a means of reducing
these extra power consumptions. Reference ^{[11]} replaces the input buffer and active integrator with low power openloop dynamic
amplifiers and ^{[10]} proposes a gainenhanced dynamic amplifier as the input buffer. Moreover, ^{[10]} greatly reduces the residue sampling capacitor, such that the activeamplifierbased
IIR filter can be substituted by a simple switchedcapacitor integrator as shown in
Fig. 10. However, the drawback is that the openloop dynamic amplifier is sensitive to PVT
variation, which degrades the NTF and limits the NS performance. To compensate for
this drawback, ^{[13]} proposes background calibration for dynamic amplifiers which increases design complexity.
Reference ^{[25]} proposes a calibrationfree PVTrobust closedloop 2stage dynamic amplifier to simplify
the design complexity of the calibration as illustrated in Fig. 11. Due to the fact that the gain of the closedloop amplifier is set by capacitor ratios,
it is robust in the presence of PVT variations. In ^{[27]} and ^{[29]}, the PVTinsensitive voltagetimevoltage converter and PVTrobust source followerbased
unit gain buffer for active residue processing are proposed , respectively.
Fig. 9. FIRIIR loop filter with input buffer[6].
Fig. 10. FIRIIR loop filter with dynamic amplifier and switchedcapacitor implementation[10].
Fig. 11. PVTrobust closedloop 2stage dynamic amplifier[25].
2. Passive Loop Filter
A passive loop filter is a simple, PVT robust, and scalingfriendly strategy because
it consists of switches and capacitors. It is more powerefficient than an active
loop filter given that it does not need a powerconsuming amplifier. However, the
passive strategy suffers from charge sharing in switchedcapacitor operation and shows
mild NTF due to the insufficient gain. Therefore, many efforts have been expended
on reducing the charge sharing and providing adequate gain for the passive loop filter.
The first fully passive NSSAR ADC is proposed in ^{[2]}. The proposed architecture utilizes the switchedcapacitor circuit for the purpose
of residue sampling and integration. Residue summation is realized by a multiinput
comparator as shown in Fig. 12. However, switchedcapacitor residue sampling attenuates the input signal by factor
of 2 while the charge sharing of residue integration degrades NTF. This architecture
is improved in ^{[3]} to 2ndorder NS. The 2ndorder NS is realized with the application of capacitor stacking
^{[43]} thus achieving passive gain but this does nothing to resolve signal attenuation limitations.
Reference ^{[4,}^{8]} eliminates this signal attenuation and realizes sharper NTF than ^{[2,}^{3]}. In addition, the relative gain between input signal and integrated residue is realized
through the input transistor sizing of the multiinput comparator as shown in Fig. 13. The multiinput comparator not only provides relative gain but also realizes signal
summation. However, the large extra input pair which provides relative gain also introduces
additional thermal noise, while the residue sampling and integration introduce extra
unshaped kT/C noise, increasing the overall noise.
To alleviate the extra thermal noise from the multiinput comparator, ^{[18]} proposes a passive signalresidue summation scheme as shown in Fig. 14. This architecture achieves the residue summation by serialization of CDAC and integration
capacitor. Moreover, the differential residue sampling on backtoback capacitors
provides a passive gain of 2 thereby eliminating the multiinput comparator. Even
so, it achieves only 2x passive gain so resulting in mild NTF while the small residue
sampling capacitor introduces large kT/C noise.
In ^{[23]}, the differential integration with split capacitor and capacitor stacking are presented
as described in Fig. 15. This scheme eliminates residue sampling and provides 4x the passive gain, which
obviates the need for a multiinput comparator. Therefore, it reduces the kT/C and
comparator noise significantly. However, it remains difficult to increase gain because
the passive gain using capacitor stacking is sensitive to parasitic capacitance.
Fig. 12. Fully passive NSSAR ADC[2].
Fig. 13. Passive NSSAR ADC with relative gain using multiinput comparator[4].
Fig. 14. Passive signalresidue summation with 2x passive gain using capacitor stacking[18].
Fig. 15. Passive residue integration with 4x passive gain using capacitor split and stacking[23].
IV. ADDITIONAL NOISE AND ERROR REDUCTION TECHNIQUES
Although the NTF efficiently suppresses quantization and comparator noise, additional
noise and error that are not shaped by NTF remain. These additional nonidealities,
such as the CDAC mismatchinduced error and kT/C noise, serve to limit the SNDR of
the NSSAR ADCs. This section, therefore, presents the noise and error reduction techniques
to mitigate these additional nonidealities.
1. CDAC Mismatch
The CDAC mismatch introduces additional unshaped errors which cause harmonic distortion
and increase the inband noise floor. It can be modeled as an additive noise, ε(z),
in a loop filter as shown in Fig. 16. Then $D_{OUT}\left(z\right)$ can be expressed as follows.
Calibration and mismatch shaping (MS) are commonly used methods to relieve the CDAC
mismatch. The first one, calibration, including both the foreground and background
method, compensates for CDAC mismatch in the analog and digital domain, and thus it
can cancel errors from the CDAC mismatch. Foreground calibration is more widely used
than the background method due to the greater simplicity of its implementations. However,
foreground calibration needs additional calibration phase interrupting normal operation
of ADCs.
The second one, MS suppresses the inband noise and distortion from CDAC mismatch.
The wellknown MS are the dynamic elements matching (DEM) ^{[44]} and dataweighted averaging (DWA) ^{[45]}. An element selection logic (ESL) randomizes and rotates the DAC capacitor as shown
in Fig. 17. Therefore, the DEM and DWA suppresses and shapes the inband harmonic distortion
and noise, respectively. The drawbacks of these DEMbased MS methods are complexity
and long delay. If higher order shaping is to be achieved, more complicated logic
is required, with ESL complexity growing exponentially as CDAC resolution increases.
To limit complexity of the ESL, some designs shuffle only a few MSBs, despite the
continuing presence of errors from LSBs.
Another MS technique is mismatch error shaping (MES) ^{[6]}. Conceptually, it is similar to the NS mechanism. It captures the mismatch error
and feeds it back by presetting the LSBs of CDAC before sampling. Fig. 18 illustrates the 1storder MES operations. During the sampling phase (in Fig. 18(a)), the LSB parts are preset to hold the previous mismatch error, $z^{1}E_{M}\left(z\right)$.
Following this, the LSB parts are reset in the conversion phase (in Fig. 18(b)) to subtract the previous error from the current error, $E_{M}\left(z\right)z^{1}E_{M}\left(z\right)$.
Therefore, it realizes a high pass shaping of the CDAC mismatch error, $\left(1z^{1}\right)E_{M}\left(z\right)$.
The MES is easier to implement than DEM because it does not require complex logic.
However, the MES suffers input dynamic range loss due to LSB presetting.
Fig. 16. Signal flow diagram of (a) CIFF; (b) EF structures including noise from CDAC mismatch.
Fig. 17. Block diagram of a simple DEM.
Fig. 18. Block diagram of a simple MES: (a) sampling phase; (b) conversion phase.
To alleviate this loss, references ^{[6,}^{23,}^{40]} apply the DEM or DWA for the MSBs and MES for LSBs. These references can also mitigate
the complexity of DEMbased implementations by applying DEM techniques to only some
MSBs.
2. kT/C Noise
Sampling kT/C noise is one of the unshaped noises in NSSAR ADCs. Even though oversampling
relieves kT/C noise by OSR, the disadvantage is that increasing OSR limits the signal
bandwidth. Fig. 19 shows sampling circuit and its equivalent noise modeling. The onresistance of the
sampling switch introduces the noise power spectral density (PSD) of $4kTR_{ON}$ and
its equivalent noise bandwidth (ENBW) is $1/4R_{ON}C_{S}$. For a simple singlepole
system, the total noise power ($\overline{v_{n}^{2}}$) can be expressed as the product
of the PSD and ENBW ^{[46]}.
Therefore, only the sampling capacitor appears in total noise power. Reference ^{[46,}^{47]} propose a kT/C noise reduction scheme using feedback topology by decoupling the noise
PSD and ENBW. Fig. 20(a) and (b) shows a sampling circuit with a singlestage and twostage amplifier, respectively.
They reduce total sampling noise as follows.
Note that $\gamma $ is the amplifier noise factor ^{[46,}^{47]}.
If the amplifier gain, $g_{m,m1}$ is large, the noises can be approximate as
It shows that the sampling noise can be adjusted by $R_{L},R_{FB},$ and $g_{m2}$ while
$C_{S}$ remains constant.
References ^{[22,}^{30,}^{46,}^{48]} introduce the active sampling kT/C noise canceling scheme as shown in Fig. 21. This scheme captures the noise on an additional series capacitor ($C_{N}$) which
is placed between the preamplifier and the latch of the comparator. Then this noise
would be canceled in the next phase. Although the additional series capacitor induces
extra noise, this is attenuated by preamplifier gain. However, this noise cancellation
cannot be employed directly in NSSAR.
This is because the noise cancellation occurs inside the comparator, which causes
the noise captured by $C_{N}$ to be shaped by NTF. To overcome this limitation, references
^{[22,}^{30]} perform the noise cancellation in the precomparator feedback path as shown in Fig. 22. Although EF structure has been adopted to validate the precomparator kT/C noise
cancellation, they can also be applied to CIFF structures. These techniques alleviate
the burden of the ADC input driver by reducing the sampling capacitor.
Fig. 19. (a) Simple sampling circuit; (b) its equivalent noise modeling[46].
Fig. 20. kT/C noise reduction using feedback topology with (a) singlestage; (b) twostage amplifier[46,47].
Fig. 21. kT/C noise cancellation using series capacitor[46,48].
Fig. 22. Precomparator kT/C noise cancellation[22,30].
V. ADVANCED ARCHITECTURES (FUTURE TRENDS)
Even though the NSSAR ADCs are a highefficient and lowcost architecture, they still
have inherent limitations, such as the challenge of driving large sampling capacitors
for highresolution NSSAR and limited BW due to the oversampling. This section summarizes
the advanced architectures employed in an effort to address these limitations.
1. Hybrid Architectures
In ^{[49]}, the NSSAR ADC is employed as a quantizer in continuous time (CT)DSM ADC so as
to achieve a powerefficient 3rdorder NS effect. It is implemented by means of a
1storder CTDSM ADC and a fully passive 2ndorder NSSAR. Thanks to the 2ndorder
NSSAR, the overall loop filter can be simplified given that it needs only a single
active amplifier to realize the 3rdorder NS effect.
In ^{[50,}^{51]}, the pipelined NSSAR ADC is proposed to solve BW limitation. The 2ndstage residue
is summed with 1ststage residue, which amplified by interstage residue amplifier.
Then further quantized in 2ndstage, realizing EF NS. Since the 2ndstage integrates
the residue during the 1ststage sampling and conversion a highspeed pipeline operation
is maintained.
In ^{[32,}^{39]}, the multistage noiseshaping (MASH) ADC is presented. Reference ^{[32]} implements NSSAR assisted pipelined ADC, realizing 20 MASH. The 2ndorer NSSAR
ADC shapes the interstage gain error and nonlinearities of pipelined ADC. It relaxes
the gain sensitivity of conventional pipelined ADC. Reference ^{[39]} proposes 11 MASH structure using fully passive NSSAR and VCO ADC alleviating the
burden of driving large sampling capacitors. The proposed MASH ADC allows for the
use of the lowresolution NSSAR as a 1ststage, allowing for small input capacitors
while signal attenuation of passive NSSAR is addressed by leveraging it to linearize
the VCO.
2. Timeinterleaved Architectures
The oversampling ADCs suffer from the limited BW due to the OSR. Timeinterleaved
(TI) architecture is a wellknown technique for increasing BW. However, this TI strategy
is not a straightforward solution for NSSAR ADCs due to the residue process. Because
the multiple channels (subADCs) operate in parallel with overlapping the conversion
cycles, the residue from the previous channel cannot be fed back to the adjacent channel
directly as shown in Fig. 23(a). To apply the TI technique to NSSAR ADC, ^{[16]} proposes the midway feedback which is multiple feedback to other channels as shown
in Fig. 23(b). Thanks to the inherent delay in midway feedback, this allows highorder NTF to be
realized. However, as the TI NSSAR ADC in ^{[16]} is implemented on EF architecture, it requires a summing amplifier consuming large
static power. Moreover, it shows mild NTF to ensure stability due to the gain of the
amplifier being vulnerable to PVT variations. To overcome these drawbacks of the EF
structure, ^{[28,}^{31]} realizes the TI NSSAR ADC using CIFF architecture. ^{[31]} uses the multiinput comparator as a feedforward summation and ^{[28]} adopts the passive summation using capacitor stacking scheme. Therefore, the CIFFbased
TI NSSAR ADCs show better power efficiency than EFbased structure due to unnecessariness
of a static amplifier.
Fig. 23. (a) Interchannel noncasual feedback; (b) midway feedback proposed in[16].
VI. CONCLUSION
In this paper, the fundamentals of NSSAR ADCs are described. Additionally, the noise
reduction techniques including the implementation of a loop filter, CDAC MES, and
kT/C noise cancellation are also reviewed. The loop filters to realize NS effects
are categorized as either active or passive topology with the advancements of each
topology provided. Additional noise reduction techniques such as CDAC MES and kT/C
cancellation to suppress the unshaped noise by NTF are presented. Advanced hybrid
architectures capable of overcoming the inherent limitations of NSSARs are also summarized.
Table 2 compares and summarizes the performance, feedback structure, loop filter implementation,
and features of NSSAR ADCs with chip measurement results.
Table 2. Comparison and summary
Year

Publication

BW
(MHz)

Power
($\mu$W)

OSR

NS
order

SNDR
(dB)

SFDR
(dB)

FoMS
(dB)

FoMW
(fJ/c.step)

Structure

Loop
Filter

Features

2012

^{[1]} JSSC

11

806

4

1

62.1

72.5

163.5

35

CIFF

Active

First CIFF NSSAR ADC

2015

^{[2]} VLSIC

6.25

120.7

4

1

58



165.2

14.8

EF

Passive

First EF NSSAR ADC

2016

^{[3]} ASSCC

8

252.9

4

2

64.9



169.9

11

EF

Passive

Passive gain with cap. stacking

^{[4]} ESSCIRC

0.125

61

8

1

74

95

167.1

59.6

CIFF

Passive

Multiinput comp. for relative gain

^{[5]} VLSIC

0.002

37.1

25

3

98

111.8

175.3

143

CIFF

Active

DEM, modulation dither effect

^{[6]} JSSC

0.001

15.7

500

1

101

105.1

179

85.6

CIFF

Active

DWA, MES

2017

^{[7]} CICC

1.75

70.5

8

1

68.1

84.8

172

9.7

CIFF

Active

Least squares estimationbased calibration

^{[8]} VLSIC

0.262

143

16

2

80



172.6

33.4

CIFF

Passive

Trilevel majority voting

^{[9]} VLSIC

25

2400

6

1

69.1

81.2

169.2

20.7

CIFF

Passive

Noise quantizer technique

^{[10]} ISSCC

5

460

13.2

1

79.7

92.6

180.1

5.8

CIFF

Active

Gainenhanced dynamic amp.

^{[11]} CICC

0.25

257.8

20

3

83.4

96.5

173.3

42.6

CIFF

Active

Openloop integrator, binary DEM

2018

^{[12]} ASSCC

0.05

60

16

2

72

78.7

161.2

184.4

CIFF

Passive

Majority voting, cycle DEM

^{[13]} ISSCC

0.625

84

8

2

79

89

177.7

9.2

EF

Active

NTF optimization

^{[14]} MWSCAS

0.002

74.2

32

1

78.8

87.6

153.1

2605.9

EF

Active

2C DAC

2019

^{[15]} ASSCC

5

108.7

4

2

68.2

84.6

174.8

5.2

CIFF

Active

Optimal 2zeros & 2poles, compiled layout

^{[16]} JSSC

50

13000

4

4

70.4

88

166.3

48

TIEF

Active

Timeinterleaved

^{[17]} CICC

2

2130

20

2

73.8

87.3

163.5

133

CIFF

Passive

Bufferembedded

^{[18]} ISSCC

40

1250

4

1

66.6

77.4

171.6

9

CIFF

Passive

Passive signalresidue summation

^{[19]} ASSCC

0.625

130

8

2

71

81

167.8

35.9

EF

Active

Dynamic amp., ring amp.

2020

^{[20]} TCASI

0.625

70

8

2

74.6



174.1

12.8

EF

Active

Configurable bandpass, clockcontrolled amp.

^{[21]} JSSC

0.1

120

10

4

87.6

102.8

176.8

30.6

Cas.EF

Active

Multiphase settling amp.

^{[23]} ISSCC

0.04

67.4

25

1

90.5

102.2

178.2

30.8

CIFF

Passive

Passive gain with cap. stacking, 2ndorder MES

^{[24]} MWSCAS

0.002

40.8

32

1

82.6

90.9

159.5

925.1

EF

Active

2C DAC, correlated double sampling

^{[25]} JSSC

0.625

107

8

2

83.8

94.3

181.5

6.8

CIFF

Active

Closedloop dynamic amp.

^{[26]} TCASII

3.125

1240

16

2

77

90.1

171

34.3

CIFF

Active

Lossless integrator

2021

^{[27]} ASSCC

0.625

71

8

2

73.8

88.1

173.2

14.2

EF

Active

Openloop VTV converter

^{[28]} ISSCC

80

2560

4

1

66.3

73.6

171.2

9.5

TICIFF

Passive

Coarsefine segmentation

^{[29]} ISSCC

0.25

340

10

4

93.3

104.4

182

18

CIFF

Active

Cap. stacking, dynamic buffering

^{[30]} JSSC

0.625

119

8

3

84.8

103

182

6.7

EFCIFF

Active

kT/C cancellation, floating inv. dynamic amp.

^{[31]} JSSC

50

8500

4

2

69.1



166.8

36.5

TICIFF

Passive

Fully dynamic

^{[32]} ISSCC

25

1260

8

2

75

92.1

178

5.5

CIFF

Passive

20 MASH, NSSAR assisted pipeline

2022

^{[33]} ISSCC

0.5

133.88

5

4

84.1

97

179.8

10.2

EFCRFF

Active

EFcascaded resonator FF, bufferembedded

^{[34]} TCASII

0.625

113.02

16

2

79.3

90.4

176.7

12

EF

Active

Unitygain buffer

^{[35]} JSSC

0.125

96

8

3

79.6

94.8

170.7

49.4

EFCIFF

Active

Ditherbased digital calibration

^{[39]} JSSC

1.1

160

11

1

71.5

81

169.9

23.7

CIFF

Passive

11 MASH using NSSAR & VCO

^{[40]} JSSC

5

8006

6

2

84.2

97.3

172.2

60.4

CIFF

Active

Bufferembedded

^{[41]} JSSC

0.03125

7.3

16

2

80

98

176.3

14.3

CIFF

Active

Dutycycled amp. digitalpredicted MES

ACKNOWLEDGMENTS
This work was supported in part by ChungAng University Research Grants in 2020,
and in part by Institute of Information & Communications Technology Planning & Evaluation
(IITP) grant funded by the Korea government (MSIT) (No. 2020001294, Development
of IoT based edge computing ultralow power artificial intelligent processor).
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Kiho Seong received the B.S. and M.S. degrees at School of Electrical and Electronics
Engineering from ChungAng University (CAU), Seoul, Korea, in 2018 and 2020, respectively.
He is currently working toward the Ph.D. degree in electrical and electronics engineering.
His research interests include highspeed and highresolution analogtodigital converter
(ADC).
JaeSoub Han received the B.S. and M.S. degrees at School of Electrical and Electronics
Engineering from ChungAng University (CAU), Seoul, Korea, in 2019 and 2021, respectively.
He is currently working toward the Ph.D. degree in electrical and electronics engineering.
His research interests include high speed direct digital frequency synthesizer (DDFS)
and lowpower phaselocked loop (PLL).
SungEun Kim was born in South Korea in October 1978. He received the B.S. degree
in electrical and computer engineering from Hanyang University, Seoul, South Korea,
in 2002, and the M.S. degree in electrical engineering from the Korea Advanced Institute
of Science and Technology (KAIST), Daejeon, South Korea, in 2004. Since March 2004,
he has been with the Electronics and Telecommunications Research Institute (ETRI),
Daejeon, where he is currently a Principal Researcher. He has been primarily involved
in researching analog circuit design for human body communications and power management
of energy harvesting systems.
Yong Shim received the B.S. and M.S. degrees in electronics engineering from Korea
University, in 2004 and 2006, respectively, and the Ph.D. degree from the School of
Electrical and Computer Engineering, Purdue University, West Lafayette, IN, in 2018.
He was a Memory Interface Designer with Samsung Electronics, Hwaseong, from 2006 to
2013. At Samsung, he has worked on the design and development of a memory interface
for synchronous DRAMs (DDR1 and DDR4). He is currently an Assistant Professor with
ChungAng University. Prior to joining ChungAng University, in 2020, he was an SRAM
Designer with Intel Corporation, Hillsboro, OR, from 2018 to 2020, where he was involved
in designing circuits for superscaled nextgeneration SRAM cache design. His research
interests include neuromorphic hardware and algorithm, inmemory computing, robust
memory interface design, as well as emerging devices (RRAM, MRAM, and STO) based unconventional
computing models.
KwangHyun Baek received the B.S. and M.S. degrees from Korea University, Seoul,
Korea, in 1990 and 1998, respectively. He received the Ph.D. degree in electrical
engineering from the University of Illinois at UrbanaChampaign (UIUC), IL, USA, in
2002. From 2000 to 2006, he was with the Department of HighSpeed MixedSignal ICs
as a senior scientist at Rockwell Scientific Company, formerly Rockwell Science Center
(RSC), Thousand Oaks, CA, USA. At RSC, he was involved in development of highspeed
data converters (ADC/DAC) and direct digital frequency synthesizers (DDFS). He was
also with Samsung Electronics from 1990 to 1996. Since 2006 he has been with the School
of Electrical and Electronics Engineering, ChungAng University (CAU), Seoul, Korea,
where he is a faculty member. His research interests include highperformance analog
and digital circuits such as lowpower ADCs, highspeed DACs, hybrid frequency synthesizers
(PLLs, DDFSs), highspeed interface circuits (CDRs, SerDes), PMIC, and near thresholdvoltage
(NTV) circuits.