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  1. (Department of Electric Engineering, Pukyong National University, Busan 48513, Korea)
  2. (Department of Electronic Engineering, Sogang University, Seoul 04107, Korea)
  3. (Department of Electronic Engineering, Myongji University, Yongin 17058, Korea)

Tunnel field-effect transistor, on-current variation, work function variation, quantized current


Recently, as the use of mobile devices increases, power dissipation in integrated circuits (ICs) has been concerned dramatically. To solve this, the amount of power consumption and size of the complementary metal-oxide semiconductor (CMOS) device have trends for reduction [1-7]. In the trends of development, the key point of this reduction is lowering supply voltage while achieving a high on/off current ratio. However, due to the physical limitations of metal-oxide-semiconductor field-effect transistor (MOSFET), the supply power cannot be reduced because the theorical subthreshold swing (SS) cannot be lower than 60 mV/dec. To overcome this problem, many researching groups have researched a tunneling field-effect transistor (TFET) for its good electrical performance in low power circumstance and CMOS compatibility [8-11]. Moreover, the electrical performance of TFET can be improved dramatically by applying the high-${\kappa}$/metal gate (HKMG) technology for small equivalent oxide thickness (EOT), low gate leakage current and low gate resistance [12-21]. Therefore, the TFET with HKMG has notable electrical performance for low voltage operation due to its small SS, low-level off-state current ($\textit{I}$$_{\mathrm{off}}$). Thus, it is expected that the TFET is applicable to the real industry as a substitutional or complementary device for conventional CMOS. Despite these advantages, the metal gate occurs work function (WF) variation (WFV) issue due to the non-uniformity of various metal gate grains by size and by orientation according to the fabrication processes [22-31] Therefore, adopting the TFET to the real CMOS circuits, the electrical performance variations according to the WFV must be scrutinized. In previous research, most of studies have been noticed on variation ranges of the MOSFET and TFET [17, 32, 33]. However, WFV effect on the current variation characteristics about the MOSFET and TFET hasn’t been studied rigorously [34].

In this research, an investigation has been performed to study the relation between on-current ($\textit{I}$$_{\mathrm{on}}$) and WFV in the TFET with help of technology computer-aided design (TCAD) simulation. Comparing TFET and MOSFET, the TFET can be identified for multiple quantized $\textit{I}$$_{\mathrm{on}}$. The contents of this paper are as follows. In Section II, the structure and simulation models of studied the TFET and MOSFET are explained. The WFV induced by the grain of the metal gate is set reflecting the actual gate physical properties. In Section III, the quantitative analysis is performed by confirming location of metal grains and BTBT rate to monitor the variation of $\textit{I}$$_{\mathrm{on}}$ (${\Delta}$$\textit{I}$$_{\mathrm{on}}$), with various bias.


The three-dimensional (3-D) structure of planar TFET and MOSFET is shown in Fig. 1(a). This technology computer-aided design (TCAD) simulation is performed by Synopsys Sentaurus. All parts of source, drain, and channel consist of silicon. To focus on the WFV in TFET and MOSFET rigorously, the physical dimension is set for suppressing short channel effect. Commonly in TFET and MOSFET, the channel length ($\textit{L}$$_{\mathrm{ch}}$) of 50 nm and gate oxide thickness ($\textit{T}$$_{\mathrm{OX}}$) of 1 nm are set. The channel width ($\textit{W}$) varies in size from 10 to 50 nm. The body doping concentration ($\textit{N}$$_{\mathrm{B}}$) of 10$^{17}$ cm$^{-3}$ (boron, p-type). The source doping concentration ($\textit{N}$$_{\mathrm{S}}$) and drain doping concentration ($\textit{N}$$_{\mathrm{D}}$) of 10$^{20}$ cm$^{-3}$ are consist of same doping types of arsenic in the MOSFET. Contrastively, boron concentration in the TFET source $\textit{N}$$_{\mathrm{S}}$ and arsenic concentration in the drain $\textit{N}$$_{\mathrm{D}}$ are 10$^{20}$ cm$^{-3}$. The gate area is divided 10 nm ${\times}$ 10 nm units with random work function (4.4 eV, 4.6 eV). In fabrication process, the sputtered TiN at gate has 10 nm grain size and crystallized primarily in <200> (60 %) and in <111> (40 %) corresponding to WF value of 4.6 eV and 4.4 eV [35-37]. All the parameters for device structure are summarized in Table 1.

Table 1. Margin specifications


Value $^{\mathrm{a}}$



Source doping conc. (\textit{N}$_{\mathrm{S}}$)

10$^{20}$ cm$^{-3}$(arsenic)        10$^{20}$ cm$^{-3}$(boron)

Drain doping conc. (\textit{N}$_{\mathrm{D}}$)

10$^{20}$ cm$^{-3}$

Body doping conc. (\textit{N}$_{\mathrm{B}}$)

10$^{17}$ cm$^{-3}$

Gate Work-function

4.6 eV / 4.4 eV

Channel length (\textit{L}$_{\mathrm{ch}}$)

50 nm

Channel width (\textit{W})

10 nm ~ 50 nm

Metal grain size

10 nm

Gate oxide thickness (\textit{T}$_{\mathrm{OX}}$)

1 nm

Fig. 1. (a) 3-D structure of planar the TFET and MOSFET device; (b) Top view of the TFET and MOSFET. The WFV is reflected in random from 4.4 eV to 4.6 eV; (c) Calibration of the simulated transfer characteristics at $\textit{V}$$_{\mathrm{DS}}$ of 1 V. The BTBT models are calibrated by experimental data of the fabricated planar Si TFET.

The electrical characteristics of the MOSFET and TFET are simulated with Shockley-Read-Hall (SRH) generation-recombination model and dynamic nonlocal band to band tunneling (BTBT) model. The dynamic nonlocal BTBT model is necessary to examine BTBT in TFET. Because it can dynamically calculate and determine all tunneling paths grounded on the energy band profile. Concretely, the BTBT model is calibrated to the experimental data for planar Si TFET. The BTBT generation rate per unit volume ($\textit{G}$) in the uniform electric field limit is calculated by

$ G=~ A\left(\frac{F}{F_{0}}\right)^{P}\exp \left(-\frac{B}{F}\right) $

where $\textit{F}$$_{0}$ = 1 V/m and $\textit{P}$ = 2.5 for an indirect BTBT. In (1) there are coefficients A, B, whereas here $\textit{A}$$_{\mathrm{Si}}$, $\textit{B}$$_{\mathrm{Si}}$ are used the Kane parameters of Si, and $\textit{F}$ is electric field. For accurate simulation, we calibrate the model parameters by extracting current from the fabricated planar TFET. Fig. 1(c) shows the accuracy of calibration model. After the calibration, Kane parameters in TFET are set to $\textit{A}$$_{\mathrm{Si}}$ = 1.0 ${\times}$ 10$^{17}$ and $\textit{B}$$_{\mathrm{Si}}$ = 1.0 ${\times}$ 10$^{6}$ V/cm [38]. The used models in simulation are summarized in Table 2.

Table 2. Model in TCAD simulation



Bandgap narrowing

Old slot boom

Fermi statistic


Phonon scattering

Constant mobility

SRH recombination


Band to band tunneling

Nonlocal BTBT

Work-Function Variation

4.6 / 4.4 eV (60 % / 40 %)



Bandgap narrowing

Old slot boom

Fermi statistic



Fig. 2 shows the transfer characteristics of the 3-D Planar TFET (Fig. 2(a)) and MOSFET (Fig. 2(b)) with various width at 1.0 V of drain voltages ($\textit{V}$$_{\mathrm{DS}}$). According to TiN grain orientation, the metal grain variations were generated by randomization algorithms provided in the Sentaurus tool. In each width, the 30 samples are simulated by uniquely randomized metal gate grain profiles. Although all parameters except for the type of source doping are implemented equally in MOSFET and TFET, the $\textit{I}$$_{\mathrm{on}}$ and threshold voltage ($\textit{V}$$_{\mathrm{T}}$) values of each device are different due to different operation mechanisms. Therefore, we focus on variation but for comparison of devices. Fig. 2(c) and (d) show the transfer characteristics that occur when $\textit{V}$$_{\mathrm{DS}}$ is given 0.1~V and 1.0 V by width in TFET and MOSFET. We found three facts in the figure. First, when 1.0 V-$\textit{V}$$_{\mathrm{GS}}$ is applied in the TFET, the current is scattered indiscriminately, unlike quantized current at 2.0 V-$\textit{V}$$_{\mathrm{GS}}$. Considering depletion length with magnitude of $\textit{V}$$_{\mathrm{GS}}$, at low $\textit{V}$$_{\mathrm{GS}}$, the tunneling area is widened as the depletion region of TFET is enlarged, resulting in a smaller amount of electron tunneling. And the TFET current is affected by WF in the region where the channel is formed [35]. On the other hand, as $\textit{V}$$_{\mathrm{GS}}$ increases, the position of the WF affecting TFET moves closer to the source and channel junctions, and the quantized current is finally observed. Second, as the $\textit{V}$$_{\mathrm{DS}}$ grows larger, only ${\Delta}$$\textit{I}$$_{\mathrm{on}}$ in TFET become larger. On the contrary, in MOSFET, the ${\Delta}$$\textit{I}$$_{\mathrm{on}}$ by the $\textit{V}$$_{\mathrm{DS}}$ is not well observed. Because channel potential in TFET is affected by $\textit{V}$$_{\mathrm{DS}}$. Third, $\textit{I}$$_{\mathrm{on}}$ in TFET is quantized to several specific levels according to width size. This dependency is also observed in only TFET. With smaller the width size, the less ${\Delta}$$\textit{I}$$_{\mathrm{on}}$ especially quantized with specific current level is observed.

Fig. 2. When the $\textit{V}$$_{\mathrm{DS}}$ is 1.0 V, there are various width (10 nm \textasciitilde{} 50 nm) in (a) TFET; (b) MOSFET. For each width, the 30 samples are simulated by randomly work function. When $\textit{V}$$_{\mathrm{DS}}$ is applied 0.1 V and 1.0 V, the the $\textit{I}$$_{\mathrm{on}}$ is changed by width in (c) TFET; (d) MOSFET.

Fig. 3 shows a standardization of current changing on width when the $\textit{V}$$_{\mathrm{GS}}$ varies from 2.0 V to 0.1 V and 1.0 V of $\textit{V}$$_{\mathrm{DS}}$. The current standardization of MOSFET shows that when $\textit{V}$$_{\mathrm{DS}}$ increases, the current standardization is little change. Although the current of the MOSFET is also divided, unlike TFET, it is not divided into specific levels, but rather randomly. The concept of standardization was introduced because it is difficult to quantitatively distinguish the current pattern from the current characteristics. The standardization was applied by

Fig. 3. (a) The standardization of current on width when $\textit{V}$$_{\mathrm{GS}}$ is 2.0 V by $\textit{V}$$_{\mathrm{DS}}$ = 0.1 V; (b) $\textit{V}$$_{\mathrm{DS}}$= 1.0 V.
$ z=~ \frac{X-~ \mu }{\sigma } $

$\textit{z}$ is a random variable, $\textit{X}$ is the observed value, ${\mu}$ is the population mean, and ${\sigma}$ is the standard deviation. By applying standardization for TFET and MOSFET, we can compare the differences in current variations between MOSFET and TFET and it shows following three factors. First, at high $\textit{V}$$_{\mathrm{GS}}$, the current is clearly quantized in TFET. At high $\textit{V}$$_{\mathrm{GS}}$, unlike low $\textit{V}$$_{\mathrm{GS}}$, tunneling is not affected by the depletion region, so it can be confirmed that the current is quantized in detail when expressed in standardization [35]. Second, we can also see that the change in $\textit{V}$$_{\mathrm{DS}}$ does not affect at all in MOSFET, but the change in the standardization value decreases as $\textit{V}$$_{\mathrm{DS}}$ increases in TFET. When $\textit{V}$$_{\mathrm{DS}}$ is 0.1 V, the standardization slope of change is 1.16 unit/nm and - 0.64 unit/nm, indication that the standardization of $\textit{V}$$_{\mathrm{DS}}$ is larger than the slope of change 0.98 unit/nm and - 0.43 unit/nm when the $\textit{V}$$_{\mathrm{DS}}$ is 1.0 V. Comparing the absolute value of the slope, the slope decreases as $\textit{V}$$_{\mathrm{DS}}$ value increases. Therefore, the current of TFET can be quantized by several levels. Third, TFET tends to increase the standardization value by width, but MOSFET is constant. It is confirmed that the increase in width is a major factor affecting ${\Delta}$$\textit{I}$$_{\mathrm{on}}$ in TFET.

We analyzed the reason of current quantization at high $\textit{V}$$_{\mathrm{GS}}$ in TFET. When voltage is applied to the gate on MOSFET, the channel is formed under the entire area under gate oxide which is affected by WFV. Thus, even if a local WFV occurs, it has an average effect on the entire channel. Since the WFV changes randomly, the average effect of the entire channel also changes randomly, which produces the result that the current of the MOSFET is randomly divided [39]. On the other hand, TFET shows that the level is divided almost constantly. When $\textit{V}$$_{\mathrm{DS}}$ is bigger, the levels are more clearly divided. Furthermore, the difference in the current standardization can be seen to widen when $\textit{V}$$_{\mathrm{DS}}$ is larger than when it is smaller. Unlike MOSFET where the area under the entire gate oxide is affected, the TFET is only affected by the WFV near the source region junction.

Fig. 4(a) shows the BTBT diagram in $\textit{V}$$_{\mathrm{GS}}$ in 0 V and 2.0 V near source junction by WFV (4.4 eV and 4.6 eV) by 10 nm width. The band with WF value of 4.6 eV at 0~V-$\textit{V}$$_{\mathrm{GS}}$ does not produce a smooth curve because the band is also affected by WF value in the channel region. When $\textit{V}$$_{\mathrm{GS}}$ increases to 2.0 V, the energy band become smoother because the channel potential cannot be fluctuated by WF variation due to the induced electrons from drain [40]. When the WF values near source region decrease, it is found that the band near the source junction decreases further, what means it is steeper and the tunneling width is reduced. This phenomenon makes it easier for electrons to move with a reduced width and results in an increase in current. Specifically, to confirm this phenomenon, the electronic BTBT generation rate of cutting 2 nm points under gate oxide at 2 V of $\textit{V}$$_{\mathrm{GS}}$ can be seen in inset of Fig. 4(b). It is found that the BTBT generation rate is larger when the WF value near source is 4.4 eV compared with 4.6 eV (Fig. 4(b)). Therefore, this incensement of BTBT makes higher current value than WF value of 4.6 eV. These currents are categorized into quantized level.

Fig. 4. (a) The Band structure in 3-D planar TFET by WF; (b) The graph and structure of BTBT generation rate due to change in WF values closest to the junction of the source at 1.0 V of $\textit{V}$$_{\mathrm{GS}}$ in 3-D planar TFET.

Then, we analyzed the reason of dependency between current quantization and $\textit{V}$$_{\mathrm{DS}}$ in TFET. Fig. 5(a) shows the energy band in $\textit{V}$$_{\mathrm{DS}}$ by 0.1 V and 1.0 V. It is different from the previous band graph because it was confirmed that only $\textit{V}$$_{\mathrm{DS}}$ was given. The larger $\textit{V}$$_{\mathrm{DS}}$ in the energy band, the lower the band and getting steep in the drain part. Fig. 5(b) shows an extension of the conduction band in the drain side when $\textit{V}$$_{\mathrm{DS}}$is 0.1 V, 1.0 V. When $\textit{V}$$_{\mathrm{DS}}$ is applied, the inversion electrons from the drain side are induced [41]. At this point, it can be confirmed that the energy differences exist while the inversion electrons move at the same distance. The inversion electrons accumulate at the point of the tunneling band. Then, the electrons make channel potential pinning which migrates WFV on tunneling region. Increasing $\textit{V}$$_{\mathrm{DS}}$, the energy band on the drain side goes down further and prevents inversion electrons. As a result, more electrons are tunneling and a lot of current flows.

Fig. 5. (a) The energy band according to differences by $\textit{V}$$_{\mathrm{DS}}$ variation in 3-D planar TFET; (b) The energy band and inversion electrons on the drain side according to the difference in $\textit{V}$$_{\mathrm{DS}}$.

Finally, we analyzed the dependency between current quantization and TFET width. Considering the probability of WFVs, these quantized current levels are easily predictable. Fig. 6 shows the bird’s eye view of TiN gate for randomly WF value 4.4 eV and 4.6 eV by width. Representatively, 10 nm (Fig. 6(a)), 20 nm (Fig. 6(b)), and 30 nm (Fig. 6(c)) widths were compared among widths of 10 nm \textasciitilde{} 50 nm. As the width increases, the number of cases of WF values of grains of 10 nm ${\times}$ 10 nm per square meter can be used in the formula for a number of combinations with repetition (3).

$ N~ =~ nHr $

The $\textit{N}$ is the number of the combinations with repetition. The $\textit{H}$ is symbol of the combination with repetition, $\textit{n}$ is a duplicate count and $\textit{r}$ is the number of cases where $\textit{r}$ is selected. Therefore, when applied to the equation, the number of levels divided can be determined. As a result, it is divided into 2 levels at 10 nm, 3 levels a 20 nm, 4 levels at 30 nm. Furthermore, at 40 nm and 50 nm, it is divided into 5 levels and 6 levels, respectively. Fig. 6(d) shows a probability graph with width between 10 and 30 nm using $\textit{N}$ values. The current of the gate with a width of 10 nm is divided into two levels, with a probability of 4.4 eV and 4.6 eV equal to 0.4, 0.6. In the case of the gate width of 20 nm, the probability is divided when the total is 4.4 eV, when the total is 4.6 eV, and when 4.4 eV and 4.6 eV are emitted simultaneously. The probability that the total is 4.4 eV is 0.4 ${\times}$ 0.4 = 0.16, the probability that the total is 4.6 eV is 0.6 ${\times}$ 0.6 = 0.36, and the probability of the simultaneous occurrence is 2 ${\times}$ 0.4 ${\times}$ 0.6 = 0.48. Similarly, the probability and the number of levels remaining at 30 nm, 40 nm, and 50 nm width can be obtained when approached in the probability aspect. The reason why the number of levels could not be clearly determined in the previous graph is because the task identified simulation with 30 samples. As mentioned earlier, because the WF value is designated random, so 30 samples are bound to show a limit. However, this trend can be predicted.

Fig. 6. The bird’s eye view of gate for randomly WF 4.4 eV and 4.6 eV in width by (a) 10 nm; (b) 20 nm; (c) 30 nm; (d) The probability that WF value is determined.


In the TFET, it was confirmed that the current was quantized, and the quantized level and appearance could be predicted. In the probability aspect, the effect of WFV affecting TFET is shown through the current. The current of TFET is quantized to a specific level by WFV near the junction between source and gate at high $\textit{V}$$_{\mathrm{GS}}$. The degree of specific levels can be divided using the combination with repetition. We can see that there are four factors in controlling the quantized current. First, WFV contributes greatly to level control. When the WF value is 4.4 eV, the ${\Delta}$$\textit{I}$$_{\mathrm{on}}$ is larger than when it is 4.6 eV. Second, the high impact of $\textit{V}$$_{\mathrm{GS}}$ controls the levels. $\textit{V}$$_{\mathrm{GS}}$ exceeds a certain voltage, the current quantized. When low $\textit{V}$$_{\mathrm{GS}}$ is applied, the tunneling area is wide due to the influence of the depletion area, but when high $\textit{V}$$_{\mathrm{GS}}$ is applied, the quantization is clearly visible. Third, the change in $\textit{V}$$_{\mathrm{DS}}$ affects control of levels. As $\textit{V}$$_{\mathrm{DS}}$ increases, less channel inversion occurs and tunneling becomes migrated. Fourth, width affects control of the level. As width increases, WF value near the gate and source junction increases, so the number of current quantized by the combination with repetition formula increases. Therefore, the current of TFET is quantized according to the values of WF, $\textit{V}$$_{\mathrm{GS}}$ $\textit{V}$$_{\mathrm{DS}}$ and width.


This research was supported in part by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (NRF-2020R1G1A1101263) and in part by the NRF of Korea grant funded by the MSIT (NRF-2020M3F3A2A01081672) (Intelligent Semiconductor Technology Development Program). The EDA tool was supported by the IC Design Education Center (IDEC), Korea.


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Kim G., Kim J. H., Kim J., Kim S., 2020., Analysis of Work-Function Variation Effects in a Tunnel Field-Effect Transistor Depending on the Device Structure, Applied Sciences, Vol. 10, No. 15, pp. 5378DOI
Kim H. W., Kim J. H., 2020, Study on the Influence of Drain Voltage on Work Function Variation Characteristics in Tunnel Field-effect Transistor, J. Semicond. Technol. Sci., Vol. 20, No. 6, pp. 558-564DOI
Lee W., Choi W., 2011, Influence of inversion layer on tunneling field-effect transistors, IEEE Electron Device Lett., Vol. 32, No. 9, pp. 1191-1193DOI
Kang Lee

Kang Lee was born in Gyeongju, South Korea, in 1996. He receives B.S. degree from Pukyong National University (PKNU), Busan, South Korea, in 2022. His major is the Electrical Engineering. His interests include Tunnel FET, GAA FET.

Sangwan Kim

Sangwan Kim was born in Daegu, South Korea, in 1983. He received the B.S., M.S., and the Ph.D. degrees in Electrical Engineering from Seoul National University, Seoul, Republic of Korea, in 2006, 2008, and 2014, respectively. He had been a post-doctoral scholar at the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, USA, from 2014 to 2017. He had been with the Department of Electrical and Computer Engineering, Ajou University, Suwon, Republic of Korea, as Assistant/Associate Professor from 2017 to 2022. Since 2022, he has been a Faculty Member with Sogang University, Seoul, Republic of Korea, where he is currently an Associate Professor with the Department of Electronic Engineering.

Garam Kim

Garam Kim received the B. S. and the Ph.D. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 2008 and 2014, respectively. He worked as a senior engineer at Samsung Electronics from 2014 to 2019. In 2019, he joined the Department of Electronic Engineering at Myongji University, Yongin, where he is currently an assistant professor.

Jang Hyun Kim

Jang Hyun Kim received the B.S. degree from KAIST, Daejeon, Korea, in 2009 and the M.S. and Ph.D degrees from Seoul National University, Seoul, in 2011 and 2016, respectively, all in electrical and computer engineering. From 2016 to 2020, he worked at SK Hynix as senior research engineer. In 2020, he moved to Pukyong National University, Busan, Korea, as an assistant professor of the school of Electrical Engineering.