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1. (Department of Electric Engineering, Pukyong National University, Busan 48513, Korea)
2. (Department of Electronic Engineering, Sogang University, Seoul 04107, Korea)
3. (Department of Electronic Engineering, Myongji University, Yongin 17058, Korea)

Tunnel field-effect transistor, on-current variation, work function variation, quantized current

## I. INTRODUCTION

Recently, as the use of mobile devices increases, power dissipation in integrated circuits (ICs) has been concerned dramatically. To solve this, the amount of power consumption and size of the complementary metal-oxide semiconductor (CMOS) device have trends for reduction [1-7]. In the trends of development, the key point of this reduction is lowering supply voltage while achieving a high on/off current ratio. However, due to the physical limitations of metal-oxide-semiconductor field-effect transistor (MOSFET), the supply power cannot be reduced because the theorical subthreshold swing (SS) cannot be lower than 60 mV/dec. To overcome this problem, many researching groups have researched a tunneling field-effect transistor (TFET) for its good electrical performance in low power circumstance and CMOS compatibility [8-11]. Moreover, the electrical performance of TFET can be improved dramatically by applying the high-${\kappa}$/metal gate (HKMG) technology for small equivalent oxide thickness (EOT), low gate leakage current and low gate resistance [12-21]. Therefore, the TFET with HKMG has notable electrical performance for low voltage operation due to its small SS, low-level off-state current ($\textit{I}$$_{\mathrm{off}}). Thus, it is expected that the TFET is applicable to the real industry as a substitutional or complementary device for conventional CMOS. Despite these advantages, the metal gate occurs work function (WF) variation (WFV) issue due to the non-uniformity of various metal gate grains by size and by orientation according to the fabrication processes [22-31] Therefore, adopting the TFET to the real CMOS circuits, the electrical performance variations according to the WFV must be scrutinized. In previous research, most of studies have been noticed on variation ranges of the MOSFET and TFET [17, 32, 33]. However, WFV effect on the current variation characteristics about the MOSFET and TFET hasn’t been studied rigorously [34]. In this research, an investigation has been performed to study the relation between on-current (\textit{I}$$_{\mathrm{on}}$) and WFV in the TFET with help of technology computer-aided design (TCAD) simulation. Comparing TFET and MOSFET, the TFET can be identified for multiple quantized $\textit{I}$$_{\mathrm{on}}. The contents of this paper are as follows. In Section II, the structure and simulation models of studied the TFET and MOSFET are explained. The WFV induced by the grain of the metal gate is set reflecting the actual gate physical properties. In Section III, the quantitative analysis is performed by confirming location of metal grains and BTBT rate to monitor the variation of \textit{I}$$_{\mathrm{on}}$ (${\Delta}$$\textit{I}$$_{\mathrm{on}}$), with various bias.

## II. DEVICE STRUCTURE AND SIMULATION METHOD

The three-dimensional (3-D) structure of planar TFET and MOSFET is shown in Fig. 1(a). This technology computer-aided design (TCAD) simulation is performed by Synopsys Sentaurus. All parts of source, drain, and channel consist of silicon. To focus on the WFV in TFET and MOSFET rigorously, the physical dimension is set for suppressing short channel effect. Commonly in TFET and MOSFET, the channel length ($\textit{L}$$_{\mathrm{ch}}) of 50 nm and gate oxide thickness (\textit{T}$$_{\mathrm{OX}}$) of 1 nm are set. The channel width ($\textit{W}$) varies in size from 10 to 50 nm. The body doping concentration ($\textit{N}$$_{\mathrm{B}}) of 10^{17} cm^{-3} (boron, p-type). The source doping concentration (\textit{N}$$_{\mathrm{S}}$) and drain doping concentration ($\textit{N}$$_{\mathrm{D}}) of 10^{20} cm^{-3} are consist of same doping types of arsenic in the MOSFET. Contrastively, boron concentration in the TFET source \textit{N}$$_{\mathrm{S}}$ and arsenic concentration in the drain $\textit{N}$$_{\mathrm{D}} are 10^{20} cm^{-3}. The gate area is divided 10 nm {\times} 10 nm units with random work function (4.4 eV, 4.6 eV). In fabrication process, the sputtered TiN at gate has 10 nm grain size and crystallized primarily in <200> (60 %) and in <111> (40 %) corresponding to WF value of 4.6 eV and 4.4 eV [35-37]. All the parameters for device structure are summarized in Table 1. ##### Table 1. Margin specifications  Parameters Value ^{\mathrm{a}} Device MOSFET TFET Source doping conc. (\textit{N}_{\mathrm{S}}) 10^{20} cm^{-3}(arsenic) 10^{20} cm^{-3}(boron) Drain doping conc. (\textit{N}_{\mathrm{D}}) 10^{20} cm^{-3} Body doping conc. (\textit{N}_{\mathrm{B}}) 10^{17} cm^{-3} Gate Work-function 4.6 eV / 4.4 eV Channel length (\textit{L}_{\mathrm{ch}}) 50 nm Channel width (\textit{W}) 10 nm ~ 50 nm Metal grain size 10 nm Gate oxide thickness (\textit{T}_{\mathrm{OX}}) 1 nm ##### Fig. 1. (a) 3-D structure of planar the TFET and MOSFET device; (b) Top view of the TFET and MOSFET. The WFV is reflected in random from 4.4 eV to 4.6 eV; (c) Calibration of the simulated transfer characteristics at \textit{V}$$_{\mathrm{DS}}$ of 1 V. The BTBT models are calibrated by experimental data of the fabricated planar Si TFET.

The electrical characteristics of the MOSFET and TFET are simulated with Shockley-Read-Hall (SRH) generation-recombination model and dynamic nonlocal band to band tunneling (BTBT) model. The dynamic nonlocal BTBT model is necessary to examine BTBT in TFET. Because it can dynamically calculate and determine all tunneling paths grounded on the energy band profile. Concretely, the BTBT model is calibrated to the experimental data for planar Si TFET. The BTBT generation rate per unit volume ($\textit{G}$) in the uniform electric field limit is calculated by

##### (1)
$G=~ A\left(\frac{F}{F_{0}}\right)^{P}\exp \left(-\frac{B}{F}\right)$

## ACKNOWLEDGMENTS

This research was supported in part by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (NRF-2020R1G1A1101263) and in part by the NRF of Korea grant funded by the MSIT (NRF-2020M3F3A2A01081672) (Intelligent Semiconductor Technology Development Program). The EDA tool was supported by the IC Design Education Center (IDEC), Korea.

## References

1
Choi W. Y., Park B. G., Lee J. D., Liu T. J. K., 2007, Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec, IEEE Electron Device Lett., Vol. 28, No. 8, pp. 743-745
2
Bernstein K., Cavin R. K., Porod W., Seabaugh A., Welser J., 2010, Device and architecture outlook for beyond CMOS switches, Proc. IEEE, Vol. 98, No. 12, pp. 2169-2184
3
Kim J. H., Kim S., Park B. G., 2019, Double-Gate TFET With Vertical Channel Sandwiched by Lightly Doped Si, IEEE Trans. Electron Devices, Vol. 66, No. 4, pp. 1656-1661
4
Seabaugh A. C., Zhang Q., 2010, Low-voltage tunnel transistors for beyond CMOS logic, Proc. IEEE, Vol. 98, No. 12, pp. 2095-2110
5
Wang P. Y., Tsui B. Y., 2016, Band engineering to improve average subthreshold swing by suppressing low electric field band-to-band tunneling with epitaxial tunnel layer tunnel FET structure, IEEE Trans. Nanotechnol., Vol. 15, No. 1, pp. 74-79
6
Kim S. W., Choi W. Y., Kim H., Sun M. C., Kim H. W., Park B. G., 2012, Investigation on hump effects of L-shaped tunneling filed-effect transistors, 2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012, pp. 1-2
7
Mishra A., Pattanaik M., Sharma V., 2013, Double gate vertical tunnel FET for hybrid CMOS-TFET based low standby power logic circuits, 2013 Annual International Conference on Emerging Research Areas, AICERA 2013 and 2013 International Conference on Microelectronics, Communications and Renewable Energy, ICMiCR 2013 - Proceedings, pp. 1-4
8
Long P., Wilson E., Huang J. Z., Klimeck G., Rodwell M. J. W., Povolotskyi M., 2016, Design and Simulation of GaSb/InAs 2D Transmission-Enhanced Tunneling FETs, IEEE Electron Device Lett., Vol. 37, No. 1, pp. 107-110
9
Knoch J., Nanowire Tunneling Field-Effect Transistors, in Semiconductors and Semimetals, Vol. 94, S. A. Dayeh, A. Fontcuberta i Morral, and C. B. T.-S. and S. Jagadish, eds. Elsevier, 2016, pp. 273-295
10
Zhang Q., Zhao W., Seabaugh A., 2006, Low-subthreshold-swing tunnel transistors, IEEE Electron Device Lett., Vol. 27, No. 4, pp. 297-300
11
Gandhi R., Chen Z., Singh N., Banerjee K., Lee S., 2011, Vertical Si-Nanowire n-type tunneling FETs with low subthreshold swing ≤50 mV/decade) at room temperature, IEEE Electron Device Lett., Vol. 32, No. 4, pp. 437-439
12
Gusev E. P., Buchanan D. A., Cartier E., Kumar A., DiMaria D., Guha S., Callegari A., Zafar S., Jamison P. C., Neumayer D. A., Copel M., Gribelyuk M. A., Okorn-Schmidt H., D’Emic C., Kozlowski P., Chan K., Bojarczuk N., Ragnarsson L. Å., Ronsheim P., Rim K., Fleming R. J., Mocuta A., Ajmera A., 2001, Ultrathin high-K gate stacks for advanced CMOS devices, Technical Digest - International Electron Devices Meeting, pp. 451-454
13
Boucart K., Ionescu A. M., 2007, Double-gate tunnel FET with high-κ gate dielectric, IEEE Trans. Electron Devices, Vol. 54, No. 7, pp. 1725-1733
14
Datta S., Dewey G., Doczy M., Doyle B. S., Jin B., Kavalieros J., Kotlyar R., Metz M., Zelick N., Chau R., 2003, High Mobility Si/SiGe Strained Channel MOS Transistors with HfO 2/TiN Gate Stack, Technical Digest - International Electron Devices Meeting, pp. 653-656
15
Gusev E. P., Narayanan V., Frank M. M., 2006, Advanced high-κ dielectric stacks with polySi and metal gates: Recent progress and current challenges, IBM J. Res. Dev., Vol. 50, No. 4-5, pp. 387-410
16
Saha R., Bhowmick B., Baishya S., 2018, Effect of gate dielectric on electrical parameters due to metal gate WFV in n-channel Si step FinFET, Micro Nano Lett., Vol. 13, No. 7, pp. 1007-1010
17
Saha R., Bhowmick B., Baishya S., 2019, Impact of WFV on electrical parameters due to high-k/metal gate in SiGe channel tunnel FET, Microelectron. Eng., Vol. 214, pp. 1-4
18
Lee B. H., Choi R., Kang L., Gopalan S., Nieh R., Onishi K., Jeon Y., Qi W. J., Kang C., Lee J. C., 2000, Characteristics of TaN gate MOSFET with ultrathin hafnium oxide (8Å-12Å), Technical Digest - International Electron Devices Meeting, pp. 39-41
19
Hou Y. T., Li M. F., Low T., Kwong D. L., 2004, Metal gate work function engineering on gate leakage of MOSFETs, IEEE Trans. Electron Devices, Vol. 51, No. 11, pp. 1783-1789
20
Wang S. J., Chen I. C., Tigelaar H. L., 1991, Effects of Poly Depletion on the Estimate of Thin Dielectric Lifetime, IEEE Electron Device Lett., Vol. 12, No. 11, pp. 617-619
21
Anghel C., Chilagani P., Amara A., Vladimirescu A., 2010, Tunnel field effect transistor with increased on current, low-k spacer and high-k dielectric, Appl. Phys. Lett., Vol. 96, No. 12, pp. 2008-2011
22
Reid D., Millar C., Roy S., Asenov A., 2010, Understanding LER-induced MOSFET VT variability-Part I: Three-dimensional simulation of large statistical samples, IEEE Trans. Electron Devices, Vol. 57, No. 11, pp. 2801-2807
23
Croon J. A., Storms G., Winkelmeier S., Pollentier I., Ercken M., Decoutere S., Sansen W., Maes H. E., 2002, Line edge roughness: Characterization, modeling and impact on device behavior, Technical Digest - International Electron Devices Meeting, pp. 307-310
24
Li Y., Hwang C. H., Li T. Y., 2009, Random-dopant-induced variability in nano-CMOS devices and digital circuits, IEEE Trans. Electron Devices, Vol. 56, No. 8, pp. 1588-1597
25
Kovac U., Alexander C., Roy G., Riddet C., Cheng B., Asenov A., 2010, Hierarchical simulation of statistical variability: From 3-D MC with ab initio ionized impurity scattering to statistical compact models, IEEE Trans. Electron Devices, Vol. 57, No. 10, pp. 2418-2426
26
Hobbs C. C., Fonseca L. R. C., Knizhnik A., Dhandapani V., Samavedam S. B., Taylor W. J., Grant J. M., Dip L. R. G., Triyoso D. H., Hegde R. I., Gilmer D. C., Garcia R., Roan D., Lovejoy M. L., Rai R. S., Hebert E. A., Tseng H. H., Anderson S. G. H., White B. E., Tobin P. J., 2004, Fermi-level pinning at the polysilicon/metal oxide interface - Part I, IEEE Trans. Electron Devices, Vol. 51, No. 6, pp. 971-977
27
Choi K. M., Choi W. Y., 2013, Work-function variation effects of tunneling field-effect transistors (TFETs), IEEE Electron Device Lett., Vol. 34, No. 8, pp. 942-944
28
Choi K. M., Kim S. K., Choi W. Y., May 2016, Influence of number fluctuation and position variation of channel dopants and gate metal grains on tunneling field-effect transistors (TFETs), J. Nanosci. Nanotechnol., Vol. 16, No. 5, pp. 5255-5258
29
Choi W. Y., 2015, Design guidelines of tunnelling field-effect transistors for the suppression of workfunction variation, Electron. Lett., Vol. 51, No. 22, pp. 1819-1821
30
Dadgour H. F., Endo K., De V. K., Banerjee K., 2010, Grain-orientation induced work function variation in nanoscale metal-gate transistors - Part I: Modeling, analysis, experimental validation, IEEE Trans. Electron Devices, Vol. 57, No. 10, pp. 2504-2514
31
Dadgour H. F., Endo K., De V. K., Banerjee K., 2010, Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part II: Implications for Process, Device, Circuit Design, IEEE Trans. Electron Devices, Vol. 57, No. 10, pp. 2515-2525
32
Choi K. M., Choi W. Y., 2013, Work-Function Variation Effects of Tunneling Field-Effect Transistors (TFETs), IEEE Electron Device Lett., Vol. 34, No. 8, pp. 942-944
33
Avci U. E., Morris D. H., Hasan S., Kotlyar R., Kim R., Rios R., Nikonov D. E., Young I. A., 2013, Energy efficiency comparison of nanowire heterojunction TFET and Si MOSFET at Lg=13nm, including P-TFET and variation considerations, Technical Digest - International Electron Devices Meeting, IEDM, pp. 33.4.1-33.4.4
34
Lee K., Jeon M. G., Park S. H., Yoon T. Y., Noh J. S., Kim J. H., Jul. 2021, Analysis of Quantized Current Effect with Work Function Variation in Tunnel-Field Effect Transistor, Nano Korea, pp. 753
35
Kim J. H., Kim T. C., Kim G., Kim H. W., Kim S., 2020, Methodology to Investigate Impact of Grain Orientation on Threshold Voltage and Current Variability in Tunneling Field-Effect Transistors, IEEE J. Electron Devices Soc., Vol. 8, No. October, pp. 1345-1349
36
Frye A., Galyon G. T., Palmer L., 2007, Crystallographic texture and whiskers in electrodeposited tin films, IEEE Trans. Electron. Packag. Manuf., Vol. 30, No. 1, pp. 2-10
37
Dadgour H., De V., Banerjee K., 2008, Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design, IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, pp. 270-277
38
Kwon D. W., Kim J. H., Park E., Lee J., Kim S., Park B. G., 2017, Switching characteristic analysis of tunnel field-Effect transistor (TFET) inverters, J. Nanosci. Nanotechnol., Vol. 17, No. 10, pp. 7134-7139
39
Kim G., Kim J. H., Kim J., Kim S., 2020., Analysis of Work-Function Variation Effects in a Tunnel Field-Effect Transistor Depending on the Device Structure, Applied Sciences, Vol. 10, No. 15, pp. 5378
40
Kim H. W., Kim J. H., 2020, Study on the Influence of Drain Voltage on Work Function Variation Characteristics in Tunnel Field-effect Transistor, J. Semicond. Technol. Sci., Vol. 20, No. 6, pp. 558-564
41
Lee W., Choi W., 2011, Influence of inversion layer on tunneling field-effect transistors, IEEE Electron Device Lett., Vol. 32, No. 9, pp. 1191-1193
##### Kang Lee

Kang Lee was born in Gyeongju, South Korea, in 1996. He receives B.S. degree from Pukyong National University (PKNU), Busan, South Korea, in 2022. His major is the Electrical Engineering. His interests include Tunnel FET, GAA FET.

##### Sangwan Kim

Sangwan Kim was born in Daegu, South Korea, in 1983. He received the B.S., M.S., and the Ph.D. degrees in Electrical Engineering from Seoul National University, Seoul, Republic of Korea, in 2006, 2008, and 2014, respectively. He had been a post-doctoral scholar at the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, USA, from 2014 to 2017. He had been with the Department of Electrical and Computer Engineering, Ajou University, Suwon, Republic of Korea, as Assistant/Associate Professor from 2017 to 2022. Since 2022, he has been a Faculty Member with Sogang University, Seoul, Republic of Korea, where he is currently an Associate Professor with the Department of Electronic Engineering.

##### Garam Kim

Garam Kim received the B. S. and the Ph.D. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 2008 and 2014, respectively. He worked as a senior engineer at Samsung Electronics from 2014 to 2019. In 2019, he joined the Department of Electronic Engineering at Myongji University, Yongin, where he is currently an assistant professor.

##### Jang Hyun Kim

Jang Hyun Kim received the B.S. degree from KAIST, Daejeon, Korea, in 2009 and the M.S. and Ph.D degrees from Seoul National University, Seoul, in 2011 and 2016, respectively, all in electrical and computer engineering. From 2016 to 2020, he worked at SK Hynix as senior research engineer. In 2020, he moved to Pukyong National University, Busan, Korea, as an assistant professor of the school of Electrical Engineering.