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1. (Department of Electronic Engineering, Hanyang University, Ansan Gyeonggi-do 15588, Korea)

MOSFET, shallow and deep level traps, Si/SiO$_{2}$ interface, low time, TCAD simulations

## I. INTRODUCTION

The metal oxide field-effect transistors (MOSFETs) being the basic components of electronic devices are widely used in industry. The reliability of MOSFET devices is a big concern in today's research. But the aggressive scaling of MOSFETs with the demand for pronounced features e.g. lower operating voltage, higher density, and high speed leads to the complexity of the fabrication process. Because of this complexity, many short channel effects arise that result in the degradation of the device’s performance.

The leading cause of device scaling is the traps prevailing on the Si/SiO$_{2}$ interface or Si substrate that are a big source of variability. In a circuit, the random distribution of traps between the adjacent transistors leads to variation in the number and position of each trap [1,2]. The variable existence of interface and near interface traps causes significant parametric fluctuations in the device [3,4]. An additional trap-assisted leakage mechanism is also introduced because of these generated interface traps [5]. While working with the emerging MOSFET technologies, a better interpretation of the effects of interface traps is important.

When the semiconductor devices are exposed to ionizing radiations, the generated traps have a wide distribution of energy over the bandgap [6]. The generated traps having energy in the lower and upper part bandgap are donor or acceptor traps, respectively [7,8]. To study the individual traps behavior in this study, only acceptor-type traps are analyzed, since of having a distinct effect on device characteristics [9,10].

For the reliable operation of the MOSFET device, a mathematical model is reported previously for the estimation of degradation [11]. Various techniques for the measurement of hot carrier degradation in MOSFET devices are also available [12]. Another well-known technique is the charge pumping, which can be used to determine the Si/SiO$_{2}$ interface states density and capture cross-sections directly in MOSFETs [13,14].

Nowadays, in highly scaled and complex MOSFET devices, physically-based simulations play a significant role. When the semiconductor devices are simulated, it provides more insight into the physics of the device operation, which helps to shorten the development cycle for new technologies.

In this study, comprehensive two-dimensional TCAD simulations are performed to observe the electron charge pumping cycle (trapping & de-trapping of the electron) in an individual-specified trap (at a distinct energy level and location) on the interface and near the interface in the Si substrate. A comprehensive view of individual trap behavior at various locations and energy levels that is important to understand the variability in device performance is presented. Our focus is on the emission of electron charge in the low time, contributing to substrate current to estimate the degradation in device performance from an individual-specified trap. Based on this contribution, the trap participating effectively in device degradation is also identified. All electron charge emission in the low time is assumed to contribute to substrate current. A special case is also discussed, that is based on the accumulation of emitted electron charge in the low time. One femtocoulomb accumulation of charge in the low time that contributes to substrate current is considered as the threshold value of charge (after which device degradation starts). The number of cycles and time in ns to acquire the threshold value of electron charge is calculated. These calculated number of cycles are the threshold number of cycles after which failure starts in a device. The threshold number of cycles obtained in the case of each distinct trap is multiplied by cycle time to get a threshold time after which devices’ performance starts to degrade.

The remainder of this paper is organized as follows: Section II presents the simulation methodology with the used device model, trap specifications, and flow of simulation. Based on this model section III illustrates the electron charge pumping cycle to understand the dynamics for each trap. It reveals the contribution of each trap in device degradation via the distinct value of the low-time emission contributing to substrate current. The correlation of each trap’s failure contribution with the changing trap energy level and location is also divulged. Section IV presents a special case, which assumes the accumulation of electron charge in the low time. Based on the threshold value of charge accumulation (one femtocoulomb) in the low time, the calculated threshold number of cycles and time is presented in it. Finally, the presented work is concluded in section V.

## II. SIMULATION APPROACH AND DEVICE MODEL

In this section flow of simulation is discussed with the used device model and trap parameters. Sentaurus TCAD was utilized to simulate an individual-specified (at a single location with a specific energy level) trap placed at the Si/SiO$_{2}$ interface or near the interface at the Si substrate of an n-channel MOSFET device. Details of the used device model, trap specifications, and flow of simulation will be discussed in sub-sections 1, 2, and 3, respectively.

### 1. Device Model with Specified Regions

The schematic of n-channel MOSFET with a zoomed portion of the interface and near interface area has been presented in Fig. 1. The silicon substrate of n-MOSFET was doped with constant p-type doping of boron (1e17 cm$^{-3}$). A Gaussian distribution profile was used with an arsenic doping concentration of 5e19 cm$^{-3}$ for source and drain. The thickness of oxide and physical gate length was 4 nm and 0.4 ${\mu}$m, respectively.

##### Fig. 1. Schematic representation of n-channel MOSFET with all defined regions, zoomed part (green rectangle) at the middle is representing the trap locations at the interface or near interface area in Si substrate.

For the meshing in the device, a recommended fine mesh was implemented on active regions for the accuracy of results. A coarse mesh was implemented elsewhere and at the interface, meshing was implemented in such a way that it was divided into small equidistant regions from source to drain. The purpose of making small equidistant regions was to put the trap at accurate locations in selected regions. Depending on mesh size, simulation was accomplished with a different resolution at the interface and other regions. The effective length of the interface was 0.14 ${\mu}$m, and the distance between two successive nodes on the interface was 0.0039 ${\mu}$m which was sufficient to accomplish our purpose. The details of trap specifications have been presented in sub-section 2.

### 2. Trap Specifications

Based on the reported results, acceptor-type traps have prominent effects on device characteristics [9,10]. These traps are neutral before the capture of a hole or electron and hold a negative charge when occupied. Another category of traps having a positive charge if empty and neutral when occupied are the donor-type traps. Only acceptor-type traps are considered in this study because of their effectiveness.

An individual trap at a specific energy level and location is simulated in this work.

For the energy level of the trap, the acceptor-like traps are reported to exist in the upper half of the bandgap [8]. By using the mid-band as a reference energy level, trap energy distributions 0.35 to 0.55 eV, which are typical for Si/SiO$_{2}$ interface and Si bulk [15,16] are used.

For the location of the trap, at a total of 0.14 ${\mu}$m length of the interface, five equidistant regions were selected to fill with traps. One trap was placed at an accurate middle region on the interface named X3 [see Fig. 1]. By keeping this trap (X3) as a reference, two regions were selected towards the source and drain edge with a sweep of 0.03 ${\mu}$m to put traps X2 and X4, respectively. Two more regions were selected towards the source and drain edge with a sweep of 0.06 ${\mu}$m, by keeping trap X3 as a reference to put traps X1 and X5, respectively. With this sequence, five regions were chosen to fill with an individual trap at a specific energy level on the interface. The traps X1 to X5 on the interface were collectively named A''.

For the trap locations on the Si substrate, the same five regions were selected with a 0.005 ${\mu}$m (5 nm) and 0.01 ${\mu}$m sweep from the interface towards the Si substrate. The traps located at five regions at a 0.005 ${\mu}$m sweep from interface were named Y1, Y2, Y3, Y4, and Y5, from source to drain edge, respectively. The traps Y1 to Y5 in the Si substrate on a sweep of 0.005 ${\mu}$m from the interface were collectively named B''.

And the traps located at five regions at a 0.01${\mu}$m sweep from interface were named Z1, Z2, Z3, Z4, and Z5, from source to drain edge, respectively. These traps Z1 to Z5 in the Si substrate on a sweep of 0.01 ${\mu}$m from the interface were collectively named C''.

These all trap locations can be seen in the zoomed part of Fig. 1.

Capture and emission cross-section for both Si/SiO$_{2}$ interface and Si bulk traps have been reported in the range 10e-12 cm$^{-2}$ to 10e-18 cm$^{-2}$[9, 14, 17]. For this work, the capture and emission cross-sections are set to 10e-13 cm$^{-2}$.

### 3. Simulation Approach

The device model presented in Fig. 1, was simulated by putting an individual trap at various locations [see zoom area in the middle of Fig. 1], and energy levels (0.35-0.55). The 2D device simulations were performed by using the conventionally used square waveform with 0.1 ns rise/fall time and 4.9 ns high/low time duration having five switching points (Pt1, Pt2, Pt3, Pt4, and Pt5). The used square waveform has been presented in Fig. 2. The flow of the simulation has been presented in Fig. 3.

##### Fig. 3. Flow chart of simulations used in this study.

All the selected regions on the interface and Si substrate to fill with an individual trap add to fifteen. The simulation was performed by filling a single region with an individual trap and assigning one of the energy levels (0.35 to 0.55 eV with a difference of 0.05 eV). After simulating at a single trap location with five different energy levels, the trap was swept to an adjacent location. Using this sequence, simulation was performed at all selected trap regions.

During the execution of one cycle via simulating an individual trap, the electron charge pumping cycle (trapping & de-trapping of the electron) was recorded. Electron charge pumping cycle data recorded during one cycle was used to extract the probability of trapped electron charge emission in the low time. This emission of charge moves towards the substrate, giving rise to substrate current that degrades the performance of the device. This study was effective to analyze/distinguishing the trap's most effective location and energy level at the interface and near the interface area in the channel. The probability of failure time obtained from each trap was used to conclude the impact of each trap on device failure. A special case was also discussed in which the probability of trapped electron charge emission in low time was used to calculate the number of cycles to accumulate the threshold value of electron charge (set to 1 femtocoulomb for this study) after which the performance of the device degrades. These number of cycles for each case were multiplied by used cycle time to extract the threshold time for each trap.

## III. ELECTRON CHARGE PUMPING CYCLE

This section presents the electron charge pumping cycle of an individual eNeutral trap in an n-channel MOSFET device, operated using a square waveform [see Fig. 2] and assumed cycle time of 10 ns (0.1 ns rise/fall time and 4.9 ns high/low time duration). To observe the individual trap’s impact on device failure, the recorded trap charge pumping cycle is discussed in sub-section 1. The correlation of trap failure contribution with trap location and energy level is discussed in sub-section 2. At a constant energy level, the impact of different location traps on device failure is discussed in sub-section 3.

### 1. Trapping and de-Trapping from an Individual Trap

The trapping and de-trapping of electron charge from each trap at five different energy levels have been observed. To avoid the complexity of data, three trap locations (X3, Y3, and Z3) are selected to present the electron charge pumping cycle.

The probability of trapped electron charge is presented at all time points in a waveform [see Fig. 2] in Fig. 4(a), (b), and (c) for the traps X3, Y3, and Z3, respectively. The word time point is written as Pt'' in the remainder of the paper.

The same trend of electron charge trapping and de-trapping is observed at all trap locations. A trap captures an amount of charge in the rise time (Pt1 to Pt2), accumulates it during the high time (Pt2 to Pt3) then starts to emit partially in fall time (Pt3-Pt4) and partially in low time (Pt4-Pt5) depending on its energy (E$_{\mathrm{t}}$-E$_{\mathrm{i}}$ = 0.35-0.55). A partial amount of charge also remains trapped inside a trap even after a cycle is completed that also depends on trap energy. The amount of charge emitting during fall time (Pt3-Pt4) contributes to the current that may or may not contributes to device failure. But the amount of charge, emitting during the low time (Pt4-Pt5) can cause device malfunctions by contributing to substrate current that degrades the performance of the device.

##### Fig. 4. Probability of trapped electron charge at time points in a complete waveform, for traps: (a) X3; (b) Y3; (c) Z3 at all five energy levels.

To study the impact of each trap on device degradation, it is important to analyze its electron charge pumping cycle. During the trap capture process from Pt1 to Pt3, captured charge saturates quickly because of strong band bending. But The emission of trapped charge takes time depending on trap energy [18]. This emission from each trap describes its impact on device failure. To study the individual trap impact on device failure and calculate the failure time from each trap, it is desired to study the individual trap emission process (Pt3-Pt5). The duration of trap emission (Pt3-Pt5) is covered by two steps Pt3 to Pt4 (2V-0V) and Pt4 to Pt5 (0V-0V), that define the probabilities of trapped electron charge emission in the fall time and low time, respectively. Our focus is to extract the low-time emission contributing to substrate current, from each trap at a certain energy level. The area of electron charge emission, assumed to completely contribute to substrate current is highlighted by a rectangle in Fig. 4(a)-(c).

For a normal eNeutral trap behavior in MOS devices, a deep level (located near to mid-band) trap captures more charge during the ON-state and takes more time to emit during off-state. A shallow level (located near to conduction band) trap captures less charge during ON-state and takes less time to emit during off-state [18-20].

In the electron charge pumping cycle presented in Fig. 4(a)-(c), similar behavior is followed by deep to shallow level traps (0.35-0.55).

By changing the trap location from the interface (Fig. 4(a)) to the Si substrate (Fig. 4(b) and (c)), it behaves less effectively (trapping and de-trapping both reduces).

### 2. Contribution to Substrate Current from Each Individual-specified Trap

The difference in the probability of trapped electron charge at Pt4 to Pt5 [see Fig. 4(a)-(c)] gives the probability of trapped charge emission in the low time. The probability of trapped charge emission in low time, contributing to substrate current is critical to analyzing the impact of each trap location and energy level in device degradation. Because in the low time, when the device is OFF, no charge is desired for this duration. If any charge emits at this time, it leads to the device’s degradation by contributing to the substrate current that causes device malfunctions.

The probability of trapped charge emission in the low time versus trap energy has been presented in Fig. 5. Based on the results presented in Fig. 5, trapped charge emission in low time increases from shallow to deep level traps (0.55 ${\rightarrow}$ 0.35) and reduces from interface to the Si substrate (X3 ${\rightarrow}$ Y3 ${\rightarrow}$ Z3). It is observed that trap X3 at energy level 0.35 eV, having ~74% contribution to substrate current is degrading effectively to the device’s performance. This result is extracted by comparing traps X3, X4, and X5. It is also observed that traps at any location, having energy less than 0.50 eV, have ~0% contribution to substrate current and consequently don’t have any impact on device degradation. The reason behind having zero low-time emission is the short emission time of traps close to the conduction band (E$_{\mathrm{t}}$-E$_{\mathrm{i}}$ = 0.50-0.55). These traps seem to have an emission time within fall time (0.1 ns). The probability of emission from each trap at a certain energy in Fig. 5, illustrates the role of that trap in device degradation.

##### Fig. 5. presents the probability of trapped charge emission in low time versus trap energy levels for traps X3, Y3, and Z3 [seeFig. 1].

The emphasis of our work is to observe the contribution of each trap in substrate current to conclude the impact of that trap on device degradation. The probability of trapped charge emission in low time from all traps (each location trap at five different energy levels), giving their contribution to substrate current will be presented in sub-section 3.

### 3. Contribution of Individual Trap to Device Degradation

In this study, a total of fifteen trap locations were considered at five different energy levels for studying the impact of each location on malfunctions due to device degradation. To accomplish this need, the electron charge pumping cycle was recorded from each specific trap (at a single location and energy level). The probability of trapped charge emission in the low time was extracted from the recorded electron charge pumping cycle. The extracted probability of trapped charge emission in the low time versus trap locations on interface and Si substrate has been presented in Fig. 6(a)-(c), for traps at energy levels 0.35, 0.45, and 0.55 eV respectively. The result presented at these three energy levels (rather than five 0.35-0.55) is sufficient to understand the trend of results and avoid the complexity of data.

##### Fig. 6. presents the probability of trapped charge emission in the low time (LT) versus trap locations (on the interface, and Si substrate) at energy levels: (a) 0.35 eV; (b) 0.45 eV; (c) 0.55 eV, respectively.

It is observed that the trap X2 at energy level 0.35 eV, having ~84% emission probability in low time is contributing effectively to substrate current. This conclusion is from all the considered traps in this study. It is also observed that trap Z3 at energy level 0.55 eV having less than 0.01 emission probability in low time is contributing least to substrate current and consequently to device’s failure.

The result presented in Fig. 6(a)-(c), has been presented on the same axis in Fig. 7. This gives us a very clear view of how a trap behaves with changing location and energy level.

It is observed in Fig. 7, that the low time emission from a trap reduces while moving from, deep level to shallow level traps and interface to Si substrate. The result presented in Fig. 7, is very important to understanding the dynamics of an individual-specified trap.

##### Fig. 7. presents the probability of trapped charge emission in the low time (LT) versus trap locations presented inFig. 6(a)-(c), on the same axis.

Based on this result, a special case is discussed in which it is assumed that during the device operation, the emission of electron charge in the low time keeps on accumulating. An accumulated electron charge emission of one femtocoulomb contributing to substrate current is assumed as the threshold value of charge (after which device degradation starts). Based on this assumption, the number of threshold cycles and threshold time (in which one femtocoulomb charge accumulates for each trap) is calculated after which the device starts to degrade. It will be discussed in Section IV.

## IV. ESTIMATED TIME TO START FAILURE BY AN INDIVIDUAL-SPECIFIED TRAP

In this section, the electron charge emitting from each trap during the low time [see Fig. 7] is collected and the number of cycles is counted for each trap to accumulate this emission up to one femtocoulomb. It will be discussed in sub-section 1. The number of cycles required up to the accumulation of one femtocoulomb electron charge contribution to substrate current is along with cycle time is utilized to get the threshold time after which the device starts to degrade. It will be discussed in sub-section 2. The discussion of our results and the implementation of these results in other device models will be explained in sub-section 3.

### 1. Threshold Number of Cycles for an Individual-Specified Trap

A single electron has a charge of 1.60217733e-19 coulombs. And one femtocoulomb equals 6.2415e3 electron charge. To accumulate one femtocoulomb charge in the low time, 6.2415e3 electrons must emit during the low time. Based on the emission from each trap [see Fig. 6(a)-(c)] during the low time, the number of cycles to accumulate this value of charge (6.2415e3 e) in low time was calculated. To calculate the number of threshold cycles, after which device degradation starts, the amount of electron charge that a specific trap emits in the low-time was divided by the amount of electron charge that equals one femtocoulomb (6.2415e3 e).

The calculated, threshold number of cycles for individual specified trap locations has been presented in Fig. 8, for trap energy levels (a) 0.35 eV, (b) 0.45 eV, and (c) 0.55 eV, respectively.

The result presented in Fig. 8(a)-(c), has been presented on the same x-y axis in Fig. 9. This gives us a clear image of how the threshold number of cycles is increasing by moving towards the shallow level traps, and Si substrate.

### 2. Threshold Time for an Individual-specified

The threshold number of cycles to accumulate one femtocoulomb of electron charge (giving rise to substrate current), was multiplied by cycle time (10 ns) to get the threshold time after which device degradation is assumed to start. The calculated start of degradation time for each trap has been presented in Fig. 10, for trap energy levels (a) 0.35 eV, (b) 0.45 eV, and (c) 0.55 eV, respectively.

The result presented in Fig. 10(a)-(c), has been presented on the same x-y axis in Fig. 11. This gives us a clear image of how the threshold time to start degradation is increasing by moving towards the shallow level traps, and Si substrate.

### 3. Discussion

Among the considered individual-specified traps in this study, trap X2 at energy 0.35 eV (from mid-band) needs the least time of 74583.5 ns to emit an electron charge equal to one femtocoulomb during the low time that contributes to substrate current and the device starts to degrade. The trap at this location (-0.031), and energy level (0.35 eV) on the interface is the most effective (worst) trap among the considered traps in this study.

However, the trap Z3 at energy 0.55 eV (from mid-band) needs a maximum time of 984463722.4 ns to emit an electron charge equal to one femtocoulomb in the low time and start degradation in the device. The trap at this location (0.00), and energy level (0.55 eV) in the Si substrate on a sweep of 0.01 ${\mu}$m from the interface is the least effective trap among the considered traps in this study.

To identify the most/least effective trap in any other device or have an estimation of device degradation time, a similar methodology can be implemented with the new specifications of the used device and cycle time.

## V. CONCLUSIONS

This study gives a comprehensive view of the trap’s behavior, prevailing on the Si/SiO$_{2}$ interface or Si substrate of n-MOSFET. It reveals that the traps at variable locations and energy levels contribute to device degradation to a different extent. It is observed that the mismatch of a similar transistor’s operation is highly dependent on traps. Based on the reported results, traps (from the considered traps in this study) having the worst or least contribution to device degradation are identified. A special case is also explained based on the accumulation of electron charge emitting during the low time of device operation and contributing to substrate current. It helps to estimate the start of device degradation for the individual-specified trap.

## ACKNOWLEDGMENTS

This work was supported in part by the Korea Institute for Advancement of Technology (KIAT) through the Korean Government [Ministry of Trade, Industry, and Energy (MOTIE)] (The competency development program for industry specialists) under Grant P0012451, and in part by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, Information and Communication Technologies (ICT) and Future Planning under Grant NRF-2020R1H1A2103043.

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