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Title Quantification of Substrate Current Caused by an Individual Trap at Different Locations and Energies, Prevailing on Si/SiO2 Interface or Si Substrate of n-MOSFETs
Authors (Nosheen Shahzadi) ; (Sanghyeon Baeg)
Page pp.234-243
ISSN 1598-1657
Keywords MOSFET; shallow and deep level traps; Si/SiO2 interface; low time; TCAD simulations
Abstract Traps on Si/SiO2 interface or Si substrate are a big source of variability that cause the mismatch of transistors’ performance and leads to failure. To have a comprehensive view of individual traps, causing random fluctuations, variable trap locations are considered on Si/SiO2 interface and Si substrate. Each trap location is filled with a trap alternatively and simulated via Sentaurus TCAD at five different energy levels (0.35-0.55 eV with a difference of 0.05 eV). The electron charge pumping cycle is recorded to understand each trap's dynamics. In this study, electron charge emission in low time, contributing to substrate current is considered as an indicator to estimate degradation in device performance. The specific value of charge emission in low time contributing to substrate current from an individual-specified trap, reveals the impact of that trap on device degradation. A special case is also discussed to calculate the threshold of failure time based on the accumulation of one femtocoulomb charge in the low time.