I. INTRODUCTION

With the recent advances in technology, the development of applications requiring high power and efficiency, such as computers, electric vehicles, solar power, and smart grids is emerging. Electric vehicles require high-performance power semiconductor devices. Gallium nitride (GaN) has attracted great attention for applications in power electronics due to its wide bandgap, high critical electric field, and thermal resistance ^[1-5].

GaN-based high electron mobility transistors (HEMT) have high breakdown voltage due to the material properties of GaN. In addition, since the on-resistance is reduced via the two-dimensional electron gas (2DEG) with high electron mobility caused by the AlGaN/GaN junction as a channel, it is suitable for high-frequency and high-power semiconductors. However, in the general AlGaN/GaN HEMT, the 2DEG layer is used as a channel to have a negative threshold voltage ($\textit{V}$$_{\mathrm{th}}$), so power consumption is high. Therefore, it is very important for the design to have a positive $\textit{V}$$_{\mathrm{th}}$ to reduce the power loss ^[6].

Recently, many technologies for realizing normally-off HEMT through various methods such as gate injection transistor (GIT) ^[7-9], fluorine plasma treatment ^[10-12], and recessed gate metal insulator semiconductor (MIS) structure ^[13-17] have been studied. GIT is difficult to grow p-GaN and the output current is relatively low as compared to other structures. Additionally, when GaN is grown by metal organic chemical vapor deposition (MOCVD), it becomes n-GaN, so that it is difficult to dope the p-type to grow p-GaN. Fluorine plasma treatment is unstable at high temperatures. Conversely, the recessed gate MIS structure has a relatively simple process and high output current compared to the GIT structure. In addition, since there is an insulator under the gate, it is possible to effectively reduce the gate leakage current ^[18-23].

In this paper, a dual gate insulator is adopted to prevent the increase in the gate leakage current and the off-current and to improve the on-current for general recessed gate AlGaN/GaN MOSFETs. Therefore, Si$_{3}$N$_{4}$ (${\upvarepsilon}$ = 8.9) with relatively better interfacial properties than TiO$_{2}$ (${\upvarepsilon}$ = 80) was first deposited on GaN, and high-k TiO$_{2}$ was deposited on Si$_{3}$N$_{4}$ to fabricate a device. We fabricated two types of dual gate dielectric-based devices with different thicknesses of Si$_{3}$N$_{4}$ and TiO$_{2}$ (Si$_{3}$N$_{4}$/TiO$_{2}$ = 10/20 nm and 20/10 nm) and Si$_{3}$N$_{4}$ single dielectric-base device with the same process. We compared the electric characteristics of the three devices.

II. STRUCTURE AND FABRICATION

Fig. 1(a) and (b) show the schematic cross-sectional view of the single gate dielectric- and dual gate dielectric-based devices, respectively. Fig. 1(c) shows the optical microscope image of the fabricated recessed gate AlGaN/GaN MOSFET. The dual gate dielectric-based device consists of Si$_{3}$N$_{4}$ gate dielectric at the bottom and TiO$_{2}$ gate dielectric at the top. Si$_{3}$N$_{4}$ instead of TiO$_{2}$ is chosen as the material to be deposited directly on GaN as the gate leakage current increases when high-k TiO$_{2}$ is directly bonded to GaN. Later, when TiO$_{2}$ is stacked and used as a dual gate dielectric, the increased oxide capacitance can lead to a high on-state current without significant change in the gate leakage current due to the Si$_{3}$N$_{4}$/GaN junction.

Fig. 2 shows the process flow of the recessed gate AlGaN/GaN MOSFET with Si$_{3}$N$_{4}$/TiO$_{2}$ stacked dual dielectric. The fabricated device was an epitaxial growth of GaN and AlGaN layers using MOCVD on a sapphire substrate. The thicknesses of sapphire substrate, GaN buffer, GaN channel, and AlGaN layers are 430 ${μ}$m, 2.1 ${μ}$m, 180 nm, and 25 nm, respectively. The Al composition in the AlGaN layer was 21%. The sheet carrier density and the electron mobility obtained by hall measurements were 8 ${\times}$ 10$^{12}$cm$^{-2}$ and 1200 cm/V${\cdot}$s, respectively. To physically insulate each device, 380 nm depth mesa insulation was performed by Cl$_{2}$-based inductively coupled plasma-reactive ion etcher (ICP-RIE). After the mesa process, a 50 nm-thick Si$_{3}$N$_{4}$ layer was deposited via plasma enhanced chemical vapor deposition (PECVD) to be used as a hard mask in the recessed gate process. In the gate recess etching process, a 25 nm-thick AlGaN layer was etched by Cl$_{2}$-based ICP-RIE. Then, the Si$_{3}$N$_{4}$ layer used as the gate dielectric was deposited via PECVD. Subsequently, TiO$_{2}$ layer used as the gate dielectric was deposited by atomic layer deposition. Before depositing the ohmic contact metal, BOE solution was used to open the oxide at the location to enter the source and drain metals. Next, the material to be used as the ohmic contact metal of the source and drain consisting of Ti/Al/Ni/Au (25/160/40/100 nm), was deposited using an electron-beam (E-beam) evaporator. To form an ohmic contact, annealing was performed at 800$^{\circ}$C for 30 s in the nitrogen (N$_{2}$) atmosphere. Finally, a gate metal composed of Ni/Au (40/100 nm) material was deposited using an E-beam evaporator.

Fig. 1. The schematic cross-sections of the recessed gate AlGaN/GaN MOSFET with (a) the single gate dielectric, (b) dual gate dielectric, (c) The optical microscope image of the fabricated the recessed gate AlGaN/GaN MOSFET.

Fig. 2. Process flow of the recessed gate AlGaN/GaN MOSFET with Si$_{3}$N$_{4}$/TiO$_{2}$ stacked dual dielectric.

III. RESULTS AND DISCUSSION

Fig. 3(a) and (b) show the transfer curve of the single gate dielectric and dual gate dielectric-based devices. The on- state drain current ($\textit{I}$$_{\mathrm{D,max}}$) is defined at $\textit{V}$$_{\mathrm{GS}}$ = 10 V and $\textit{V}$$_{\mathrm{DS}}$ = 10 V. $\textit{V}$$_{\mathrm{th}}$ is obtained by linear extrapolation. A dual dielectric-based device has higher on-current and transconductance ($\textit{g}$$_{\mathrm{m}}$) than a single dielectric-based device. Among the two types, the dual gate dielectric (Si$_{3}$N$_{4}$/TiO$_{2}$ = 10/20 nm)-based device exhibited the highest current characteristics, with the $\textit{V}$$_{\mathrm{th}}$ of 1.81 V, $\textit{I}$$_{\mathrm{D,max}}$ of 7.95 mA, $\textit{g}$$_{\mathrm{m}}$ of 1.12 mS, and subthreshold swing ($\textit{SS}$) of 229 mV/dec. The measured electrical characteristics of the fabricated devices are summarized in Table 1. The current characteristics were improved for the dual gate dielectric because of higher capacitance than the single Si$_{3}$N$_{4}$ gate dielectric. The formula for calculating the capacitance is as follows:

where $\varepsilon _{{\mathrm{TiO}_{2}}}$(=80) and $\varepsilon _{{\mathrm{Si}_{3}}{\mathrm{N}_{4}}}$(=8) are the relative dielectric constants of TiO$_{2}$ and Si$_{3}$N$_{4}$, respectively. $\varepsilon _{0}$ is the vacuum permittivity. $\mathrm{t}_{{\mathrm{TiO}_{2}}}$and $\mathrm{t}_{{\mathrm{Si}_{3}}{\mathrm{N}_{4}}}$are the thicknesses of TiO$_{2}$ and Si$_{3}$N$_{4}$, respectively. $\mathrm{C}_{{\mathrm{TiO}_{2}}}$ and $\mathrm{C}_{{\mathrm{Si}_{3}}{\mathrm{N}_{4}}}$ are the capacitances of TiO$_{2}$ and Si$_{3}$N$_{4}$, respectively, and $\mathrm{C}_{\text{total}}$ is the total accumulation capacitance. The calculated capacitances of the single gate dielectric (Si$_{3}$N$_{4}$ = 30 nm), dual gate dielectric (Si$_{3}$N$_{4}$/TiO$_{2}$ = 20/10 nm) and dual gate dielectric (Si$_{3}$N$_{4}$/TiO$_{2}$ = 10/20 nm) were 236 nF/cm$^{2}$, 337 nF/cm$^{2}$, and 590 nF/cm$^{2}$ respectively. In MOSFET, $\textit{I}$$_{\mathrm{D}}$ is proportional to $\textit{C}$$_{\mathrm{ox}}$, so using a dual gate dielectric increases the on-current. Therefore, compared to the single gate dielectric-based device, the $\textit{I}$$_{\mathrm{D,max}}$ and $\textit{g}$$_{\mathrm{m}}$ of the dual gate dielectric-based device were improved by 292% and 195%, respectively.

Fig. 4(a) shows the $\textit{C}$${-}$$\textit{V}$ curves of the single gate dielectric- and dual gate dielectric-based devices which with almost similar capacitance to the calculated one, and the dual gate dielectric (Si$_{3}$N$_{4}$/TiO$_{2}$ = 10/20 nm)-based device exhibited the highest capacitance. In Fig. 4(a), the slope of the dual gate dielectric (Si$_{3}$N$_{4}$/TiO$_{2}$ = 20/10 nm)-based device was the largest, with high $\textit{SS}$ due to a high slope. The slope of the $\textit{C}$-$\textit{V}$ curve is affected by the interface trap between the gate oxide and the semiconductor junction. Therefore, dual gate dielectric (Si$_{3}$N$_{4}$/TiO$_{2}$ = 20/10 nm)-based device has the highest interface trap density ($\textit{D}$$_{\mathrm{it}}$).

Fig. 4(b) shows the $\textit{G}$$_{\mathrm{p}}$/${\omega}$ vs $\textit{V}$$_{\mathrm{GS}}$ characteristics of the single gate dielectric and dual gate dielectric-based devices. $\textit{D}$$_{\mathrm{it}}$ was extracted using the conductance method. The formula to calculate $\textit{G}$$_{\mathrm{p}}$/${\omega}$ is as follows ^[24,25]:

where ${\omega}$ (=2${π}$f) is the angular frequency, $\textit{C}$$_{\mathrm{ox}}$ is the gate oxide capacitance, $\textit{G}$$_{\mathrm{p}}$ is the parallel conductance, $\textit{G}$$_{\mathrm{m}}$ is the measured conductance, and $\textit{C}$$_{\mathrm{m}}$ is the measured capacitance. Moreover, the formula to calculate $\textit{D}$$_{\mathrm{it}}$ is as follows ^[24,25]:

where A is the area of the proposed device and q is the electronic charge in coulombs. $\textit{D}$$_{\mathrm{it}}$ of the single gate dielectric (Si$_{3}$N$_{4}$ = 30 nm), dual gate dielectric (Si$_{3}$N$_{4}$/TiO$_{2}$ = 20/10 nm), and dual gate dielectric (Si$_{3}$N$_{4}$/TiO$_{2}$ = 10/20 nm)-based device extracted from the Eq. (5) were 2.79 ${\times}$ 10$^{13}$ cm$^{-2}$${\cdot}$eV$^{-1}$, 1.37 ${\times}$ 10$^{14}$ cm$^{-2}$${\cdot}$eV$^{-1}$, and 2.53 ${\times}$ 10$^{12}$ cm$^{-2}$${\cdot}$eV$^{-1}$, respectively.

Fig. 5(a)-(c) show the pulsed $\textit{I}$${-}$$\textit{V}$ curves of the single gate dielectric and dual gate dielectric-based devices. Pulsed $\textit{I}$${-}$$\textit{V}$ measurement was performed using the curve tracer B1500A instrument. Gate stress bias $\textit{V}$$_{\mathrm{GS}}$ = ${-}$2 V was applied to completely turn-off the device. Specific on resistances ($\textit{R}$$_{\mathrm{on}}$) of the single-gate dielectric (Si$_{3}$N$_{4}$= 30 nm), dual-gate dielectric (Si$_{3}$N$_{4}$/TiO$_{2}$ = 20/10 nm), and dual-gate dielectric (Si$_{3}$N$_{4}$/TiO$_{2}$ = 10/20 nm)-based devices were 116 ${\omega}$${\cdot}$mm, 58 ${\omega}$${\cdot}$mm, and 43 ${\omega}$${\cdot}$mm, respectively. And the ${\Delta}$$\textit{I}$$_{\mathrm{D,max}}$ was 1.64%, 3.5%, and 2.91%, respectively. The ${\Delta}$$\textit{I}$$_{\mathrm{D,max}}$ of the three devices was low due to the MIS structure which improved the gate lag. $\textit{R}$$_{\mathrm{on}}$ was 62% improvement in the dual gate dielectric-based device with a higher capacitance than a single-gate dielectric-based device, so the performance improvement can be expected in a switching device.

Fig. 6 shows the breakdown voltage (BV) characteristics of the single gate dielectric and dual gate dielectric-based devices with an off-state. BV was extracted at $\textit{I}$$_{\mathrm{D}}$=1 mA/mm. The BV values of single gate dielectric (Si$_{3}$N$_{4}$ = 30 nm), dual gate dielectric (Si$_{3}$N$_{4}$/TiO$_{2}$ = 20/10 nm), and dual gate dielectric (Si$_{3}$N$_{4}$/TiO$_{2}$ = 10/20 nm)-based devices were 572 V, 556 V and 564 V, respectively, with no significant difference because of no change in the structure.

Fig. 7 shows the simulated results of the single gate dielectric (Si$_{3}$N$_{4}$ = 30 nm) and dual gate dielectric (Si$_{3}$N$_{4}$/TiO$_{2}$ = 10/20 nm)-based devices at $\textit{V}$$_{\mathrm{GS}}$ = ${-}$2.5 V and $\textit{V}$$_{\mathrm{DS}}$ = 500 V. Fig. 7(a) and (b) show the contour map of the electric field distribution of the single gate dielectric (Si$_{3}$N$_{4}$ = 30 nm) and dual gate dielectric (Si$_{3}$N$_{4}$/TiO$_{2}$ = 10/20 nm)-based devices. Fig. 7(c) shows the electric field distribution along the A${-}$A$^{\prime}$ cut line at the peak electric field strength, and the electric fields of single gate dielectric- and dual gate dielectric (Si$_{3}$N$_{4}$/TiO$_{2}$ = 10/20 nm)-based devices were almost similar. BV is greatly affected by the peak electric field with a little change in BV because of a small change in the peak electric field.

Fig. 3. The transfer curve of single gate dielectric and dual gate dielectric-based device with (a) $\textit{g}$$_{\mathrm{m}}$, (b) gate current.

Fig. 4. (a) The $\textit{C}$${-}$$\textit{V}$ curves, (b) $\textit{G}$$_{\mathrm{p}}$/${\omega}$ vs $\textit{V}$$_{\mathrm{gs}}$ characteristics of the single gate dielectric and dual gate dielectric-based devices.

Fig. 5. The pulsed $\textit{I}$$_{\mathrm{D}}$${-}$$\textit{V}$$_{\mathrm{DS}}$ transfer curve of recessed gate AlGaN/GaN MOSFETs with (a) Si$_{3}$N$_{4}$ = 30 nm, (b) Si$_{3}$N$_{4}$/TiO$_{2}$ = 20 nm/10 nm, (c) Si$_{3}$N$_{4}$/TiO$_{2}$ = 10 nm/20 nm with $\textit{L}$$_{\mathrm{G}}$ = 5 ${μ}$m, $\textit{L}$$_{\mathrm{GD}}$ = 5 ${μ}$m, $\textit{W}$$_{\mathrm{G}}$ = 50 ${μ}$m.

Fig. 6. The BV characteristics of single gate dielectric and dual gate dielectric-based devices with off-state.

Fig. 7. The contour map of the electric field distribution of (a) single gate dielectric (Si$_{3}$N$_{4}$ = 30 nm), (b) dual gate dielectric (Si$_{3}$N$_{4}$/TiO$_{2}$ = 10/20 nm)-based devices at $\textit{V}$$_{\mathrm{GS}}$ = ${-}$2.5 V and $\textit{V}$$_{\mathrm{DS}}$ = 500 V, (c) The Electric field distribution along the A${-}$A$^{\prime}$ cut line at the peak electric field strength.

IV. CONCLUSION

This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. NRF-2020R1A2C1005087). This study was supported by the BK21 FOUR project funded by the Ministry of Education, Korea (4199990113966). This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (NRF-2021R1A6A3A13039927). This research was supported by National R&D Program through the National Research Foundation of Korea (NRF) funded by Ministry of Science and ICT (2021M3F3A2A03017764). This investigation was financially supported by Semiconductor Industry Collaborative Project between Kyungpook National University and Samsung Electronics Co. Ltd. The EDA tool was supported by the IC Design Education Center (IDEC), Korea.