In this paper, a compact macromodeling method for characterizing the large-signal characteristics of heterojunction bipolar transistors (HBTs) is proposed and successfully applied to describe the DC and AC performance of InP and GaAs HBT devices. Using the Symbolically-defined Device (SDD) technology, an empirical macro circuit preserving the Spice Gummel-Poon (SGP) intrinsic network and a simplified thermal network is established. The empirical current and charge functions are embedded in the SDD macro circuit network module. Compared with other large-signal models, the proposed model description and the relevant parameter extraction are relatively simpler, and at the same time, this method can maintain high fitting accuracy. To assess the validity and the accuracy of the proposed model, the compact large-signal model is constructed for 1 μm InP HBT and 1 μm GaAs HBT. Based on the complete extraction of the model parameters, excellent consistency is obtained between the measured and modeled results.

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## I. INTRODUCTION

In recent years, semiconductor technology has developed rapidly, and semiconductor
devices have been widely used in the fields of microwave and millimeter-wave ^{[1,}^{2]}. Compared with CMOS devices, heterojunction bipolar transistors (HBTs) have a wider
bandgap, faster electron saturation speed, and higher cut-off frequency, so they are
more suitable for the design of ultra-high-speed integrated circuits ^{[3-}^{5]}. Though the HBTs have a great prospect in the future application of microwave and
millimeter-wave frequencies, the development of its device model is still in the exploratory
stage. The successful design of a circuit requires an accurate large-signal model
that can describe the DC and AC characteristics of the device within a certain range
of bias and signal frequency ^{[6,}^{7]}, which makes the research on the device model extremely important.

Recently, several papers on HBT device models have been published in many authoritative
journals ^{[8-}^{14]}, which are devoted to creating device models for CAD tools and model parameter extraction
programs. Although a great deal of work has been done on this research, there is still
no unified and accurate model standard and automatic extraction procedure for industrial
application. The main reasons are that the physical model of the device is very complex
^{[15-}^{17]}, the current range is very wide, and the power density of the device is very high
during operation, which is more obvious in high-power devices. In addition, when the
model is complex, another difficulty of model parameter extraction is that the established
model may have convergence problems during the circuit simulation. At the same time,
the calibration of the test equipment of RF devices and the parasitic de-embedding
of pads will affect the accuracy of parameter extraction.

Besides, the topological structure and physical meaning of the equivalent circuit, the extraction method of parameters, and so on will also have a certain impact on the accuracy of the device model. All of these issues, along with the low thermal conductivity of III-V materials, make it particularly difficult to create a general large-signal model for HBTs.

When HBT devices are used for large-signal applications, the high-power densities
associated with these devices generate lots of heat ^{[18-}^{20]}. Moreover, due to the low conductivity of GaAs and InP, the heating phenomenon is
more likely to occur, leading to the increase of device temperature. This phenomenon
(self-heating effect) is particularly important in predicting the large-signal behavior
of devices. Several methods to simulate the self-heating effect have been reported
in the past ^{[21-}^{24]}. These methods involve complex analysis of the thermal-electric coupled field calculation.
What’s more, collector current transit time is also an important parameter in the
HBT model. Generally, the base region of the device is highly doped to reduce the
thin-layer resistance, while the collector is lightly doped to reduce the base-collector
capacitance and increase the breakdown voltage. Therefore, high current injection
occurs in the collector region, resulting in the modulation effect of the base-collector
space charge region, which changes the collector transit time. To simulate the high-frequency
characteristics, a variety of numerical models have been developed to simulate the
base-collector capacitance. However, the nonlinear field dependence of electronic
velocity and self-heating effect in InP-based and GaAs-based HBT devices makes the
analysis and calculation process extremely complex. In engineering applications, therefore,
to improve the success rate of integrated circuit design and reduce the design time
and cost, it is necessary to develop empirical models.

Given this, a simple and accurate macromodeling method is proposed in this paper.
Compared with the Agilent model ^{[25]}, the proposed model discards the division of intrinsic and extrinsic parts in DC
model and overcomes the drawback of the Agilent model not being able to simulate leakage
current. And it avoids the tedious establishment of the depletion charge model, in
which the Agilent model needs at least 14 parameters to simulate the junction capacitances.
In this part, however, the proposed model only needs to extract 6 empirical parameters
and maintains relatively accurate fitting results. Finally, the proposed model is
verified by applying it to a 1 $\mu$m InP HBT and a 1 $\mu$m GaAs HBT devices.

## II. DEVICE STRUCTURE AND EXPERIMENT

The cross section of the adopted InP HBT which was fabricated by the Institute of Microelectronics in the Chinese Academy of Sciences is shown in Fig. 1. The structure consists of 300 nm of InP (Si: 3 $\times$ 10$^{19}$ cm$^{-3}$) and 25 nm of In$_\mathrm{0.53}$Ga$_\mathrm{0.67}$As (Si: 3 $\times$ 10$^{19}$ cm$^{-3}$) and 50 nm of InP (Si: 1.2 $\times$ 10$^{19}$ cm$^{-3}$) as the subcollector, 160 nm of InP (Si: 2 $\times$ 10$^{16}$ cm$^{-3}$) as the collector, 10 nm of In$_\mathrm{0.88}$Ga$_\mathrm{0.12}$As$_\mathrm{0.27}$P$_\mathrm{0.73}$ (Eg = 1.15 eV) and 10 nm of In$_\mathrm{0.73}$Ga$_\mathrm{0.27}$As$_\mathrm{0.58}$P$_\mathrm{0.42}$ (Eg = 0.95 eV) and 20 nm of In$_\mathrm{0.53}$Ga$_\mathrm{0.47}$As (Si:2 $\times$ 10$^{16}$ cm$^{-3}$) as the grade layer, 40 nm of InGaAs as the base layer (C: 4 $\times$ 10$^{19}$ cm$^{-3}$), 60 nm of InP as the emitter (Si:3 $\times$ 10$^{17}$ cm$^{-3}$), and 100 nm of InP (Si: 3 $\times$ 10$^{19}$ cm$^{-3}$) and 200 nm of In$_\mathrm{0.53}$Ga$_\mathrm{0.67}$As as the cap layer (Si: 3 $\times$ 10$^{19}$ cm$^{-3}$). On-chip DC characteristic measurements were made with Keysight B2902A Semiconductor Device Analyzer. Scattering parameters ($\textit{S}$-parameters) were measured by employing Rohde & Schwarz ZVA 50 Network Analyzer. All measurements were carried out on wafer using Cascade Microtech’s Probes ACP50-GSG-150.

The adopted GaAs HBT was fabricated by the WIN Semiconductors Corporation, Tao Yuan
Shien, Taiwan (type Q1H201B1). The width and length of each emitter mesa for Q1H201B1
are 1 and 20 $\mu$m, respectively. And the details of the technological process are
described in ^{[26]}.

## III. MODEL CONSTRUCTION

### 1. Model Topologyitle

The model topological structure proposed in this paper includes an empirical macro circuit preserving the Spice Gummel-Poon (SGP) intrinsic network and a simplified thermal network. Fig. 2 shows the equivalent circuit diagram of the topology used in the large-signal model, with the SGP intrinsic network in the dotted box. The intrinsic unit includes the collector transmission current $\textit{I}$$_\mathrm{CE}$, base-emitter current $\textit{I}$$_\mathrm{BE}$, base-collector current $\textit{I}$$_\mathrm{BC}$, intrinsic base-emitter charge $\textit{Q}$$_\mathrm{BEI}$, intrinsic base-collector charge $\textit{Q}$$_\mathrm{BCI}$, intrinsic base resistance $\textit{R}$$_\mathrm{bi}$, and intrinsic collector resistance $\textit{R}$$_\mathrm{ci}$. The extrinsic unit includes extrinsic base-emitter charge $\textit{Q}$$_\mathrm{BEX}$, extrinsic base-collector charge $\textit{Q}$$_\mathrm{BCX}$, emitter resistance $\textit{R}$$_\mathrm{e}$, extrinsic base resistance $\textit{R}$$_\mathrm{bx}$, extrinsic collector resistance $\textit{R}$$_\mathrm{cx}$. The simplified thermal network shown in Fig. 3 includes device thermal resistance $\textit{R}$$_\mathrm{TH}$, device thermal capacity $\textit{C}$$_\mathrm{TH}$, dissipated power $\textit{P}$$_\mathrm{diss}$.

### 2. Direct-current Model

The collector transmission current $\textit{I}$$_\mathrm{CE}$ is usually regarded as the sum of forward collector current $\textit{I}$$_\mathrm{CC}$ and reverse emitter current $\textit{I}$$_\mathrm{EC}$, so the empirical Direct-Current (DC) model includes four parts: forward collector current $\textit{I}$$_\mathrm{CC}$, reverse emitter current $\textit{I}$$_\mathrm{EC}$, base-emitter current $\textit{I}$$_\mathrm{BE}$, and base-collector current $\textit{I}$$_\mathrm{BC}$. For $\textit{I}$$_\mathrm{BC}$, when the base-collector voltage $\textit{V}$$_\mathrm{BC}$ is small ($\textit{V}$$_\mathrm{BC}$$\leq$ 0.6 Vfor InP HBT, $\textit{V}$$_\mathrm{BC}$$\leq$ 1.2 V for GaAs HBT), the base current is mainly composed of the recombination current of the emitter space charge region and the surface recombination current, and this region is called non-ideal area. When $\textit{V}$$_\mathrm{BC}$ is large ($\textit{V}$$_\mathrm{BC}$> 0.6 Vfor InP HBT, $\textit{V}$$_\mathrm{BC}$> 1.2 V for GaAs HBT), this region is called ideal area. Thus, $\textit{I}$$_\mathrm{BC}$ covers the ideal and non-ideal behavior as shown in Eq. (2). For $\textit{I}$$_\mathrm{EC}$, the non-ideal behavior is not considered, and the expression of $\textit{I}$$_\mathrm{EC}$ is shown in Eq. (3). In addition, we define Eq. (1) as an empirical function, and $\textit{i}$,$\textit{v}$,$\textit{x}$ in it are formal parameters, which can be replaced by the empirical parameters in Eqs. (2)-(5).

##### (2)

$$ I_{\mathrm{BC}}=\sum_{p=\mathrm{I}, \mathrm{N}} \operatorname{diOde}\left(I_{\mathrm{em}, \mathrm{BC} p}, V_{\mathrm{BC}}, N_{\mathrm{em}, \mathrm{BC} p}\right) $$##### (3)

$$ I_{\mathrm{EC}}=\operatorname{diOde}\left(I_{\mathrm{em,ECI}}, V_{\mathrm{BC}}, N_{\mathrm{em,ECI}}\right) $$where $\textit{I}$$_\mathrm{em,BC}$$_{p}$, $\textit{N}$$_\mathrm{em,BC}$$_{p}$, $\textit{I}$$_\mathrm{em,ECI}$, $\textit{N}$$_\mathrm{em,ECI}$ are the reverse current empirical parameters, $\textit{p}$=I and $\textit{p}$=N represent the ideal and non-ideal current regions, respectively.

Similar to base-collector current $\textit{I}$$_\mathrm{BC}$, $\textit{V}$$_\mathrm{BE}$ is the base-emitter voltage, and the base-emitter current $\textit{I}$$_\mathrm{BE}$ includes not only the ideal current ($\textit{V}$$_\mathrm{BE}$$\leq$ 0.6 Vfor InP HBT, $\textit{V}$$_\mathrm{BE}$$\leq$ 1.2 V for GaAs HBT) and the non-ideal current ($\textit{V}$$_\mathrm{BE}$> 0.6 Vfor InP HBT, $\textit{V}$$_\mathrm{BE}$> 1.2 V for GaAs HBT), but also the leakage current ($\textit{V}$$_\mathrm{BE}$$\leq$ 0.4 V for InP HBT, $\textit{V}$$_\mathrm{BE}$$\leq$ 0.9 V for GaAs HBT), as shown in Eq. (4). The forward collector current $\textit{I}$$_\mathrm{CC}$ consists of ideal current and leakage current as shown in Eq. (5).

##### (4)

$$ I_{\mathrm{BE}}=\sum_{p=\mathrm{L}, \mathrm{I}, \mathrm{N}} \operatorname{diode}\left(I_{\mathrm{em}, \mathrm{BE} p}, V_{\mathrm{BE}}, N_{\mathrm{em}, \mathrm{BE} p}\right) $$##### (5)

$$ I_{\mathrm{CC}}=\sum_{p=\mathrm{L}, \mathrm{I}} \operatorname{diode}\left(I_{\mathrm{em}, \mathrm{CC} p}, V_{\mathrm{BE}}, N_{\mathrm{em}, \mathrm{CC} p}\right) $$where $\textit{I}$$_\mathrm{em,BE}$$_{p}$, $\textit{N}$$_\mathrm{em,BE}$$_{p}$, $\textit{I}$$_\mathrm{em,CC}$$_{p}$, $\textit{N}$$_\mathrm{em,CC}$$_{p}$ are the forward current empirical parameters, $\textit{p}$=L, $\textit{p}$=I, and $\textit{p}$=N represent the leakage, ideal and non-ideal current regions, respectively.

### 3. Direct-current Model

The empirical Alternating-Current (AC) model includes the junction capacitance model and diffusion charge model. Among them, the junction capacitance model includes base-collector junction capacitance $\textit{C}$$_\mathrm{BC}$ and base-emitter junction capacitance $\textit{C}$$_\mathrm{BE}$, as shown in Eqs. (6)-(8).

##### (6)

$$ C_{\mathrm{B} n}=W \cdot C_{\mathrm{B} n \mathrm{i}}+(1-W) \cdot C_{\mathrm{B} n \mathrm{x}} \quad(n=\mathrm{C}, \mathrm{E}) $$##### (7)

$$ C_{\mathrm{BC} t}=C_{\mathrm{em}, \mathrm{C}}\left(1-C o_{\mathrm{em}, \mathrm{C}} \cdot V_{\mathrm{BC} t}\right)^{-M_{\mathrm{em}, \mathrm{C}}} \quad(t=\mathrm{i}, \mathrm{x}) $$##### (8)

$$ C_{\mathrm{BE} t}=C_{\mathrm{em}, \mathrm{E}}\left(1-C o_{\mathrm{em}, \mathrm{E}} \cdot V_{\mathrm{BE} t}\right)^{-M_{\mathrm{em}, \mathrm{E}}} \quad(t=\mathrm{i}, \mathrm{x}) $$where $\textit{C}$$_\mathrm{em,C}$, $\textit{Co}$$_\mathrm{em,C}$, $\textit{M}$$_\mathrm{em,C}$ and $\textit{C}$$_\mathrm{em,E}$, $\textit{Co}$$_\mathrm{em,E}$, $\textit{M}$$_\mathrm{em,E}$ are the BC and BE junction capacitance empirical parameters, respectively. $\textit{W}$ is a weight factor with values between 0 and 1, $\textit{V}$$_\mathrm{Bnt}$ is the bias voltage, $\textit{C}$$_\mathrm{Bn}$ is the junction capacitance. $\textit{n}$=C and $\textit{n}$=E represent the collector and emitter, respectively. $\textit{t}$=i and $\textit{t}$=x represent the intrinsic and extrinsic region parameters, respectively. The characteristic description of junction capacitance is regarded as the superposition of intrinsic junction capacitance and extrinsic junction capacitance.

The diffusion charge model includes three charge elements: base delay charge ($\textit{Q}$$_\mathrm{tb}$), Krik effect charge ($\textit{Q}$$_\mathrm{krk}$), and collector delay charge ($\textit{Q}$$_\mathrm{tc}$). Thus, the model divides the transit time parameters into three types, and the above three kinds of charges are corresponding to $\tau$$_\mathrm{b}$, $\tau$$_\mathrm{krk}$, and $\tau$$_\mathrm{c}$, respectively, as shown in Eqs. (9)-(15).

where $\tau$$_\mathrm{b}$ is the base transit time, $\textit{Q}$$_\mathrm{tb}$ is the base delay charge, $\textit{TFB}$ represents the constant value of $\tau$$_\mathrm{b}$, $\textit{I}$$_\mathrm{CC}$ is the forward collector current.

##### (10)

$$ Q_{\mathrm{krk}}=\int \tau_{\mathrm{krk}} d I_{\mathrm{CC}}=T K R K \cdot \frac{I_{\mathrm{CC}}}{V K R K} \cdot\left(\frac{I_{\mathrm{CC}}}{I_{\mathrm{kirk} 2}}\right)^{G k r k} $$##### (11)

$$ V_{\mathrm{bc}_{-} \text {eff }}=V K T R \cdot \ln \left(\exp \left(\frac{V K M X+V_{\mathrm{bci}}}{V K T R}\right)+1\right)-V K M X $$where $\tau$$_\mathrm{krk}$ is the Kirk effect transit time, $\textit{Q}$$_\mathrm{krk}$ is the Kirk effect charge, $\textit{V}$$_\mathrm{bci}$ is the intrinsic base-collector voltage, $\textit{TKRK}$ is the delay time correlation of Kirk effect, $\textit{Gkrk}$ is the delay index factor of Kirk effect, $\textit{V}$$_{\text {bc_eff }}$ represents the non-linear change of electron speed with voltage, $\textit{IKRK}$ is the Kirk effect current, $\textit{VKRK}$ is the voltage of Kirk effect current changing with $\textit{V}$$_\mathrm{cb}$, $\textit{VKMX}$ is the maximum of $\textit{V}$$_\mathrm{cb}$, $\textit{VKTR}$ is the crossing width from $\textit{V}$$_\mathrm{cb}$ to $\textit{VKMX}$.

##### (13)

$$ \begin{aligned} Q_{\mathrm{tc}}=& \int \tau_{\mathrm{c}} d I_{\mathrm{CC}}=T C M I N \cdot I_{\mathrm{CC}} \cdot\left(1-\frac{V_{\mathrm{bc}_{2} \text { eff }}}{V T C M I N}\right) \\ &+\frac{1}{2} T F C 0 \cdot\left(I_{\mathrm{CC}}-I_{\mathrm{tc} 2}\right) \cdot\left(1-\frac{V_{\mathrm{bc} \text { _eff }}}{V T C 0}\right) \end{aligned} $$##### (14)

$$ I_{\mathrm{tc} 2}=I T C 2 \cdot\left(1-\frac{V_{\mathrm{bci}}}{V T C 2}\right) \cdot \ln \left(\cosh \left(\frac{I T C \cdot\left(1-\frac{V_{\mathrm{bci}}}{V T C}\right)-I_{\mathrm{CC}}}{I T C 2 \cdot\left(1-\frac{V_{\mathrm{bci}}}{V T C 2}\right)}\right)\right) $$where $\tau$$_\mathrm{c}$ is the collector transit time, $\textit{Q}$$_\mathrm{tc}$ is the collector delay charge, $\textit{TCMIN}$ is the transit time of high current, $\textit{TFC}$0 is the transit time of low current. $\textit{ITC}$ and $\textit{ITC}$2 are the intermediate current and the width of the collector current between $\textit{TFC}$0 and $\textit{TCMIN}$, respectively. $\textit{VTCMIN}$, $\textit{VTC}$0, $\textit{VTC}$, and $\textit{VTC}$2 are the variation of $\textit{TCMIN}$, $\textit{TFC}$0, $\textit{ITC}$, and $\textit{ITC}$2 with $\textit{V}$$_\mathrm{cb}$, respectively. $\textit{I}$$_\mathrm{EC}$ is the reverse emitter current, $\tau$$_\mathrm{r}$ is the reverse transit time, $\textit{Q}$$_\mathrm{tr}$ is the reverse delay charge.

### 4. Thermal Model

When the HBT device is in the high-power application, the increase of collector current
leads to the higher junction temperature of the device, which reduces the electron
saturation rate and leads to the decrease of current gain. It is particularly important
to characterize this phenomenon in predicting the large-signal behavior of devices
^{[27]}. In this paper, this effect is simulated by the first-order RC thermal network as
shown in Fig. 3, and its model description can be expressed as Eqs. (16) and (17).

##### (16)

$$ P_{\mathrm{diss}}=\frac{\Delta T}{R_{\mathrm{TH}}}+C_{\mathrm{TH}} \frac{d \Delta T}{d t} $$where $\textit{T}$$_\mathrm{dev}$ is the internal temperature of the device, $\textit{T}$$_\mathrm{nom}$ isthe room temperature. $\textit{R}$$_\mathrm{TH}$ is the device thermal resistance, $\textit{C}$$_\mathrm{TH}$ is the device thermal capacity, $\textit{P}$$_\mathrm{diss}$ is the dissipated power. charge.

### 5. Model Implementation

The proposed HBT model is implemented by SDD technology in the Advanced Design System,
which can be used to directly simulate the characteristics of the devices. In the
SDD module, functions describing the port voltage and current correlation are Explicit
Function and Implicit Function. When there is more than one expression on a port,
it will add each of the independent equations together to form a final expression.
Thus, it is convenient to build a non-linear device by defining the port I-V equations
^{[28]} with SDD technology.

The SDD module shown in Fig. 4 is an 8-port device represented by equations. The module and the large-signal model of the proposed topology are completely equivalent, and the constitutive relation between port current and port voltage is dealt with in the time domain.

## IV. RESULTS AND DISCUSSION

### 1. DC Characteristics

Forward Gummel test method and reverse Gummel test method ^{[29]} are used to obtain the measurement data of base-emitter current $\textit{I}$$_\mathrm{BE}$
and forward collector current $\textit{I}$$_\mathrm{CC}$, base-collector current $\textit{I}$$_\mathrm{BC}$
and reverse emitter current $\textit{I}$$_\mathrm{EC}$, respectively. For the extraction
of $\textit{I}$$_\mathrm{BE}$ parameters in the ideal region, we measure the relationship
curve between ln($\textit{I}$$_\mathrm{BE}$) and $\textit{V}$$_\mathrm{BE}$, and use
the intercept and slope of the curve to obtain the values of $\textit{I}$$_\mathrm{em,BEI}$
and $\textit{N}$$_\mathrm{em,BEI}$, respectively. And the similar extraction process
is used to obtain the DC parameters in other areas. The comparisons shown in Fig. 5 and 6 demonstrates that the proposed model presents a good agreement with the measured
data, which verifies the validity and the accuracy of the DC current model. Furthermore,
the proposed DC model(solid line) overcomes the drawback of the Agilent model(dotted
line) not being able to simulate leakage currents as shown in the leakage region in
Fig. 5.

The comparison between HBT $\textit{I}$$_\mathrm{C}$-$\textit{V}$$_\mathrm{CE}$ DC
output characteristic measured and modeled results is shown in Fig. 7, for GaAs HBT, the input $\textit{I}$$_\mathrm{b}$ was 10 ~ 50 $\mu$A from bottom
to top, and the step value was 10 $\mu$A, for InP HBT, the input $\textit{I}$$_\mathrm{b}$
was 20 ~ 180 $\mu$A from bottom to top, and the step value was 40 $\mu$A. As shown
in this figure, as the collector-emitter voltage $\textit{V}$$_\mathrm{CE}$ increases,
the self-heating effect is obvious in the high current and high-power region. And
we simulate this effect using the network in Fig. 3, in which the thermal parameters can be obtained from the method in Ref. ^{[13]}. In the process of simulating the DC output characteristics, it is necessary to adjust
and extract the intrinsic collector resistance parameter $\textit{R}$$_\mathrm{ci}$,
which describes the quasi-saturation effect of the device.

### 2. AC Characteristics

The measured junction capacitances are obtained by converting the measured results
of the $\textit{S}$-parameter at a fixed frequency into the $\textit{Y}$-parameter
and then calculated ^{[30]}, as shown in Eqs. (18) and (19). For the extraction of BC junction capacitance empirical parameters, we perform logarithmic
processing on both sides of Eq. (7), and use linear regression to extract the capacitance parameters. Given several different
$\textit{Co}$$_\mathrm{em,C}$ values, compare the linear errors of Eq. (7) fitted under different $\textit{Co}$$_\mathrm{em,C}$ values after logarithmic processing,
and select the $\textit{Co}$$_\mathrm{em,C}$ value with the smallest error. And in
the process of linear fitting, $\textit{C}$$_\mathrm{em,C}$ and $\textit{M}$$_\mathrm{em,C}$
are obtained from the intercept and the slope, respectively. And the BE junction capacitance
empirical parameters are extracted in a similar way. Comparisons of the capacitance
measured and modeled results of BC junction and BE junction are shown in Fig. 8 and 9, respectively. Compared with the Agilent model, the proposed model avoids the cumbersome
establishment of the depletion charge model and maintains relatively accurate fitting
results.

where $\omega$ is the angular frequency, $\textit{Y}$$_{11}$ is the input admittance with output port short-circuited, $\textit{Y}$$_{12}$ is the reverse transmission admittance with input port short-circuited.

For the transit time parameters in the diffusion charge model, because the base region of III-V group HBT is highly doped, the base region transit time parameter $\tau$$_\mathrm{b}$ can be regarded as constant. The Kirk effect is more obvious at high current, so the extraction of $\tau$$_\mathrm{krk}$ needs to be carried out in the case of high current. And $\tau$$_\mathrm{c}$ plays a dominant role in the total delay time for the collector current $\textit{I}$$_\mathrm{c}$ is weak. $\tau$$_\mathrm{b}$ and some other non-critical parameters are obtained by fitting the curve of $\textit{F}$$_\mathrm{t}$ with the change of $\textit{I}$$_\mathrm{c}$. Comparisons of the measured and modeled results of cut-off frequency $\textit{F}$$_\mathrm{t}$ are shown in Fig. 10. Finally, the parameters extracted from the large-signal model proposed in this paper are shown in Tables 1 and 2.

##### Fig. 8. Measured and modeled $\textit{C}$$_\mathrm{BC}$ characteristics for (a) GaAs HBT, (b) InP HBT.

##### Fig. 9. Measured and modeled $\textit{C}$$_\mathrm{BE}$ characteristics for (a) GaAs HBT, (b) InP HBT.

##### Fig. 10. Measured and modeled $\textit{F}$$_\mathrm{t}$ characteristics for (a) GaAs HBT, (b) InP HBT.

##### Table 1 Extracted Values of Model Complete DC Parameters

##### Table 2 Extracted Values of Model Critical AC Parameters

## V. CONCLUSIONS

In this paper, a compact macromodeling method for characterizing the large-signal characteristics of heterojunction bipolar transistors (HBTs) devices is proposed by using the Symbolically-defined Device (SDD) technology. The proposed model discards the division of intrinsic and extrinsic parts in DC model and avoids the tedious establishment of the depletion charge model, which makes the parameter extraction process more convenient. And at the same time, it can maintain high fitting accuracy. This model has been successfully applied to describe the non-linear behaviors of the DC and AC characteristics of 1$\mu$m GaAs HBT and 1$\mu$m InP HBT devices. By comparing the modeled results of the proposed model with the measured results, the accuracy of the compact macromodeling method is verified.

## ACKNOWLEDGMENTS

This work was supported in National Defense Science and Technology Foundation Strengthening Program (Program No. 2019-XXXX-XX-236-00) and Key Research and Development Program of Shaanxi (Program No. 2021GY-010).

## References

Lin Cheng received the B.S. degree in Electrical Engineering College, Henan University of Science and Technology, Luoyang, China in 2020. His research is focused on modeling of HBTs and design of very high-speed integrated circuit.

Hongliang Lu was born in Tulufan, China, in 1978. She received the M.S. and Ph.D. degrees in microelec-tronics engineering from Xidian University, Xi’an, China, in 2003 and 2007, respectively. Since 2010, she has been a professor of the school of Microelectronics, Xidian University, Xi’an, China. Her work involves the modeling and experiments on SiC MESFET and other devices.

Yuming Zhang received the M.S. and Ph.D. degrees from Xidian university, Xi’an, China, and Xi’an Jiaotong University, Xi’an, in 1992 and 1998, respectively. Since 2001, he is Professor at the Microelectronics Institute, Xidian University. His research field is in the design, modeling, fabrication, and electrical characterization of SiC electronic devices for high-temperature and high-power operation.

Yimen Zhang is a Professor of the school of Microelectronics, Xidian University, Xi’an, China. He has been a Visiting Scholar and Senior Visiting Scholar at Arizona State University, Tempe, and Yale Univer-sity, New Haven, CT, respectively. His research interests are in the areas of wideband semiconductor devices, semiconductor devices modeling, TCAD for VLSI and quantum well devices.