Mobile QR Code QR CODE

  1. (Dept. of Electronic Engineering, Hanyang University, Seoul, Korea )

Oversampling ADC, noise-shaping, multi-bit/cycle SAR


Successive-approximation register (SAR) ADC has long been a favorable architecture in mid-resolution, low-power applications and quickly embraced modern nanoscale technologies owing to its mostly digital nature (1,2). Nevertheless, the power consumption drastically increases as the designer pushes the resolution of an SAR ADC above 9 or 10 bits, since the size of the capacitive DAC, and its switching power grows exponentially.

To overcome such difficulties in improving the resolution, noise-shaping (NS) SAR ADC was introduced with the goal of trading the bandwidth for resolution while maintaining good power efficiency (3). The cascade of integrators with feedforward (CIFF) structure employed in (3) required an active integrator to configure the NS filter, and the active integrator necessitated the use of power-hungry operational amplifiers, deteriorating the low-power advantage of SAR ADCs. (4) proposed error-feedback (EF) NS-SAR ADC to maintain low-power feature of the SAR ADC while suppressing the increase in power consumption by eliminating active integrators in the loop filter. Further research such as (5-7) have refined the EF structure to achieve lower power consumption and PVT-robustness.

There has been an attempt to reclaim the reduced bandwidth of NS-SAR ADC due to oversampling, by speeding up the SAR operation. One of the straightforward ways to boost the speed of an ADC is to time-interleave multiple ADCs (8,9). Usually, the speed of a time-interleaved-ADC (TI-ADC) can be improved by a factor proportional to the number of ADC channels. However, this is not the case for the TI-NS-ADCs, because the feedback signals need to be transferred between the ADC channels without violating the causality requirement. The timing overlap between the conversion periods of each channel ADC should be reduced due to this restriction (10). Therefore, the TI-NS-ADC cannot take full advantage of interleaving.

Multi-bit/cycle approach can be a useful alternative for speeding up the NS-SAR ADC. Multi-bit/cycle techniques accelerate the conversion of an ADC by reducing the number of cycles required for a conversion. A SAR ADC using a 2-bit/cycle scheme can achieve roughly twice the speed of those using a single-bit/cycle scheme (11,12).

This article proposes a NS-SAR ADC, which employs a 2-bit/cycle SAR ADC for high conversion rate. The proposed ADC employs the 2-bit/cycle SAR structure of (11). The noise-shaping is achieved using an EF structure, in which effective summation of the feedback signals and the input signal is performed by a multi-input residue amplifier and multi-input comparators. By SPICE-level simulations, we demonstrate the performance of the proposed design implemented in a 28-nm CMOS process. When operated with 1-V power supply, it achieves SNDR of 69.9 dB (ENOB = 11.3) with a bandwidth of 20 MHz. The power consumption was 4.1 mW, resulting in a Walden figure of merit (FoM) of 39.9 fJ/conversion-step.

The content of the article is as follows. Section II details the operation of the proposed ADC. In Section III, schematic level implementation of the proposed ADC is presented. Section IV provides SPICE-level simulation results and compares the performance of the proposed ADC with those in previous works. Finally, Section V concludes this article.



Fig. 1. EF noise-shaping structure with DAC for quantization error extraction.


A low-pass noise transfer function (NTF) could be realized without an integrator when a loop filter of the NS ADC is configured in an EF structure. Fig. 1 shows a signal-flow diagram of a NS ADC using an EF structure. Here, X represents the analog input of the NS-ADC, while Y and E represents the digital output and the quantization error of the quantizer, respectively. H(z) represents the finite impulse response (FIR) filter acting on the EF signal. The FIR filter can be implemented using switched capacitors, which is appealing since significant amount of power, area and design effort could be saved by eliminating active integrators. Yet, for a conventional delta-sigma ADC with flash quantizer, the EF structure is very much susceptible to errors associated with the extraction of the quantization error, which involves subtraction of the digital output from the quantizer input in the analog domain as shown in Fig. 1 (16). Fortunately, in a NS-SAR ADC, the quantization error can be conveniently extracted because the subtraction of the digital output is carried out by the capacitive DAC (C-DAC) of the SAR ADC itself (4).

Fig. 2. A simplified 1st-order version of the EF structure adopted in (5).


When the FIR filter is designed as a passive switched capacitor filter, the charge sharing between capacitors cause large signal attenuation, which limits the effectiveness of the NS. Therefore, especially for an NTF of an order higher than one, a gain stage is desired to compensate the attenuation. To illustrate this, we show in Fig. 2 a simplified schematic of the 1st-order EF structure of (5). Here, the residue E = Y – X is initially stored at $C_{DAC}$, which is the C-DAC of the SAR ADC. This residue is amplified by the residue amplifier RA with the gain of $A_{RES}$ and stored at $C_{FIR}$ of the FIR filter. Then, after the processing by the filter, which is a simple delay and charge redistribution between $C_{DAC}$ and $C_{FIR}$ in this case, the residue is fed back to the input. This can be expressed in z-domain as

$Y=\frac{C_{D M C}}{C_{D M C}+C_{F M R}} X+\left(1-\frac{A_{R E S} C_{F B R}}{C_{D M C}+C_{F I R}} z^{-1}\right) E$,

and the resulting 1st-order NTF is

$N T F(z)=1-\frac{A_{\text {RES }} C_{\text {FIR }}}{C_{D A C}+C_{F I R}} z^{-1}$

Fig. 3. Signal-flow model of the proposed structure.


We can observe that the NTF is determined by the parameter α ≡ $A_{RES}$$C_{FIR}$/($C_{DAC}$+$C_{FIR}$). To obtain the desired NTF, $A_{RES}$ and $C_{FIR}$/$C_{DAC}$ should be set properly. If $C_{FIR}$/$C_{DAC}$ is small, the $A_{RES}$ should be large, which could be problematic when the conversion speed of the NS-SAR ADC is of much concern, as designing a residue amplifier with high gain and high speed can become much more challenging than designing the ADC itself. On the other hand, $A_{RES}$ could be lowered by choosing a large $C_{FIR}$. However, this approach can be problematic, too, because a large $C_{FIR}$ not only hinders the fast operation of the amplifier but also attenuates severely the external analog input sampled at $C_{DAC}$ after charge sharing between $C_{FIR}$ and $C_{DAC}$.

Such difficulty brought by the charge sharing of $C_{FIR}$ and $C_{DAC}$ in the EF structure of (5) can be bypassed by isolating these capacitors using a multi-input preamplifier or a comparator. In (10), the residue stored on $C_{FIR}$ and the analog input sampled on $C_{DAC}$ are summed effectively by a multi-input preamplifier without resorting to charge sharing. As a result, the ratio between $C_{FIR}$ and $C_{DAC}$ no longer affects the NTF coefficients directly.

Fig. 3 shows the signal flow in the proposed 2nd order NS ADC structure using error feedback. Note that this model is focusing on the noise-shaping aspect of the ADC not showing the SAR ADC operation. The SAR ADC operates with the analog input X and error-feedback signals from FIR filter and produces digital output Y. The quantization error E is amplified by a multi-input RA and fed-back through a second order passive FIR. In (10), which also employs a similar EF structure, the RA also functions as a preamplifier to the comparator. In this work, however, RA was placed at the input of the FIR filter as shown in Fig. 3 and used for the amplification of the residue only. This is to prevent the RA output settling from affecting the settling of the comparator inputs and enables the ADC to operate in the maximum speed determined by the propagation delay of digital control logic.

The structure of the proposed ADC is presented in Fig. 4. It should be noted that the diagram is drawn in a single-ended form for convenience, whereas the actual circuit is built in differential scheme. The ADC utilizes two DACs, namely the reference DAC (REF-DAC) and the signal DAC (SIG-DAC). The REF-DAC serves as a reference voltage generator enabling the 2-bit/cycle SAR conversion, which generates $V_{REF}$/2, $V_{REF}$/8, $V_{REF}$/32, and $V_{REF}$/128, for the 1st, 2nd, 3rd and 4th comparisons respectively. Details of the 2-bit/cycle ADC operation will be covered in Section II-2. The SIG-DAC and REF-DAC are connected to three comparators which operates under the clock signal generated by an asynchronous clock generator. The asynchronous comparator-clock generator, which drives three single-stage StrongArm comparators, is constructed with four NAND gates as shown in Fig. 5. In, Fig. 5, Dcmpk represents the output of the k-th comparator. In the reset state, the comparators produce at both the positive and the negative outputs. This leads to $Φ_{cmp}$ = HIGH, which triggers the comparators to start comparison. When all the comparators have completed their decision, $Φ_{cmp}$ falls to LOW, resetting the comparators. This asynchronous loop repeats in a ring-oscillator-like manner until the comparator-clock-enable signal, EN, becomes LOW. EN is enabled (HIGH) when the input sampling clock $Φ_{s}$ goes down, and disabled ( ) when all the SAR cycles are finished.

The residue output of the SIG-DAC, and the prior ADC cycles’ feedback values $V_{EF1}$ and $V_{EF2}$ are summed and amplified by the residue amplifier RA and input to FIR filter. In this work, we used a residue amplifier operating in an in-complete settling mode. For a proper operation of this amplifier, we used switches at the input and output of the amplifier, which is controlled by control signals $Φ_{AMP}$ and $Φ_{AMP_EXT}$ The switches connect the input signal to the amplifier input only when $Φ_{AMP_EXT}$ = HIGH and output of the amplifier to the FIR filter input only when $Φ_{AMP}$ = HIGH. A detailed description of the amplifier will be presented in Sec. III.

Fig. 4. Block diagram of the proposed 2b/cycle NS SAR ADC.


Fig. 5. Asynchronous comparator clock generator.


Fig. 6. Schematic of the FIR filter to process the EF signal.


Fig. 6(a) shows the schematic of the FIR filter and Fig. 6(b) shows the timing diagram of the filter operation along with that of the SAR ADC. The analog input is sampled on the SIG-DAC by the sampling clock The fall of the triggers the asynchronous comparator clock loop and four SAR cycles are carried out. In each cycle, two bits are obtained from three comparators. After the SAR cycles are completed, with the residue remaining at SIG-DAC, the residue processing is executed, starting from the amplification set off by The differential output of RA is sampled by $C_{1}$ of FIR filter, and then passed through the network of capacitors and switches. It is noted that the common-mode of the FIR filter outputs $V_{EF1}$ and $V_{EF2}$ are fixed at VCM even when the common-mode of the input $V_{AMP}$ varies. This feature helps a proper operation of the multi-input comparators and residue amplifier. New $V_{EF1}$ and $V_{EF2}$ are produced during $Φ_{DEL_{2}}$ and $Φ_{DEL_{1}}$ respectively. Therefore, the falling edge of $Φ_{DEL_{2}}$ should occur before the falling edge of $Φ_{S}$ Therefore, the minimum conversion time of the NS-ADC is from the falling edge of $Φ_{S}$ to the falling edge of $Φ_{DEL_{2}}$ $C_{att}$ is used to calibrate the gain of the residue amplifier.

Fig. 7. Example of 8-bit resolution 2b/cycle SAR operation.

Red line: the sum of SIG-DAC output and two error-feedback signals, Black lines: reference voltages produced by REF-DAC.


The NTF of the proposed NS SAR ADC could be expressed as

$N T F(z)=1-b z^{-1}+a z^{-2}$,

where b = 2$A_{RES}$$C_{1}$/(2$C_{1}$+$C_{2}$) and a = $C_{2}$/($C_{2}$+$C_{3}$)b. In this work, $A_{RES}$ = 3.8 and 2$C_{1}$ = $C_{2}$ = $C_{3}$ = 256 fF are used, resulting in a = 1.9 and b = 0.95, which optimizes the NTF for the maximum SQNR (5).

2. 2b/cycle Operation of the NS SAR ADC

Fig. 7 shows the operation of the 2 bit/cycle SAR ADC used in this work. The red line represents the sum of the SIG-DAC output and two error-feedback signals. Note that this summed quantity does not appear explicitly on any node in the circuit. The summation is performed only virtually by multi-input comparators. The black lines represent the outputs of the REF-DAC, (+)$V_{REF-DAC}$ and (–)$V_{REF-DAC}$. The $V_{REF-DAC}$, which is independent of the comparison results, is $V_{REF}$/2 in the 1st comparison cycle, and is quartered every SAR cycle.

In each SAR cycle, three comparators compare the sum of SIG-DAC output and two EF signals with $V_{REF-DAC}$, zero, and –$V_{REF-DAC}$, respectively, to determine two output bits. After four SAR cycles are done and all the output codes determined, the SIG-DAC switches the LSB capacitor one more time according to the LSB conversion result to generate the valid residue voltage equivalent to the minus of the quantization error E, which is used in the noise-shaping process.

3. Effects of Non-idealities

Various non-idealities in the circuit degrade the performance of ADCs. In the proposed NS-ADC, the most important potential non-idealities are the RA gain variation, and the capacitor mismatches (5,10). The RA gain deviation shifts the NTF coefficients resulting in the increase of the in-band quantization noise. To investigate the effect, behavioral-level simulations were performed using MATLAB. Fig. 8 shows the effect of the RA gain variation on the SQNR when the gain deviates from the nominal value of $A_{RES}$ = 3.8. In Fig. 8, the rectangles and circles represent the results with and without incorporating thermal noise of various building blocks, respectively. (The noise contribution of the various building blocks will be discussed in Sec. IV). From Fig. 8, we observe that when the thermal noise is absent, the SNDR is degraded by about 8 dB at a gain mismatch of 10%. When the thermal noise is considered, the SNDR is degraded by 1.2 dB only at the same gain mismatch. Therefore, we can conclude that the SNDR performance of the ADC would not be very sensitive to the RA gain and that if we can control the RA gain variation below 10 %, it would not limit the performance of the ADC.

Next, we investigate the effect of capacitor mismatches. Fig. 9 shows the SNDR degradation from the capacitor mismatches obtained from behavioral-level Monte-Carlo simulations using MATLAB. The x-axis represents the standard deviation of the capacitance of the unit capacitors. Note that we use custom designed lateral metal-to-metal capacitors of 1 fF as unit capacitors in this work. The black rectangles represent the SNDR degradation from the mismatches of capacitors in the FIR filters. We can observe that the mismatches in the FIR filter does not degrade the performance up to 0.5 % of mismatch. It is because of the relatively large size of capacitors of the FIR filter which is dictated by the thermal noise requirement. The circles represent the degradation due to the mismatches of the capacitors in the C-DACs. The empty circles and solid circles represent the bottom 10 % and 1% SNDR out of 1000 Monte-Carlo iterations, respectively. For a power-efficient design, the noise should be dominated by the thermal noise. Therefore, for our design target of 70 dB of SNDR, it is desired that the SNDR of Fig. 9 should be larger than 75 dB. Therefore, we observe that mismatches smaller than 0.15 % is required, which is usually achievable by a careful layout.

Next, we investigated the effect of the comparator noise on the performance of the proposed ADC. We performed behavioral-level Monte-Carlo simulations where the comparator noise is the only non-ideality. Fig. 10 shows the SNDR as a function of the input referred noise of the comparators. We assumed that all three comparators have the same input-referred noise power. We can observe that when the noise is smaller than 1.5 mV, SNDR stays above 80 dB, and when the noise becomes larger, the SNDR drops very fast. Therefore, it is desired that the comparator noise is not larger than 1.5 mV.

Fig. 8. Effect of RA gain deviation from the nominal value of 3.8 on SNDR. Circles: without noise, rectangles: with noise.


Fig. 9. Effect of capacitor mismatch on SNDR from behavioral-level Monte-Carlo simulations (1000 runs for each mismatch). x-axis represents the standard deviation of capacitance of the 1-fF-sized unit capacitors (a) variation of capacitors in the FIR filter, (b) variation of the capacitors in the C-DACs.


Fig. 10. SNDR vs comparator input referred noise from behavioral level Monte Carlo simulations using MATLAB (1000 runs). The worst 1% SNDR is presented for each comparator noise.


Because our 2-bit/cycle structure uses three comparators, large comparator dc-offsets can degrade the performance of the ADC. Fig. 11 shows the results of the behavioral level Monte-Carlo simulations. We observe that the standard deviation of the dc offset should be smaller than 2 mV to make the offset-limited SNDR larger than 75 dB 99 % of the time. Because it requires very large transistors to reduce the offset to this level, we adopted a comparator structure with an auxiliary input pair used for offset calibration, which will be presented in Sec. III.

Fig. 11. Comparator offset versus SNDR from behavioral level Monte-Carlo simulations (1000 runs for each offset).


Fig. 12. Schematic of 5-input StrongArm latch comparator.



Fig. 12 shows the schematic of the comparators designed in StrongArm latch structure with five input pairs. Four out of the five input pairs are connected to the C-DACs and FIR filter outputs and one input pair is used for offset calibration. All five input pairs of the comparators have equal sizes, since all the inputs have the same weights. Transient noise simulations using Spectre confirm that the designed comparators have input referred noise of 1.5 mV$_{rms}$. This satisfies the requirements set in Sec. II. Although not implemented in this work, the comparator offset can be calibrated in a foreground calibration. In the calibration, multiple comparisons are made while shorting the 4 input pairs of the comparators. The input to the calibration pair, $V_{CAL+}$ and $V_{CAL-}$, are adjusted so that multiple comparisons result in equal number of positive and negative outputs.

Fig. 13. Schematic of 3-input residue amplifier.


Fig. 13(a) shows the structure of the switched-input/output RA used to amplify the residue voltage in this work. The amplifier output is connected to the sampling capacitor of the FIR filter through switches, which are closed during $Φ_{AMP_EXT }$ phases. The amplifier operates in incompletely-settling mode. Because of the incomplete-settling behavior, the amplifier needs to be reset before each amplification action. Therefore, the input signals are connected to the amplifier input through switches, SW_AMPs, which are shown in Fig. 13(b). The switches are closed during $Φ_{AMP_EXT }$_EXT, which is slightly longer than $Φ_{AMP_EXT }$ to avoid disturbing the operation of the amplifier near the end of amplification phases. When $Φ_{AMP_EXT }$= LOW, the RA input signals are connected to VCM for reset.

Fig. 13(c) shows the schematic of the core 3-input RA. The RA is implemented in a single-stage current-source load structure. NMOS cascode transistors were employed for fast settling and output resistance boosting. Because the RA is used only part of the time when $Φ_{AMP_EXT }$= HIGH, the use of a fully dynamic amplifier could potentially improve the power efficiency. However, to avoid the disturbance during fast turn-on interfering with multiple inputs, we employed a normal always-on amplifier.

Fig. 14. Capacitor attached at the input to mitigate kickback noise.


The RA operates almost like a Gm-C integrator, of which the gain can be approximated by $A_{RES}$ = G${_m}$T$_{int}$/C$_L$, where G${_m}$, T$_{int}$, and C$_L$ are the short-circuit transconductance of the RA, the integration time, and the load capacitance, respectively. As discussed in Sec. II.3, the ADC performance is not very sensitive to the RA gain variation. Nevertheless, $C_{ATT}$ is employed to calibrate the gain of the amplifier in a foreground calibration. Since the gain of the RA is inversely proportional to the load capacitance, $C_{ATT}$ can be adjusted to maximize the SNDR in a foreground calibration.

To mitigate the perturbation of error-feedback signals by the kickback from the amplifier, cross-coupling capacitors were attached between the gates of input MOSFETs and the drains of the opposite input MOSFETs in an input pair as shown in Fig. 14. The coupling capacitors were implemented as MOSCAPs, of which the width is one half of the input NMOS transistors.


The proposed 2-bit/cycle NS-SAR ADC was implemented in a 28-nm CMOS process. It operates at the sampling-rate of 320 MS/s with 1-V power supply. With OSR of 8, this corresponds to 20 MHz of bandwidth. Fig. 15 shows the waveforms of the various clock signals controlling the operation of the ADC. Roughly one half of the conversion time of 3.125 ns is used by SAR ADC and the other half is used by the residue amplification and processing. Note that for a proper operation of the ADC, DEL2 phase should finish before the completion of the input sampling. Fig. 15 shows that the designed circuit has about 0.51 ns of timing margin.

Fig. 15. Waveforms showing the timing of the ADC operation. CKS: sampling clock, CKC: comparator clock, AMP, RST1, DEL1, RST2, DEL2, RST2: FIR clocks (see Fig. 6).


Fig. 16. Output spectram of the proposed ADC from transient simulations ($N_{fft}$=4096, V$_p$=950 mV, $f_{sig}$=5.23 MHz). Solid line: transient noise simulation ($f_{max}$= 200 GHz), dots: without noise.


Fig. 16 shows the output spectrum of the ADC obtained from Spectre simulation. The blue solid and red dotted lines represent the spectra from simulations with and without noise, respectively. The vertical dashed line represents the bandwidth of 20 MHz. We can clearly observe the characteristic of the noise-shaping in both the spectra.

Fig. 17. Input amplitude versus SNDR. Rectangles: with transient noise ($f_{max}$=200 GHz), circles: without noise, $f_{sig}$=5.31 MHz.


Fig. 18. Input frequency versus SNDR from transient noise simulations ($f_{max}$ = 200 GHz). V$_p$ = 950 mV.


Fig. 17 shows the SNDR as functions of the input amplitude. When the noise not is included in the simulation (red circles), it achieved the maximum SNDR of 78.7 dB at $V_{pk,diff}$ = 900 mV. At larger input, the SNDR is reduced by the harmonic distortion which can be observed in the spectrum of Fig. 16 also. When the noise is included in the simulation, the maximum SNDR was 69.9 dB at $V_{pk,diff}$ = 950mV. The dynamic range is 70.3 dB and the SFDR is 78.1 dB.

Fig. 18 shows the SNDR from transient noise simulations measured at multiple frequencies. The SNDR is almost constant across the entire bandwidth of 20 MHz with less than 1 dB variation, which is from statistical variation rather than from real frequency-dependent performance.

Table 1. In-band noise Contribution

Noise Power (V2)

Percentage (%)




FIR Filter









Quantization Noise






Table 2. Power consumption

This Work


1.83 mW


0.67 mW

Comparator (+comparator clock)

0.98 mW

SAR logic

0.35 mW

Noise-shaping (FIR) filter (+clock)

0.25 mW


4.08 mW

Table 1 shows the contribution of various components to the input-referred noise of the ADC estimated by behavioral simulations using MATLAB. It is noted that the behavioral simulations predicted SNR of 71.9 dB with input with $V_{pk,diff}$ = 900 mV, which is very close to the value predicted by transient noise simulations of Spectre. From Table 1, we observe that the residue amplifier noise dominates the ADC noise. The input referred noise of the dynamic amplifier was modeled modifying the results of (16) and expressed as

$\sigma_{V, \text { in }}=\sqrt{4 k_{B} T \frac{g_{m, \text { tot }}}{g_{m, i n}^{2}} \frac{1}{2 T_{\text {int }}}}$

where $g_\text{m,in}$ is the transconductuance of a input nMOSFET and $g_\text{m,tot}$ is the sum of transconductance of all input nMOSFETs and the load pMOSFET. In our design, the use of multiple input-pairs increased the noise significantly.

When operated with the sampling rate of 320 MS/s and with 1-V supply voltage, the ADC dissipates 4.08 mW, where 1.83 mW, 0.98 mW, and 0.67 mW are consumed by the RA, the comparators, and the C-DACs, respectively. The power consumptions of the main building blocks are represented in Table 2.

The Walden FoM is 39.9 fJ/conv-step and the Schreier FoM is 166.8 dB. The performance of the proposed ADC is summarized and compared with relevant works in Table 3.

Table 3. Performance summary and comparison

This Work





Technology [nm]






Supply Voltage [V]






Power [mW]






Sampling Rate [MS/s]












Bandwidth [MHz]






NTF Order


















DR [dB]






FoMS [dB]






FoMW [fJ/conv-step]







This paper proposed a new approach to extend the bandwidth of the NS SAR ADC. By employing 2-bit/cycle SAR ADC along with accurate EF using FIR filter with a switched input/output amplifier, a significant improvement in SNDR performance was made possible.


This work was supported by the Korea Institute for Advancement of Technology (KIAT) grant funded by the Korea Government (MOTIE) (P0017011, HRD Program for Industrial Innovation). The CAD tools were provided by IC Design Center (IDEC), Korea.


Lim S., Woo Kim J., Yoon K., Lee S., Feb 2013, A 12-b Asynchronous SAR Type ADC for Bio Signal Detection, J. Semiconductor Technology and Science, Vol. 13, No. 2, pp. 108-113DOI
Kim B., Yan L., Yoo J., Yoo H.-J., Jan 2011, A 40fJ/c-s 1 V 10 bit SAR ADC with Dual Sampling Capacitive DAC Topology, J. Semiconductor Technology and Science, Vol. 11, No. 1, pp. 23-32DOI
Fredenburg J. A., Flynn M. P., Dec 2012, A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC, IEEE J. of Solid-State Circuits, Vol. 47, No. 12, pp. 2898-2904DOI
Chen Z., Miyahara M., Matsuzawa A., A 9.35-ENOB, 14.8 fJ/conv.-step fully-passive noise-shaping SAR ADC, Digest of 2015 Symp. on VLSI Circuits, pp. c64-C65DOI
Li S., Qiao B., Gandara M., Pan D. Z., Sun N., Dec 2018, A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure, IEEE J. of Solid-State Circuits, Vol. 53, No. 12, pp. 3484-3496DOI
Guo W., Zhuang H., Sun N., A 13b-ENOB 173dB-FoM 2nd-order NS SAR ADC with Passive Integrators, Digest of 2017 Symp. on VLSI Circuits 2017, pp. c236-C237DOI
Hwang Y., Song Y., Park J., Jeong D., A 0.6-to-1V 10k-to-100kHz BW 11.7b-ENOB Noise-Shaping SAR ADC for IoT sensor applications in 28-nm CMOS, Digest of 2018 IEEE Asian Solid-State Circuits Conf. (A-SSCC), pp. 247-248DOI
Park J.-S., An T.-J., Cho S.-H., Kim Y.-M., Ahn G.-C., Roh J.-H., Lee M.-K., Nah S.-P., Lee S.-H., Feb 2014, A 12b 100 MS/s Three-Step Hybrid Pipeline ADC Based on Time-Interleaved SAR ADCs, J. Semiconductor Technology and Science, Vol. 14, No. 2, pp. 189-197DOI
Chung H., Mar 2016, ADC-Based Backplane Receivers: Motivations, Issues and Future, J. Semiconductor Technology and Science, Vol. 16, No. 4, pp. 300-311DOI
Jie L., Zheng B., Flynn M. P., Dec 2019, A Calibration-Free Time-Interleaved Fourth-Order Noise-Shaping SAR ADC, IEEE Journal of Solid-State Circuits, Vol. 54, No. 12, pp. 3386-3395DOI
Hong H., Feb 2015, A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC, IEEE J. Solid-State Circuits, Vol. 50, No. 2, pp. 543-555DOI
Luo J., April 2020, A Low Voltage and Low Power 10-bit Non-Binary 2b/Cycle Time and Voltage Based SAR ADC, IEEE Trans. Circuits and Systems I: Regular Papers, Vol. 67, No. 4, pp. 1136-1148DOI
Liu C.-C., Huang Y.-T., Huang G.-Y., Chang S.-J., Huang C.-M., Huang C.-H., Automation and Test, A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-µm digital CMOS process, 2009 Inter. Symp. on VLSI Design, Automation and Test, pp. 215-218DOI
Li D., Zhu Z., Liu J., Zhuang H., Yang Y., Sun N., Nov 2020, A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration, IEEE J. of Solid-State Circuits, Vol. 55, No. 11, pp. 3051-3063DOI
Miyahara M., Asada Y., Paik D., Matsuzawa A., A low-noise self-calibrating dynamic comparator for high-speed ADCs, Digest of 2008 IEEE Asian Solid-State Circuits Conf. (A-SSCC), pp. 269-272DOI
van Elzakker M., van Tuijl E., Geraedts P., Schinkel D., Klumperink E. A. M., Nauta B., May 2010, A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s, IEEE J. Solid-State Circuits, Vol. 45, No. 5, pp. 1007-1015DOI


Jaehyeong Park

Jaehyeong Park received the B.S. and M.S. degrees in Electronics Engineering from Hanyang Univer-sity, Seoul, Korea, in 2019 and 2021, respectively.

His research focuses on analog/mixed-signal circuit design including data converters and wireline transceivers.

He is currently with the School of Electrical Engineering and Computer Science, Oregon State University, pursuing a Ph.D. degree.

Sang-Gyu Park

Sang-Gyu Park received B.S. and M.S. degrees in Electronics Engi-neering from Seoul National University in 1990 and 1992, respectively and received Ph.D. degree in Electrical and Computer Engineering from Purdue University in 1998.

He worked at AT&T Laboratories-Research from 1998 to 2000 and joined the faculty of Hanyang University in 2000, where he is a professor in Electronics and Computer Engineering.

His research area is the mixed-signal CMOS circuit design, with focus on delta-sigma oversampling data converters, high speed SAR ADCs and memory interface circuits.