ParkJaehyeong
ParkSangGyu

(Dept. of Electronic Engineering, Hanyang University, Seoul, Korea )
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Oversampling ADC, noiseshaping, multibit/cycle SAR
I. INTRODUCTION
Successiveapproximation register (SAR) ADC has long been a favorable architecture
in midresolution, lowpower applications and quickly embraced modern nanoscale technologies
owing to its mostly digital nature ^{(1,}^{2)}. Nevertheless, the power consumption drastically increases as the designer pushes
the resolution of an SAR ADC above 9 or 10 bits, since the size of the capacitive
DAC, and its switching power grows exponentially.
To overcome such difficulties in improving the resolution, noiseshaping (NS) SAR
ADC was introduced with the goal of trading the bandwidth for resolution while maintaining
good power efficiency ^{(3)}. The cascade of integrators with feedforward (CIFF) structure employed in ^{(3)} required an active integrator to configure the NS filter, and the active integrator
necessitated the use of powerhungry operational amplifiers, deteriorating the lowpower
advantage of SAR ADCs. ^{(4)} proposed errorfeedback (EF) NSSAR ADC to maintain lowpower feature of the SAR
ADC while suppressing the increase in power consumption by eliminating active integrators
in the loop filter. Further research such as ^{(5}^{7)} have refined the EF structure to achieve lower power consumption and PVTrobustness.
There has been an attempt to reclaim the reduced bandwidth of NSSAR ADC due to oversampling,
by speeding up the SAR operation. One of the straightforward ways to boost the speed
of an ADC is to timeinterleave multiple ADCs ^{(8,}^{9)}. Usually, the speed of a timeinterleavedADC (TIADC) can be improved by a factor
proportional to the number of ADC channels. However, this is not the case for the
TINSADCs, because the feedback signals need to be transferred between the ADC channels
without violating the causality requirement. The timing overlap between the conversion
periods of each channel ADC should be reduced due to this restriction ^{(10)}. Therefore, the TINSADC cannot take full advantage of interleaving.
Multibit/cycle approach can be a useful alternative for speeding up the NSSAR ADC.
Multibit/cycle techniques accelerate the conversion of an ADC by reducing the number
of cycles required for a conversion. A SAR ADC using a 2bit/cycle scheme can achieve
roughly twice the speed of those using a singlebit/cycle scheme ^{(11,}^{12)}.
This article proposes a NSSAR ADC, which employs a 2bit/cycle SAR ADC for high conversion
rate. The proposed ADC employs the 2bit/cycle SAR structure of ^{(11)}. The noiseshaping is achieved using an EF structure, in which effective summation
of the feedback signals and the input signal is performed by a multiinput residue
amplifier and multiinput comparators. By SPICElevel simulations, we demonstrate
the performance of the proposed design implemented in a 28nm CMOS process. When operated
with 1V power supply, it achieves SNDR of 69.9 dB (ENOB = 11.3) with a bandwidth
of 20 MHz. The power consumption was 4.1 mW, resulting in a Walden figure of merit
(FoM) of 39.9 fJ/conversionstep.
The content of the article is as follows. Section II details the operation of the
proposed ADC. In Section III, schematic level implementation of the proposed ADC is
presented. Section IV provides SPICElevel simulation results and compares the performance
of the proposed ADC with those in previous works. Finally, Section V concludes this
article.
II. PROPOSED 2B/CYCLENSSAR ADC
1. EFNS SAR
Fig. 1. EF noiseshaping structure with DAC for quantization error extraction.
A lowpass noise transfer function (NTF) could be realized without an integrator when
a loop filter of the NS ADC is configured in an EF structure. Fig. 1 shows a signalflow diagram of a NS ADC using an EF structure. Here, X represents
the analog input of the NSADC, while Y and E represents the digital output and the
quantization error of the quantizer, respectively. H(z) represents the finite impulse
response (FIR) filter acting on the EF signal. The FIR filter can be implemented using
switched capacitors, which is appealing since significant amount of power, area and
design effort could be saved by eliminating active integrators. Yet, for a conventional
deltasigma ADC with flash quantizer, the EF structure is very much susceptible to
errors associated with the extraction of the quantization error, which involves subtraction
of the digital output from the quantizer input in the analog domain as shown in Fig. 1 ^{(16)}. Fortunately, in a NSSAR ADC, the quantization error can be conveniently extracted
because the subtraction of the digital output is carried out by the capacitive DAC
(CDAC) of the SAR ADC itself ^{(4)}.
Fig. 2. A simplified 1storder version of the EF structure adopted in ^{(5)}.
When the FIR filter is designed as a passive switched capacitor filter, the charge
sharing between capacitors cause large signal attenuation, which limits the effectiveness
of the NS. Therefore, especially for an NTF of an order higher than one, a gain stage
is desired to compensate the attenuation. To illustrate this, we show in Fig. 2 a simplified schematic of the 1storder EF structure of ^{(5)}. Here, the residue E = Y – X is initially stored at $C_{DAC}$, which is the CDAC
of the SAR ADC. This residue is amplified by the residue amplifier RA with the gain
of $A_{RES}$ and stored at $C_{FIR}$ of the FIR filter. Then, after the processing
by the filter, which is a simple delay and charge redistribution between $C_{DAC}$
and $C_{FIR}$ in this case, the residue is fed back to the input. This can be expressed
in zdomain as
and the resulting 1storder NTF is
Fig. 3. Signalflow model of the proposed structure.
We can observe that the NTF is determined by the parameter α ≡ $A_{RES}$$C_{FIR}$/($C_{DAC}$+$C_{FIR}$).
To obtain the desired NTF, $A_{RES}$ and $C_{FIR}$/$C_{DAC}$ should be set properly.
If $C_{FIR}$/$C_{DAC}$ is small, the $A_{RES}$ should be large, which could be problematic
when the conversion speed of the NSSAR ADC is of much concern, as designing a residue
amplifier with high gain and high speed can become much more challenging than designing
the ADC itself. On the other hand, $A_{RES}$ could be lowered by choosing a large
$C_{FIR}$. However, this approach can be problematic, too, because a large $C_{FIR}$
not only hinders the fast operation of the amplifier but also attenuates severely
the external analog input sampled at $C_{DAC}$ after charge sharing between $C_{FIR}$
and $C_{DAC}$.
Such difficulty brought by the charge sharing of $C_{FIR}$ and $C_{DAC}$ in the EF
structure of ^{(5)} can be bypassed by isolating these capacitors using a multiinput preamplifier or
a comparator. In ^{(10)}, the residue stored on $C_{FIR}$ and the analog input sampled on $C_{DAC}$ are summed
effectively by a multiinput preamplifier without resorting to charge sharing. As
a result, the ratio between $C_{FIR}$ and $C_{DAC}$ no longer affects the NTF coefficients
directly.
Fig. 3 shows the signal flow in the proposed 2nd order NS ADC structure using error feedback.
Note that this model is focusing on the noiseshaping aspect of the ADC not showing
the SAR ADC operation. The SAR ADC operates with the analog input X and errorfeedback
signals from FIR filter and produces digital output Y. The quantization error E is
amplified by a multiinput RA and fedback through a second order passive FIR. In
^{(10)}, which also employs a similar EF structure, the RA also functions as a preamplifier
to the comparator. In this work, however, RA was placed at the input of the FIR filter
as shown in Fig. 3 and used for the amplification of the residue only. This is to prevent the RA output
settling from affecting the settling of the comparator inputs and enables the ADC
to operate in the maximum speed determined by the propagation delay of digital control
logic.
The structure of the proposed ADC is presented in Fig. 4. It should be noted that the diagram is drawn in a singleended form for convenience,
whereas the actual circuit is built in differential scheme. The ADC utilizes two DACs,
namely the reference DAC (REFDAC) and the signal DAC (SIGDAC). The REFDAC serves
as a reference voltage generator enabling the 2bit/cycle SAR conversion, which generates
$V_{REF}$/2, $V_{REF}$/8, $V_{REF}$/32, and $V_{REF}$/128, for the 1st, 2nd, 3rd and
4th comparisons respectively. Details of the 2bit/cycle ADC operation will be covered
in Section II2. The SIGDAC and REFDAC are connected to three comparators which
operates under the clock signal generated by an asynchronous clock generator.
The asynchronous comparatorclock generator, which drives three singlestage StrongArm
comparators, is constructed with four NAND gates as shown in Fig. 5. In, Fig. 5, Dcmpk represents the output of the kth comparator. In the reset state, the comparators
produce at both the positive and the negative outputs. This leads to $Φ_{cmp}$ =
HIGH, which triggers the comparators to start comparison. When all the comparators
have completed their decision, $Φ_{cmp}$ falls to LOW, resetting the comparators.
This asynchronous loop repeats in a ringoscillatorlike manner until the comparatorclockenable
signal, EN, becomes LOW. EN is enabled (HIGH) when the input sampling clock $Φ_{s}$
goes down, and disabled ( ) when all the SAR cycles are finished.
The residue output of the SIGDAC, and the prior ADC cycles’ feedback values $V_{EF1}$
and $V_{EF2}$ are summed and amplified by the residue amplifier RA and input to FIR
filter. In this work, we used a residue amplifier operating in an incomplete settling
mode. For a proper operation of this amplifier, we used switches at the input and
output of the amplifier, which is controlled by control signals $Φ_{AMP}$ and $Φ_{AMP_EXT}$
The switches connect the input signal to the amplifier input only when $Φ_{AMP_EXT}$
= HIGH and output of the amplifier to the FIR filter input only when $Φ_{AMP}$ = HIGH.
A detailed description of the amplifier will be presented in Sec. III.
Fig. 4. Block diagram of the proposed 2b/cycle NS SAR ADC.
Fig. 5. Asynchronous comparator clock generator.
Fig. 6. Schematic of the FIR filter to process the EF signal.
Fig. 6(a) shows the schematic of the FIR filter and Fig. 6(b) shows the timing diagram of the filter operation along with that of the SAR ADC.
The analog input is sampled on the SIGDAC by the sampling clock The fall of the
triggers the asynchronous comparator clock loop and four SAR cycles are carried out.
In each cycle, two bits are obtained from three comparators. After the SAR cycles
are completed, with the residue remaining at SIGDAC, the residue processing is executed,
starting from the amplification set off by The differential output of RA is sampled
by $C_{1}$ of FIR filter, and then passed through the network of capacitors and switches.
It is noted that the commonmode of the FIR filter outputs $V_{EF1}$ and $V_{EF2}$
are fixed at VCM even when the commonmode of the input $V_{AMP}$ varies. This feature
helps a proper operation of the multiinput comparators and residue amplifier. New
$V_{EF1}$ and $V_{EF2}$ are produced during $Φ_{DEL_{2}}$ and $Φ_{DEL_{1}}$ respectively.
Therefore, the falling edge of $Φ_{DEL_{2}}$ should occur before the falling edge
of $Φ_{S}$ Therefore, the minimum conversion time of the NSADC is from the falling
edge of $Φ_{S}$ to the falling edge of $Φ_{DEL_{2}}$ $C_{att}$ is used to calibrate
the gain of the residue amplifier.
Fig. 7. Example of 8bit resolution 2b/cycle SAR operation.
Red line: the sum of SIGDAC output and two errorfeedback signals, Black lines: reference
voltages produced by REFDAC.
The NTF of the proposed NS SAR ADC could be expressed as
where b = 2$A_{RES}$$C_{1}$/(2$C_{1}$+$C_{2}$) and a = $C_{2}$/($C_{2}$+$C_{3}$)b.
In this work, $A_{RES}$ = 3.8 and 2$C_{1}$ = $C_{2}$ = $C_{3}$ = 256 fF are used,
resulting in a = 1.9 and b = 0.95, which optimizes the NTF for the maximum SQNR ^{(5)}.
2. 2b/cycle Operation of the NS SAR ADC
Fig. 7 shows the operation of the 2 bit/cycle SAR ADC used in this work. The red line represents
the sum of the SIGDAC output and two errorfeedback signals. Note that this summed
quantity does not appear explicitly on any node in the circuit. The summation is performed
only virtually by multiinput comparators. The black lines represent the outputs of
the REFDAC, (+)$V_{REFDAC}$ and (–)$V_{REFDAC}$. The $V_{REFDAC}$, which is independent
of the comparison results, is $V_{REF}$/2 in the 1st comparison cycle, and is quartered
every SAR cycle.
In each SAR cycle, three comparators compare the sum of SIGDAC output and two EF
signals with $V_{REFDAC}$, zero, and –$V_{REFDAC}$, respectively, to determine two
output bits. After four SAR cycles are done and all the output codes determined, the
SIGDAC switches the LSB capacitor one more time according to the LSB conversion result
to generate the valid residue voltage equivalent to the minus of the quantization
error E, which is used in the noiseshaping process.
3. Effects of Nonidealities
Various nonidealities in the circuit degrade the performance of ADCs. In the proposed
NSADC, the most important potential nonidealities are the RA gain variation, and
the capacitor mismatches ^{(5,}^{10)}. The RA gain deviation shifts the NTF coefficients resulting in the increase of the
inband quantization noise. To investigate the effect, behaviorallevel simulations
were performed using MATLAB. Fig. 8 shows the effect of the RA gain variation on the SQNR when the gain deviates from
the nominal value of $A_{RES}$ = 3.8. In Fig. 8, the rectangles and circles represent the results with and without incorporating
thermal noise of various building blocks, respectively. (The noise contribution of
the various building blocks will be discussed in Sec. IV). From Fig. 8, we observe that when the thermal noise is absent, the SNDR is degraded by about
8 dB at a gain mismatch of 10%. When the thermal noise is considered, the SNDR is
degraded by 1.2 dB only at the same gain mismatch. Therefore, we can conclude that
the SNDR performance of the ADC would not be very sensitive to the RA gain and that
if we can control the RA gain variation below 10 %, it would not limit the performance
of the ADC.
Next, we investigate the effect of capacitor mismatches. Fig. 9 shows the SNDR degradation from the capacitor mismatches obtained from behaviorallevel
MonteCarlo simulations using MATLAB. The xaxis represents the standard deviation
of the capacitance of the unit capacitors. Note that we use custom designed lateral
metaltometal capacitors of 1 fF as unit capacitors in this work. The black rectangles
represent the SNDR degradation from the mismatches of capacitors in the FIR filters.
We can observe that the mismatches in the FIR filter does not degrade the performance
up to 0.5 % of mismatch. It is because of the relatively large size of capacitors
of the FIR filter which is dictated by the thermal noise requirement. The circles
represent the degradation due to the mismatches of the capacitors in the CDACs. The
empty circles and solid circles represent the bottom 10 % and 1% SNDR out of 1000
MonteCarlo iterations, respectively. For a powerefficient design, the noise should
be dominated by the thermal noise. Therefore, for our design target of 70 dB of SNDR,
it is desired that the SNDR of Fig. 9 should be larger than 75 dB. Therefore, we observe that mismatches smaller than 0.15
% is required, which is usually achievable by a careful layout.
Next, we investigated the effect of the comparator noise on the performance of the
proposed ADC. We performed behaviorallevel MonteCarlo simulations where the comparator
noise is the only nonideality. Fig. 10 shows the SNDR as a function of the input referred noise of the comparators. We assumed
that all three comparators have the same inputreferred noise power. We can observe
that when the noise is smaller than 1.5 mV, SNDR stays above 80 dB, and when the noise
becomes larger, the SNDR drops very fast. Therefore, it is desired that the comparator
noise is not larger than 1.5 mV.
Fig. 8. Effect of RA gain deviation from the nominal value of 3.8 on SNDR. Circles:
without noise, rectangles: with noise.
Fig. 9. Effect of capacitor mismatch on SNDR from behaviorallevel MonteCarlo simulations
(1000 runs for each mismatch). xaxis represents the standard deviation of capacitance
of the 1fFsized unit capacitors (a) variation of capacitors in the FIR filter, (b)
variation of the capacitors in the CDACs.
Fig. 10. SNDR vs comparator input referred noise from behavioral level Monte Carlo
simulations using MATLAB (1000 runs). The worst 1% SNDR is presented for each comparator
noise.
Because our 2bit/cycle structure uses three comparators, large comparator dcoffsets
can degrade the performance of the ADC. Fig. 11 shows the results of the behavioral level MonteCarlo simulations. We observe that
the standard deviation of the dc offset should be smaller than 2 mV to make the offsetlimited
SNDR larger than 75 dB 99 % of the time. Because it requires very large transistors
to reduce the offset to this level, we adopted a comparator structure with an auxiliary
input pair used for offset calibration, which will be presented in Sec. III.
Fig. 11. Comparator offset versus SNDR from behavioral level MonteCarlo simulations
(1000 runs for each offset).
Fig. 12. Schematic of 5input StrongArm latch comparator.
III. CIRCUIT DESCRIPTION
Fig. 12 shows the schematic of the comparators designed in StrongArm latch structure with
five input pairs. Four out of the five input pairs are connected to the CDACs and
FIR filter outputs and one input pair is used for offset calibration. All five input
pairs of the comparators have equal sizes, since all the inputs have the same weights.
Transient noise simulations using Spectre confirm that the designed comparators have
input referred noise of 1.5 mV$_{rms}$. This satisfies the requirements set in Sec.
II. Although not implemented in this work, the comparator offset can be calibrated
in a foreground calibration. In the calibration, multiple comparisons are made while
shorting the 4 input pairs of the comparators. The input to the calibration pair,
$V_{CAL+}$ and $V_{CAL}$, are adjusted so that multiple comparisons result in equal
number of positive and negative outputs.
Fig. 13. Schematic of 3input residue amplifier.
Fig. 13(a) shows the structure of the switchedinput/output RA used to amplify the residue voltage
in this work. The amplifier output is connected to the sampling capacitor of the FIR
filter through switches, which are closed during $Φ_{AMP_EXT }$ phases. The amplifier
operates in incompletelysettling mode. Because of the incompletesettling behavior,
the amplifier needs to be reset before each amplification action. Therefore, the input
signals are connected to the amplifier input through switches, SW_AMPs, which are
shown in Fig. 13(b). The switches are closed during $Φ_{AMP_EXT }$_EXT, which is slightly longer than
$Φ_{AMP_EXT }$ to avoid disturbing the operation of the amplifier near the end of
amplification phases. When $Φ_{AMP_EXT }$= LOW, the RA input signals are connected
to VCM for reset.
Fig. 13(c) shows the schematic of the core 3input RA. The RA is implemented in a singlestage
currentsource load structure. NMOS cascode transistors were employed for fast settling
and output resistance boosting. Because the RA is used only part of the time when
$Φ_{AMP_EXT }$= HIGH, the use of a fully dynamic amplifier could potentially improve
the power efficiency. However, to avoid the disturbance during fast turnon interfering
with multiple inputs, we employed a normal alwayson amplifier.
Fig. 14. Capacitor attached at the input to mitigate kickback noise.
The RA operates almost like a GmC integrator, of which the gain can be approximated
by $A_{RES}$ = G${_m}$T$_{int}$/C$_L$, where G${_m}$, T$_{int}$, and C$_L$ are the
shortcircuit transconductance of the RA, the integration time, and the load capacitance,
respectively. As discussed in Sec. II.3, the ADC performance is not very sensitive
to the RA gain variation. Nevertheless, $C_{ATT}$ is employed to calibrate the gain
of the amplifier in a foreground calibration. Since the gain of the RA is inversely
proportional to the load capacitance, $C_{ATT}$ can be adjusted to maximize the SNDR
in a foreground calibration.
To mitigate the perturbation of errorfeedback signals by the kickback from the amplifier,
crosscoupling capacitors were attached between the gates of input MOSFETs and the
drains of the opposite input MOSFETs in an input pair as shown in Fig. 14. The coupling capacitors were implemented as MOSCAPs, of which the width is one half
of the input NMOS transistors.
IV. SIMULATION RESULTS
The proposed 2bit/cycle NSSAR ADC was implemented in a 28nm CMOS process. It operates
at the samplingrate of 320 MS/s with 1V power supply. With OSR of 8, this corresponds
to 20 MHz of bandwidth. Fig. 15 shows the waveforms of the various clock signals controlling the operation of the
ADC. Roughly one half of the conversion time of 3.125 ns is used by SAR ADC and the
other half is used by the residue amplification and processing. Note that for a proper
operation of the ADC, DEL2 phase should finish before the completion of the input
sampling. Fig. 15 shows that the designed circuit has about 0.51 ns of timing margin.
Fig. 15. Waveforms showing the timing of the ADC operation. CKS: sampling clock, CKC:
comparator clock, AMP, RST1, DEL1, RST2, DEL2, RST2: FIR clocks (see Fig. 6).
Fig. 16. Output spectram of the proposed ADC from transient simulations ($N_{fft}$=4096,
V$_p$=950 mV, $f_{sig}$=5.23 MHz). Solid line: transient noise simulation ($f_{max}$=
200 GHz), dots: without noise.
Fig. 16 shows the output spectrum of the ADC obtained from Spectre simulation. The blue solid
and red dotted lines represent the spectra from simulations with and without noise,
respectively. The vertical dashed line represents the bandwidth of 20 MHz. We can
clearly observe the characteristic of the noiseshaping in both the spectra.
Fig. 17. Input amplitude versus SNDR. Rectangles: with transient noise ($f_{max}$=200
GHz), circles: without noise, $f_{sig}$=5.31 MHz.
Fig. 18. Input frequency versus SNDR from transient noise simulations ($f_{max}$ =
200 GHz). V$_p$ = 950 mV.
Fig. 17 shows the SNDR as functions of the input amplitude. When the noise not is included
in the simulation (red circles), it achieved the maximum SNDR of 78.7 dB at $V_{pk,diff}$
= 900 mV. At larger input, the SNDR is reduced by the harmonic distortion which can
be observed in the spectrum of Fig. 16 also. When the noise is included in the simulation, the maximum SNDR was 69.9 dB
at $V_{pk,diff}$ = 950mV. The dynamic range is 70.3 dB and the SFDR is 78.1 dB.
Fig. 18 shows the SNDR from transient noise simulations measured at multiple frequencies.
The SNDR is almost constant across the entire bandwidth of 20 MHz with less than 1
dB variation, which is from statistical variation rather than from real frequencydependent
performance.
Table 1. Inband noise Contribution

Noise Power (V2)

Percentage (%)

Amplifier

22.0x109

74.3

FIR Filter

3.8x109

12.8

CDACs

1.8x109

6.1

Comparators

0.6x109

2.0

Quantization Noise

1.4x109

4.7

Total

29.6x109

100

Table 2. Power consumption

This Work

Amplifier

1.83 mW

CDACs

0.67 mW

Comparator (+comparator clock)

0.98 mW

SAR logic

0.35 mW

Noiseshaping (FIR) filter (+clock)

0.25 mW

Total

4.08 mW

Table 1 shows the contribution of various components to the inputreferred noise of the ADC
estimated by behavioral simulations using MATLAB. It is noted that the behavioral
simulations predicted SNR of 71.9 dB with input with $V_{pk,diff}$ = 900 mV, which
is very close to the value predicted by transient noise simulations of Spectre. From
Table 1, we observe that the residue amplifier noise dominates the ADC noise. The input referred
noise of the dynamic amplifier was modeled modifying the results of ^{(16)} and expressed as
where $g_\text{m,in}$ is the transconductuance of a input nMOSFET and $g_\text{m,tot}$
is the sum of transconductance of all input nMOSFETs and the load pMOSFET. In our
design, the use of multiple inputpairs increased the noise significantly.
When operated with the sampling rate of 320 MS/s and with 1V supply voltage, the
ADC dissipates 4.08 mW, where 1.83 mW, 0.98 mW, and 0.67 mW are consumed by the RA,
the comparators, and the CDACs, respectively. The power consumptions of the main
building blocks are represented in Table 2.
The Walden FoM is 39.9 fJ/convstep and the Schreier FoM is 166.8 dB. The performance
of the proposed ADC is summarized and compared with relevant works in Table 3.
Table 3. Performance summary and comparison

This Work

[3]

[4]

[5]

[10]

Technology [nm]

28

65

65

40

40

Supply Voltage [V]

1

1.2

0.8

1.1

1

Power [mW]

4.08

0.806

0.121

0.084

13

Sampling Rate [MS/s]

320

90

50

10

400

OSR

8

4

4

8

4

Bandwidth [MHz]

20

11

6.25

0.625

50

NTF Order

2

1

1

2

4

SNDR [dB]

69.9

62.14

58.03

79

70.4

SFDR [dB]

78.1

72.46



89

88

DR [dB]

70.3





80.5

71.7

FoMS [dB]

166.8

163.5

165.2

178

166.3

FoMW [fJ/convstep]

39.9

35.8

14.8

9

48.1

IV. CONCLUSIONS
This paper proposed a new approach to extend the bandwidth of the NS SAR ADC. By employing
2bit/cycle SAR ADC along with accurate EF using FIR filter with a switched input/output
amplifier, a significant improvement in SNDR performance was made possible.
ACKNOWLEDGMENTS
This work was supported by the Korea Institute for Advancement of Technology (KIAT)
grant funded by the Korea Government (MOTIE) (P0017011, HRD Program for Industrial
Innovation). The CAD tools were provided by IC Design Center (IDEC), Korea.
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Author
Jaehyeong Park received the B.S. and M.S. degrees in Electronics Engineering from
Hanyang University, Seoul, Korea, in 2019 and 2021, respectively.
His research focuses on analog/mixedsignal circuit design including data converters
and wireline transceivers.
He is currently with the School of Electrical Engineering and Computer Science, Oregon
State University, pursuing a Ph.D. degree.
SangGyu Park received B.S. and M.S. degrees in Electronics Engineering from Seoul
National University in 1990 and 1992, respectively and received Ph.D. degree in Electrical
and Computer Engineering from Purdue University in 1998.
He worked at AT&T LaboratoriesResearch from 1998 to 2000 and joined the faculty of
Hanyang University in 2000, where he is a professor in Electronics and Computer Engineering.
His research area is the mixedsignal CMOS circuit design, with focus on deltasigma
oversampling data converters, high speed SAR ADCs and memory interface circuits.