I. INTRODUCTION
Recently, the reference clock doublers have widespread use in integrated circuits.
They are used at the phase locked loop (PLL) input, with UARTs to achieve higher baud
rate and useful in a clock distribution network (1,2). As data rates have increased, the operating frequency of many circuits has also
increased. In particular, the operating frequency of the analog-to-digital or PLL
is determined by the reference clock, and a frequency doubler is used to increase
the clock frequency. This reduces overall cost of the system and time to market.
The conventional low-power reference clock doubler architecture generates a reference
clock signal and a delayed reference clock signal through an Exclusive-OR (XOR) gate
as shown in Fig. 1(a).
Fig. 1(b) and (c) show the XOR output when the input is 50 % duty and not 50 % duty respectively.
As shown in Fig. 1(c), if not 50 % duty, XOR output have a large cycle-to-cycle jitter with double frequency.
The amount of cycle-to-cycle jitter increases proportionally to the duty of the input.
Previous clock doublers have a problem that if the input signal does not have 50 %
duty, the jitter characteristic of the reference clock in the PLL is bad and directly
affects the phase noise. In the Previous duty-cycle error correction controller (DCC),
capacitors are used to sense the duty. The capacitor has a large area and the current
consumption is large for the operation of the analog circuit.
Section II shows the architecture of this work. Section III shows the circuit description.
Section IV and V show the measurement results and conclusion.
Fig. 1. (a) Block diagram of conventional clock doubler, (b) Duty cycle of the input
is 50 %, (c) Duty cycle of the input non 50 %.
II. ARCHITECTURE
Fig. 2. Block diagram of proposed reference clock doubler.
Fig. 2 shows the block diagram of proposed clock frequency doubler. The duty-cycle error
correction controller is added to the conventional reference clock doubler to eliminate
the non-50 % duty cycle input. The DCC block is a digital method that uses time to
digital converter (TDC) to measure duty error and compensate for delay using delay
cell. It has smaller area and lower current consumption than analog method [3].
III. CIRCUIT DESCRIPTION
Fig. 3 shows the block diagram of automatic DCC. It is composed of several logical gates,
TDC, 2-step delay array and controller to correct duty cycle error. If the high duty
is initially greater than the low duty, use inverter to always make the high duty
smaller, making the controller simpler. The high duty can be increased as the block
is delayed through the delay array and OR gate of the DCC. The high duty and low duty
are measured with TDC to control the delay array at the controller so that the high
duty and low duty are the same. At the end of all DCC processes, the clock with 50
% duty is output from f1.
Fig. 3. Block diagram of automatic DCC.
Fig. 4. Block diagram of 2-step delay array in DCC.
1. Delay Array of DCC
Fig. 4 shows the block diagram of two-step delay array in DCC. Delay array consists of MUX,
coarse delay cell, and fine delay cell. Delay array can be adjusted the delay by selecting
the number of coarse delay cells with DELAYCOARSE<2:0> and selecting the number of
fine delay cells with DELAYFINE<3:0>. The resolution of the delay array is smaller
than the resolution of the TDC. The smaller the resolution of the delay array, the
duty can be adjusted finely, making it closer to the 50 % duty.
2. Time to Digital Converter
Fig. 5 shows the block diagram of TDC. It consists of a delay cell that can be delayed from
0 to 20 ns, a buffer with 100 ps delay, and a D-flip flop(DFF) and an inverter. Delay
the pulse using the delay cell so that the pulse edge is within the measurable TDC
range of 2ns and measure the pulse width through TDC_OUT<19:0>. If a non-inverter
clock enters the DFF's clock input, high duty can be measured, and low duty can be
measured when an inverted clock comes in. The smaller the TDC resolution, the more
sensitive the pulse duty can be measured, enabling calibration closer to 50 % duty.
Since both buffers and DFFs are composed of digital blocks, adding the number of buffers
and DFFs has the advantage of more accurate calibration simply. This paper is designed
to be optimized for PLL applications using 64 MHz as a reference clock, but if more
control bits are used in the Delay Array, it can be used in a wide frequency range.
Fig. 5. Block diagram of TDC.
Fig. 6. Flowchart of automatic DCC
3. Mechanism of DCC
Fig. 6 shows the flow chart of automatic DCC. Initially, if the high duty rate is greater
than 50 %, enter INIT_POL=0. INIT_POL=0 opens the switch and allows the clock to pass
through the inverter so that the unconditionally high duty rate is less than 50 %.
The TDC's internal delay cell is then adjusted so that the pulse edge is within the
TDC range of 2 ns. Using TDC to measure high pulse duty and low pulse duty, and if
the measured high duty and low duty are different, increase the high duty by increasing
the delay of the delay array and compare the high duty and low duty of the pulse again.
Repeat the above process until High Duty and Low Duty are the same. Since High Duty
and Low Duty are the same, even if the delay is changed due to a change in the supply
voltage or temperature, it is compensated so that the duty is always 50%.
Fig. 7 shows the timing diagram of the automatic DCC. Measure and compare the high duty
and low duty of the fOR node signal that is the input of the TDC. If the high duty
is smaller, increase the delay of the Delay Array to increase the high duty, and then
repeat the comparison process again. If the high duty and the low duty are the same,
finish this process and save and use the delay at that time.
Fig. 7. Timing diagram of automatic DCC.
Fig. 8. Block diagram of delay cell in reference clock doubler
4. Delay Cell
Fig. 8 shows the Block Diagram of Delay cell in reference block doubler. This delay cell
and XOR gate produce double the frequency. High duty is determined as much as it is
delayed, and most digital blocks operate only on pulse edge, so can adjust it roughly.
IV. MEASUREMENT RESULTS
Fig. 9 shows the microphotograph of the proposed reference clock doubler. It is implemented
using 55 nm CMOS technology. Fig. 10 show measurement result input and output of DCC and jitter analysis at 64 MHz output
clock. Even if the duty-cycle error is 5 %, the error of the duty-cycle decreases
to 0.5 % after passing DCC. A comparison between the proposed reference clock doubler
and previous publications is shown in Table 1. This work has a power consumption of 30 µW and an area of 0.0064 mm${^2}$.
Table 1. Performance summary (measurements)
|
|
[4]
|
[5]
|
[6]
|
[7]
|
This Work
|
|
Technology (nm)
|
130
|
130
|
350
|
55
|
55
|
|
Clock Frequency (MHz)
|
312.5 ~ 1000
|
350~1000
|
1~50
|
333~1000
|
32
|
|
Duty Correction Extent (%)
|
40 ~ 60
|
10 ~ 90
|
-
|
20 ~ 80
|
20 ~ 80
|
|
Power Consumption (mW)
|
3.2
|
5.6
|
3
|
1.25
|
0.03
|
|
Chip Area (mm${^2}$)
|
0.048
|
0.059
|
0.0036
|
0.0186
|
0.0064
|
Fig. 9. Microphotograph of proposed reference clock doubler.
Fig. 10. Measurement results input and output of DCC.
V. CONCLUSIONS
The proposed reference clock doubler has less power consumption and smaller area due
to its fully digital DCC structure than other structures using Conventional analog
DCC. By using DCC that automatically compensate for the duty, they always have 50
% duty and thus have improved jitter characteristics. It has an area of 0.0064 mm${^2}$
and a power consumption of 30 µW.
ACKNOWLEDGMENTS
This research was supported by National R&D Program through the National Research
Foundation of Korea(NRF) funded by Ministry of Science and ICT(No. 2020M3H2A1076786).
REFERENCES
Reuben John, 2012, Clock frequency doubler circuit for multiple frequencies and its
application in a CDN to reduce power, International Conference on Computing, Electronics
and Electrical Technologies, pp. 752-756
Hsueh Yu-Li, 2014, A 0.29 mm${^2}$ Frequency Synthesizer in 40nm CMOS with 0.19psrms
Jitter and <-100dBc Reference Spur for 802.11ac, IEEE International Solid-State Circuits
Conference Digest of Technical Papers, pp. 472-473
Wu Wanghua, 2019, A 28-nm 75-fsrms Analog Fractional-N Sampling PLL With a Highly
Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty
Cycle Correction, IEEE Journal of Solid-State Circuits, pp. 1-12
Min Y.-J., Aug 2012, A 0.31–1 GHz fast-corrected duty-cycle corrector with successive
approximation register for DDR DRAM applications, IEEE Trans. Very Large Scale Integr.
(VLSI) Syst., Vol. 20, No. 8, pp. 1524-1528
Jeong C.H., Jan 2016, All-Digital Duty-Cycle Corrector With a Wide Duty Correction
Range for DRAM Applications, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol.
24, No. 1, pp. 363-367
Raja Immanuel, May 2016, A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique
in 130-nm CMOS, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 24, No. 5,
pp. 1975-1983
Kang K.T., Dec 2018, A 0.33–1 GHz Open-Loop Duty Cycle Corrector With Digital Falling
Edge Modulator, IEEE Trans. Circuits Syst. II, Exp. Briefs, Vol. 65, No. 12, pp. 1949-1953
Author
Dong Gyu Kim received his B.S. degree from the Department of Electronic Engineering
at Sungkyun-kwan University, Suwon, Korea, in 2017, where he is currently working
toward the Combined Ph.D. & M.S degree in School of Information and Communication
Engineering.
His research interests include CMOS RF transceiver and wireless power transfer systems.
Joon-Mo Yoo received his B.S. degree from the Department of Electronic Engineering
at Ajou University, Gyeonggi-do, Korea, in 2002, M.S. from the School of Electrical
Engineering at Seoul National University, Seoul, Korea, in 2004 respectively.
From 2004 to 2014, he worked as Principal Engineer and R&D Manager in GCT Semiconductor,
Inc, at San Jose, CA, and GCT Research, Inc, in Korea, where he’s developing PHS,
CDMA, WCDMA, LTE RF Multi-mode Multi band transceivers.
From 2014 to 2016, he worked as Chip Development Director at MELFAS, Korea, where
he was leading the capacitive touch-screen controller IC development.
And then he worked as Sr. Director at Celfras Semiconductor located in Jiangxi province
in China from 2016 to 2021, where he leading for the various power of wireless-charging
solutions.
Currently, he is working at SKAIChips as an R&D executive at Sungkyunkwan University.
His research interest is focused on digital circuit design and CMOS RF transceiver
and wireless charging solutions.
Young Gun Pu received his B.S., M.S. and Ph.D. degrees from the Department of Electronic
Engi-neering at Konkuk University, Seoul, Korea, in 2006, 2008 and 2012, respectively.
From 2012 to 2013, he served as a Senior Engineer in Modem RF Lab at DMC R&D Center,
Samsung Electronics, Korea. From 2013 to 2019, he worked as a Senior Engineer at WDT/Hivics,
Korea.
Currently, he is a research Professor at Sungkyunkwan University.
His research interest is focused on high-speed interface, CMOS fully integrated frequency
synthesizers, oscillators, and RF transceivers.
Yeon Jae Jung received the B.S., M.S. and Ph.D. degrees in the School of Electrical
Engineering from Seoul National University, Seoul, Korea, in 1997, 1999, and 2003,
respectively.
From 2003 to 2014, he was with GCT Semiconductor Inc., San Jose, CA, where he was
involved in the design of CMOS RF transceiver ICs for W-CDMA, WLAN, WIMAX, CDMA, GPS,
and LTE.
From 2014 to 2020, he was with Celfras Semiconductor Inc., where he worked on BLE
v4.2 ultra-low power RF transceiver IC and power ICs for wireless power receiver,
battery charger, and DC-DC converter.
He is currently a VP with SKAiChips and a university-industry collaboration professor
also with Sungkyunkwan University.
His research interests include the design of power integrated circuits and CMOS RF
transceiver.
Hyung Ki Huh was born in Seoul, Korea.
He received the B.S., M.S., and Ph.D. degrees from the School of Electrical Engineering
and Computer Science, Seoul National University, in 1998, 2001, and 2006, respectively.
From 2001 to 2014, he was with GCT Semiconductor Inc., San Jose, CA, where he was
involved in designing wireless transceivers.
From 2017 to 2021. He was with Anapass Inc., Seoul, where he was involved in designing
high-speed serial links.
In 2021, he joined SKAIChips Co., Suwon, as a Chief Design Officer.
Currently, he is a university-industry collaboration professor also at Sungkyunkwan
University.
His research interests are in the area of frequency synthesizers, high-speed communication
interfaces, and PMIC.
Seok Kee Kim received his B.S., M.S., and Ph.D. degrees from Seoul National University,
South Korea, in 1997, 1999, and 2006, respectively.
From 2001 to 2016, he was with GCT Semiconductor Inc. From 2016 to 2021, he was with
Celfras Semiconductor Inc., Seoul, South Korea.
In 2021, he joined SKAIChips Co., Suwon, as a Chief Design Officer.
Currently, he is a university-industry collaboration professor also at Sungkyunkwan
University.
His research interests includes analog backend design and mass-production management,
power management intergrated circuits (PMICs) implementation, and CMOS RF transceiver
and SOC integrated implementation.
Keum Cheol Hwang received his B.S. degree in electronics engi-neering from Pusan National
University, Busan, South Korea in 2001 and M.S. and Ph.D. degrees in electrical and
electronic engineering from Korea Advanced Institute of Science and Technology (KAIST),
Daejeon, South Korea in 2003 and 2006, respectively.
From 2006 to 2008, he was a Senior Research Engineer at the Samsung Thales, Yongin,
South Korea, where he was involved with the development of various antennas including
multiband fractal antennas for communication systems and Cassegrain reflector antenna
and slotted waveguide arrays for tracking radars.
He was an Associate Professor in the Division of Electronics and Electrical Engineering,
Dongguk University, Seoul, South Korea from 2008 to 2014.
In 2015, he joined the Department of Electronic and Electrical Engineering, Sungkyunkwan
University, Suwon, South Korea, where he is now an Associate Professor.
His research interests include advanced electromagnetic scattering and radiation theory
and appli-cations, design of multi-band/broadband antennas and radar antennas, and
optimization algorithms for electro -magnetic applications.
Prof. Hwang is a life-member of KIEES, a senior member of IEEE and a member of IEICE.
Young Goo Yang was born in Hamyang, Korea, in 1969.
He received the Ph.D. degree in electrical and electronic engineering from the Pohang
University of Science and Technology (Postech), Pohang, Korea, in 2002.
From 2002 to 2005, he was with Skyworks Solutions Inc., Newbury Park, CA, where he
designed power amplifiers for various cellular handsets.
Since March 2005, he has been with the School of Information and Communication Engineering,
Sungkyunkwan University, Suwon, Korea, where he is currently an associate professor.
His research interests include power amplifier design, RF transmitters, RFIC design,
integrated circuit design for RFID/USN systems, and modeling of high power amplifiers
or devices.
Kang-Yoon Lee received the B.S., M.S. and Ph.D. degrees in the School of Electrical
Engineering from Seoul National University, Seoul, Korea, in 1996, 1998, and 2003,
respectively.
From 2003 to 2005, he was with GCT Semiconductor Inc., San Jose, CA, where he was
a Manager of the Analog Division and worked on the design of CMOS frequency synthesizer
for CDMA/PCS/PDC and single-chip CMOS RF chip sets for W-CDMA, WLAN, and PHS.
From 2005 to 2011, he was with the Department of Electronics Engineering, Konkuk University
as an Associate Professor.
Since 2012, he has been with College of Information and Communication Engineering,
Sungkyunkwan University, where he is currently a Professor.
His research interests include implementation of power integrated circuits, CMOS RF
transceiver, analog integrated circuits, and analog/digital mixed-mode VLSI system
design.