I. INTRODUCTION
For broadband signal generation, there are direct digital synthesizer (DDS) and multi
phased locked loops (PLL). DDS offers board frequency generation, fast frequency hopping,
compact size, high power efficiency, decent signal to noise ratio, and excellent phase
noise (1). The multi-PLLs method has a limitation on the frequency hopping due to the switching
among PLLs and the PLL locking range from the individual loop (2). Furthermore, DDS has its advantage on the phase modulation, which is an essential
part of the communication and radar co-existence dual-functional system (3). For a broadband signal generation coving L/S/C-band, a DDS based solution with a
16 GHz clock could achieve the whole-band coverage with only one module.
Ultra-high-speed full adder is frequently used to evaluate the device performance
and integration capability of a technology (4). The phase accumulator composed of adders is the critical part of a DDS, and it is
also one of the speed bottlenecks of the whole DDS (5). The data width and clock frequency of the phase accumulator determine the frequency
resolution and output frequency range of the DDS system. To meet the requirements
of high speed and high frequency, the phase accumulator designed by III-V compound
semiconductor process is usually realized by pipeline architecture (6). The performance of the full adder directly determines the highest frequency of the
pipelined phase accumulator (7).
In a tens of GHz mixed-signal circuit, signal integrity (SI) is crucial. In a DDS
system, clock distribution is the most critical part of SI analysis. The time-domain
misalignment for clock distribution would generate the DDS system's dynamic error,
which would decrease the signal quality. Considering that a clock line would easily
be in the order of hundreds of micrometers, the passive EM model and active SPICE
model co-simulation are introduced in the RF and mm-wave synthesizer design. It is
quite time-consuming due to the complicity of the metal and semiconductor materials
(8). Furthermore, in an 8-bit DDS, the clock distribution complexity is too complicated
for this design methodology. In this paper, we proposed a transmission line equivalent
(TLE) design methodology to simplify it. In this way, the long wire will be extracted
after layout and modeled by a transmission line mode. This method can simplify the
design cycle and SI consideration according to the termination condition and successfully
demonstrated by the fulfillment of the full adder.
Fig. 1. Circuit diagram of the 3-level series-gated full adder.
For high-speed mixed-signal circuit, the InP material has higher mobility and larger
band gap than Si and GaAs. With the development of InP DHBT technology, it can integrate
a mixed-signal system on a die under a scale of hundreds of transistor (9-13). Furthermore, in InP DHBT technology, the substrate is semi-insulating. This high
resistance substrate is ideal for noise insulating, such as high-frequency clock cross-coupling,
digital-analog signal cross-coupling, and substrate noise-coupling. Compared to silicon
material and GaAs, InP DHBT is a better technology for mixed-signal circuit in millimeter-wave
frequency. In this design, the InP technology adopted is with an emitter width of
0.7 μm, with its $f_{\mathrm{t}}$ and $f_{\mathrm{max}}$ higher than 250 GHz and 280
GHz, respectively. The reverse saturation voltage (BV$_{\mathrm{CEO}}$) can be larger
than 3.5 V.
In this paper, a 32.2 GHz, 1bit full adder and its application in a 17 GHz, 8 bit
DDS in a 0.7 μm InP DHBT technology is presented. The rest of the paper is organized
as follows. In section Ⅱ, the ultra-high-speed, low power full adder circuit will
be introduced. The TLE design methodology will be analyzed in Section III. Section
IV presents the measurement results of the full adder and its application in the DDS.
Conclusions will be drawn in Section V.
II. Full Adder Circuit Design
1. Latch Combined Full Adder
A 1bit full adder generates sum “S” and carry out “$C_{\mathrm{out}}$” based on A,
B and carry in “$C_{\mathrm{in}}$”. The relations of the full adder can be expressed
by Boolean operators as shown in Eq (1) and Eq (2).
Current-mode logic (CML) is one of the best choices for bipolar devices to realize
ultra-high-speed digital circuits. It has the advantages of fast speed and low noise
(14). At the same time, CML circuits can realize complex logic operations by differential
stacking of multilevel transistors. According to Eq (1) and Eq (2), the logic operation circuits are shown in Fig. 1. It can be seen that sum “S” and carry out “$C_{\mathrm{out}}$” can be realized in
logic gate circuit by stacking three-level differential pairs and utilizing the full
differential characteristics of CML circuit.
A sequential circuit can be realized by inserting latches between combinational circuits.
The clock controlled full adder can be realized by cascading a latch at the output
end. The time required to perform one addition includes combinational logic delay
$t_{\mathrm{dlogic}}$ and latch delay $t_{\mathrm{dlatch}}$, so the maximum frequency
of the full adder is 1/($t_{\mathrm{dlogic}}$+$t_{\mathrm{dlatch}}$). If the combinational
logic and latch are combined together (15), the signal delay caused by latch can be eliminated, and the maximum frequency can
be increased to 1/$t_{\mathrm{dlogic}}$. Fig. 2 shows the clock-controlled circuit diagram of sum and carry out. The circuit adopts
four-level differential stacking structure. Compared with the combinational logic,
this circuit adds one level of differential pair. Therefore, the clock-controlled
circuits require that the supply voltage increase at least one diode voltage to ensure
the circuit work normally. It can be seen that the performance improvement is at the
cost of increasing power consumption.
Fig. 2. Circuit diagram of 4-level series-gated full adder with cascaded latch.
Fig. 3. Single-level parallel-gated carry circuit with cascaded latch.
2. Lower Power Full Adder
In DDS circuits, except for phase accumulator, most of the other circuits are one-level
or two-level stacking, and a few three-level stacking. If the four-level stacking
full adder is directly applied to DDS’s phase accumulator, the supply voltage and
power consumption will increase. Therefore, it is necessary to adjust the structure
to reduce power supply voltage. Analyzing the carry operation of an adder, when two
or three of the three input signals are logically high, the carry output is high,
which just accords with the majority decision rule (16). From the circuit point of view, the parallel structure is in good agreement with
majority decisive operations. Based on this conclusion, a single-level parallel carry
circuit is designed as shown in Fig. 3, which also integrates latch functions. Only two-level differential pair stacking
is needed to realize carry operation and data latching.
According to Fig. 3, when all three inputs are “1” or “0”, all current flows through $X_{\mathrm{p}}$
or $X_{\mathrm{n}}$ nodes, and X-terminal outputs full-swing differential signals.
When one or two input terminals are “1”, one branch flows through 1/3 of the current,
the other side 2/3, and the output amplitude of X-terminal decreases. Although the
output amplitude of majority decision operation circuit is small in some states, the
later stage latch will amplify to full-swing amplitude without affecting latter stage
circuit. Fig. 4 shows the simulation results, it is obvious that the output differential signal is
in full-swing amplitude after the latch, and the logic operation is correct.
For the multi-bit adder, the high-bit can only be performed after the low-bit is finished.
Therefore, carry link is key factor while the requirement for the sum circuit is relatively
low. Using two-stage logic to complete the sum operation and the circuit is presented
in Fig. 5. The sum circuit combines synchronous latch and adopts a three-level differential
stacking structure.
Through the above circuit design, the full adder with latches can be reduced from
four-level to three-level stacking, so the circuit can work for lower supply voltage
and lower power consumption while the performance is unchanged.
Fig. 4. Simulation results of single-level parallel-gated carry circuit.
Fig. 5. Circuit diagram of 3-level series-gated sum circuit with cascaded latch.
III. TLE Design Methodology
1. TLE Effect
In a high-speed mixed-signal circuit, the routing for the signal line could be hundreds
of micrometer. According to the rule of thumb, when the trace length of the interconnect
is greater than 1/6 of the equivalent length of the rising edge, it is considered
that this interconnect has an effect on the signal transmission and needs to be treated
as a transmission line (17). This boundary conditional can be described as,
where $t_{r}$ is the minimum rising edge of the signal on the interconnect, D is the
propagation delay of the signal.
According to the rising edge $t_{r}$, the time constant τ of the circuit and the relationship
between the circuit bandwidth (BW) and the time constant can be obtained, as shown
by Eq (4) and Eq (5).
As can be seen from the above two equations, the relationship between the rising edge
tr and the bandwidth is shown in Eq (6).
For ultra-high-speed circuit, as the logic circuit with a fully differential structure
is adopted, the clock sampling edge is judged according to the differential signals'
intersection, so the circuit has lower requirements for the rising and falling edge
of the clock signal. Also, because of the differential structure, the clock signal
can be sinusoidal. In this sinusoidal case, the bandwidth requirement of the circuit
is equal to the clock frequency. With a clock frequency of 36 GHz, the rising edge
of the clock signal is $t_{r}$ = 0.35/36 GHz = 9.7 ps. The relative permittivity of
substrate material used in InP DHBT process is ${\varepsilon}$$_{r}$=12.4, so the
phase velocity and propagation delay of the signal are
According to Eq (3), the boundary length is 136 μm. For interconnection longer than 136 μm, the transmission
line effect must be considered.
Fig. 6. Method to improve signal integrity by taking TLE effects.
Fig. 7. Comparison of the Signal.
2. Signal Integrity Issues Due To TLE
For ultra-high-speed circuits working at tens of GHz, the switching frequency of internal
signals is extremely high, and the interconnection between signals have a great impact,
mainly for reflection, crosstalk, oscillation and attenuation. All of these will cause
SI issues. To overcome these problems, the termination is needed. At the connection
node for several branches in a long interconnection line, a series resistor should
be applied to absorb the reflected signal, reducing the signal's overshoot. While,
at the end of the long interconnect, a parallel RC network should be applied to absorb
signal reflections caused by discontinuities in the interconnect impedance, as shown
in Fig. 6. A comparison of this method for a connection node among different branches is provided
in Fig. 7. As shown in Fig. 7, this method could improve the signal quality, and the SI issue is improved in this
way. Furthermore, the routing distribution should be symmetrical and balanced in the
layout, also its loading condition should be identical to each other.
3. Circuit Design With TLE Method
At present, there are simulation software and design methods for SI analysis of PCB
circuit. However, for integrated circuits (ICs), the wiring densities are much larger
and space size is much smaller. Also, active and passive devices are implemented on
the same semiconductor material so that circuit environment is more complex. Therefore,
there is no perfect solution for SI analysis at chip level, especially for ultra-high
speed mixed signal circuits in Ku and above bands.
For RF and microwave ICs, full-circuit three-dimensional electromagnetic simulation
is widely adopted (8). This method has good accuracy, but it takes very long time, so it is not appropriate
for mixed signal circuits such as DDS which have much greater integration density.
Compared with RF and microwave circuits, mixed signal circuits are relatively insensitive
to microwave parameters such as harmonic characteristics, so the requirement of accuracy
for the model is lower.
Fig. 8. Diagram of test circuit and its measurement configuration.
As mixed signal circuits have high integration and high wiring density, if the interconnect
is modified only when the physical layout design is completed, then the scope of modification
is usually small. Also the layout of the circuit needs to be adjusted, and the electromagnetic
simulation analysis is needed after each modification. Therefore, the iteration period
is very long, and the flexibility of terminal design adjustment is limited. For the
TLE method proposed, after completion of circuit layout, the length of the high-speed
signal interconnects can be estimated. For interconnects that exceed the equivalent
length of the rising edge, take their transmission line model into the circuit schematic
diagram for co-simulation analysis, and the termination mode and device parameters
of the termination network can be designed accordingly. Then the physical layout of
the circuit is designed according to the calculated termination parameters. This method
can carry out the signal integrity design at the same time of physical layout design,
and the physical layout can be adjusted at any time according to the simulation results.
Therefore, the design flexibility of termination mode is high and there is no need
for electromagnetic simulation of physical layout, thus shorten simulation time and
iteration period.
Fig. 9. Co-simulation of passive components with TLE model and active component with
the SPICE model.
Fig. 10. Equivalent simulation results of adder transmission line.
The full adder is designed with this TLE method. The clock frequency of the 1-bit
adder is designed to be 36 GHz. Because it is extremely difficult to provide such
a high-speed input signal during measurement, the 1-bit adder is connected as shown
in Fig. 8. The two inputs are connected to "1" and "0" respectively, and the carry output is
connected to the carry input in reversed-phase so that the adder can realize the function
of by two frequency divider. The equivalent length of a rising edge is 136 μm. Therefore,
some redundant designs have been made, so that the TLE is adopted for all the interconnection
lines with the length greater than 120 μm. Fig. 9 presents the co-simulation circuit diagram after the TLE is completed. The longest
interconnection line is the clock signal, and its length is 480 μm. The second-longest
is the carry output feedback to the carry input. Its frequency is half of the clock,
but its rising edge is close, and the length is 390 μm.
Fig. 10 shows the simulation results of the equivalent joint simulation of the transmission
line of the adder measurement circuit. Through the appropriate termination design,
the maximum clock frequency of the 1-bit adder is 35 GHz. Compared with the circuit
designed, the performance is slightly degraded, which is caused by the propagation
delay of the carry output feedback link.
The physical layout design is implemented according to the termination parameters
obtained from co-simulation, and the length of interconnect in the layout is then
extracted and inverted into the co-simulation circuit diagram for post-simulation
verification. As the interconnect length obtained after the overall layout is quite
accurate, and the influence of tens of μm interconnect length change on the termination
network is small, so design iterations needed is much less.
Fig. 11. Microphotograph of full adder measurement circuit.
IV. Measurement Results
The micrograph of the full adder test circuit is presented in Fig. 11. The chip consists of 142 transistors with a size of 630 μm${\times}$680 μm. It is
fabricated in two metal layers 0.7 μm InP DHBT process with $f_{\mathrm{t }}$ > 250
GHz and $f_{\mathrm{max}}$ > 280 GHz.
Fig. 12. Measured spectrum of output @$f_{\mathrm{clk}}$=32.2 GHz.
Table 1. Full adder performance summary and comparison
|
Comparison
|
(7)MWCL’05
|
(6)EL’01
|
(9)CSB’12
|
This work
|
|
Technology
|
VIP-2 InP DHBT
|
1.0 μm InP DHBT
|
1.4 μm
GaAs HBT
|
0.7 μm
InP DHBT
|
|
Transistor’s ft(GHz)
|
300
|
170
|
60
|
250
|
|
fclk,max(GHz)
|
41
|
19
|
5.3
|
32.2
|
|
FOM(bit•GHz/W)
|
91.1
|
31.7
|
70.67
|
92
|
Fig. 12 shows the output signal spectrum. It can be seen from this figure that for 32.2 GHz
input clock the output signal frequency is 16.1 GHz. From the measurement result,
the TLE co-simulation aligned with the measurement. Its accuracy is 91.4%. Also, this
standalone test circuit proves the TLE design methodology.
Table 1 summarize the performance and compares to the other works on compound semiconductor
process. To the author’s knowledge, the maximum operating frequency of ultra-high
speed adder is 41 GHz with $f_{\mathrm{t}}$ of 300 GHz (7). Ours ranks the second fastest with $f_{\mathrm{t}}$ of 250 GHz, and has the best
Figure of Merit (FOM) performance.
The 1bit full adder is the speed bottleneck of the phase accumulator thus the bottleneck
of the DDS. With the help of TLE method, a 17 GHz, 8 bit ROM-Less DDS is designed
and fabricated in the same technology. Fig. 13 is the micrograph of the DDS chip. The chip consists of about 1700 transistors with
an area of 2.2${\times}$1.6 mm$^{2}$.
The DDS is powered by a single 5 V power supply with an overall power consumption
of 7.4 W. Fig. 14 presents the SFDR curves of all frequencies rang with 17 GHz clock. The frequency
control word (FCW) increases from 1 to 128. The output frequencies of DDS range from
66.41 MHz to 8.5 GHz. The frequency resolution is 66.41 MHz. The worst SFDR is -10.4
dBc, and the average SFDR is -18.1 dBc.
Table 2. Ultra-High-Speed DDS Performance Comparison
|
Comparison
|
(3) EuMIC’18
|
(20)MWCL’06
|
(21)CSIC’05
|
(22)JSSC’06
|
This work
|
|
Process
|
SiGe
|
InP
|
InP
|
InP
|
InP
|
|
ft/fmax(GHz)
|
180/220
|
300/300
|
406/423
|
300/300
|
250/280
|
|
Emitter area of minimal Size Transistor [μm2]
|
-
|
0.4×2
|
0.25×1
|
0.4×2
|
0.7×5
|
|
Accumulator size [bit]
|
12
|
8
|
9
|
8
|
8
|
|
DAC resolution [bit]
|
6
|
7
|
-
|
5
|
4
|
|
Max clock frequency [GHz]
|
20
|
13
|
12
|
32
|
17
|
|
Average SFDR within Nyquist frequency [dBc]
|
-
|
-26.67
|
-30
|
-21.56
|
-18.1
|
|
Power consumption [W]
|
1.54
|
5.42
|
8
|
9.45
|
7.4
|
|
Transistors number
|
4500
|
1646
|
8800
|
1891
|
1700
|
|
Die size [mm2]
|
3.61
|
3.915
|
-
|
3.915
|
3.52
|
Table 2 summarize the DDS’s performance and its comparison to the other works. This work
achieves high speed, moderate resolution and keeps a decent power efficiency compared
to other works.
Fig. 13. Microphotograph of 17 GHz, 8 bit ROM-Less DDS.
Fig. 14. SFDR VS DDS output frequency @ 17 GHz clock.
V. CONCLUSIONS
In this paper, a 32.2 GHz, 1bit full adder in a 0.7 μm InP DHBT technology is presented.
The synchronous latch is combined with adding operation to improve the calculation
speed. A single-level parallel-gated circuit is designed using majority decision algorithm
to reduce power consumption. To solve the signal integrity issue for high integration
and high wiring density mixed signal integrated circuit, TLE design method is proposed
and demonstrated by the realization of the adder and the 17 GHz, 8 bit DDS which can
synthesize sin-wave outputs from 66.41 MHz to 8.5 GHz in 66.41 MHz steps with an average
SFDR of -18.1 dBc.
ACKNOWLEDGMENTS
The research is supported by National Natural Science Foundation of China (No. 61804081),
China Postdoctoral Science Foundation (No.2018M642292), Open project of State Key
Laboratory of Millimeter Waves (No. K202220) and Chinese international cooperation
funding (No. G2021016011L).
REFERENCES
Vankka J., Halonen K., Dordrecht: 2001, Direct Digital Synthesizers: Theory, Design
and Applications, Kluwer Academic Publishers
Moll J., Hils B., Shrestha A., Ehlert A., Krozer V., Thurn K., Vossiek M., Horbak
M., Hossain M., Heinrich W., Resch M., Bosse J., 2017, Panel design of a MIMO imaging
radar at W-band for space applications, 14$^{th}$ European Radar Conference, pp. 126-129
Shrestha A., Moll J., Raemer A., Horbak M., Krozer V., 2018, 20 GHz Clock Frequency
ROM-Less Direct Digital Synthesizer Comprising Unique Phase Control Unit in 0.25 μm
SiGe Technology, 13$^{th }$European Microwave Integrated Circuits Conference, pp.
206-209
Stanchina W. E., Jensen J. F., Walden R. H., Hafizi M., Sun H. C., Liu T., Raghavan
G., Elliott K. E., Kardos M., Schmitz A. E., Brown Y. K., Montes M. E., Yung M., 1995,
An InP-based fab for high-speed digital, analog, mixed-signal, and optoelectronic
ICs, GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual
Technical Digest, pp. 31-34
Aitken A. G., Matsui J., Kaneshiro E. N., Oyama B. K., Sawdai D., Oki A. K., Streit
D. C., 2002, Ultra high-speed direct digital synthesizer using InP DHBT technology,
IEEE Journal of Solid-State Circuits, Vol. 37, pp. 1115-1119
Eckroot C. G., Long S. I., 1988, A GaAs 4-bit adder-accumulator circuit for direct
digital synthesis, IEEE Journal of Solid-State Circuits, Vol. 23, pp. 573-580
Turner S. E., Elder R. B., Jansen D. S., Kotecki D. E., 2005, 4 bit adder-accumulator
at 41-GHz clock frequency in InP DHBT technology, IEEE Microwave and Wireless Components
Letters, Vol. 15, pp. 144-146
Cao J., 2014, Research on Key Technologies of microwave and millimeter wave integrated
circuits based on CMOS technology, Southeast University Nanjing China
He G., Howard J., Le M., Partyka P., Li B., Kim G., Hess R., Bryie R., Lee R., Rustomji
S., Pepper J., Kail M., Helix M., Elder R.B., Jansen D.S., Harff N.E., Prairie J.F.,
Daniel E.S., Gilbert B.K., 2004, Self-aligned InP DHBT with $f_{\mathrm{t}}$ and f}$_{\mathrm{max}}$
over 300 GHz in a new manufactural technology, IEEE Electron Device Letters, Vol.
25, pp. 520-522
Li X., Wang Z., Zhang Y., Zhang Y., Zhang M., 2018, A 13GS/s One-Bit ADC with 18GHz
Analog Bandwith Based On InP DHBT Technology, 14th IEEE International Conference on
Solid-State and Integrated Circuit Technology, pp. 1-3
Li X., Zhang Y., Wang Z., Zhang Y., Zhang M., Cheng W., Gao H., 2019, A 14-GHz 8-bit
Direct Digital Synthesizer in InP DHBT Technology, IEEE International Symposium on
Radio-Frequency Integration Technology, pp. 1-3
Zhang M., Meng Q., Zhang Y., Li X., Zhang Y., Cheng W., 2019, A Broad-Band 1:4 Static
Frequency Divider MMIC in InP HBT, IEEE 4th International Conference on Integrated
Circuits and Microsystems, pp. 242-245
Ye Q., Zhang Y., Li X., Zhang Y., 2017, A 12-bit 10GSps ultra high speed DAC in InP
HBT technology, 2nd IEEE International Conference on Integrated Circuits and Microsystems,
pp. 9-12
Razavi B., Ota Y., Swartz R. G., 1994, Design techniques for low-voltage high-speed
digital bipolar circuits, IEEE Journal of Solid-State Circuits, Vol. 29, pp. 332-339
Ivanov V. N., 1968, On realization of majority operation (the voting function) in
feedback systems, Avtomat I Telemekh, pp. 112-117
Jensen B. S., Khafaji M. M., Johansen T. K., Krozer V., Scheytt J.C., 2012, Twelve-bit
20-GHz reduced size pipeline accumulator in 0.25 μm SiGe:C technology for direct digital
synthesiser applications, IET Circuits Devices & Systems, Vol. 6, pp. 19-27
Bogatin E., 2009, Signal and Power Integrity, Prentice Hall Upper Saddle River
Mathew T., Jaganathan S., Scott D., Krishnan S., Wei Y., Urteaga M., Rodwell M., Long
S., 2001, 2-bit adder carry and sum logic circuits clocking at 19 GHz clock frequency
in transferred substrate HBT technology, Electronics Letters, Vol. 37, pp. 1156-1157
Chen J. W., Wu D. Y., Zhou L. Wu J., Jin Z., Liu X.Y., 2012, A 5.3-GHz 32-bit accumulator
designed for direct digital frequency synthesizer, Chinese Science Bulletin, Vol.
57, pp. 2480-2487
Turner S., Kotecki D., 2006, Direct digital synthesizer with ROM-less architecture
at 13-GHz clock frequency in InP DHBT technology, IEEE Microwave and Wireless Components
Letters, Vol. 16, pp. 296-298
Elliott K., 2005, Direct digital synthesis for enabling next generation RF systems,
IEEE Compound Semiconductor Integrated Circuit Symposium, pp. 125-128
Turner S., Kotecki D., 2006, Direct digital synthesizer with sine-weighted DAC at
32-GHz clock frequency in InP DHBT technology, IEEE Journal of Solid-State Circuits,
Vol. 41, pp. 2284-2290
Author
received the B.S. degree in Microelectronics from Soochow University, Suzhou, China
in 2007.
He received the Ph.D. degree in Circuit and System from RF&OE-ICs, School of Information
Science and Engineering, Southeast Univer-sity, Nanjing, China, in November 2013.
In the same year, he joined the faculty of the Department of Microelectronics Technology,
Nanjing University of Posts and Telecommunications, Nanjing, China, where he is currently
an associate professor.
His research interests include analog and mixed signal integrated circuit designs.
received the B.S. degree in Communication & Information Engineering and the M.S. degree
in Microelectronics & Solid State Electronics from Southeast University, Nanjing,
China in 2001 and 2006, respectively.
In 2006, he joined the Nanjing Electronic Device Institute, Nanjing, China, where
he is currently a senior engineer.
His research interests include high-speed data converter and ultra-high-speed mixed
signal integrated circuit designs.
received the Ph.D. degree in Shanghai Institute of Micro-system and Information Technology，Chinese
Academy of Sciences, in 2005. Then, he joined the Nanjing Electronic Devices Institute.
His research interests include high-speed analog and mixed signal integrated circuit
designs.
received the B.S. degree from Sichuan University in 1996.
He received the M.S. degree from the same university in 1999.
In June 2005, he received the Ph.D. degree in Microelectronics from University of
Electronic Science and Technology of China. He is now a Professor and vice president
of Nanjing University of Posts and Telecommunications.
His research interests include semiconductor power device, micro/nano electronics
devices, RF and power integrated circuits and systems, wireless energy transmission
and ground penetrating radar design.
He owns several awards for teaching and scientific researches and he is the recipient
and co-recipient of the several best paper rewards.
He has published more than 50 papers in his research areas.
received the B.S. degree in computer application from NUST, China in 2002. He received
the Ph.D. degree in computer application from NUST, China in May 2007.
In 2007, he joined the faculty of College of Electronic and Optical Engineering &
College of Microelectronics at Nanjing University of Posts and Telecommunications,
Nanjing, China, where he is currently a professor.
His research interests include analog/RF integrated circuit designs in CMOS technology
for the applications of body area networks and RF communications.
received the B.Eng. degree from Southeast University, Nanjing, China, the M.Sc. degree
in electrical engineering from the ELCA-Group, Delft University of Technology, Delft,
The Netherlands, in 2008.
The Ph.D. degree from the Eindhoven University of Technology, Eindhoven, The Netherlands,
in 2015.
In 2007, he was with Catena Microelectronics (now NXP), Delft.
In 2008, he was with Philips Research, Eindhoven.
In 2012, he was a European Marie Curie Researcher with Catena Wireless Electronics
Group, NXP, Stockholm, Sweden.
In 2014 he was ranked as a Staff Engineer in MediaTek.
In 2014, he joined the ELCA-Group, Delft University of Technology, as a Research Scientist.
Since 2016, he took a faculty position of the Electrical Engineering Department, Eindhoven
University of Technology, where now he is a member of the University Central Ethics
Committee board.
He is also a Principle Scientist and group leader in Silicon Austria Labs from 2019,
Austria National Lab, with a joint professorship.
He did consultant for industries for years, including NXP, AAC, etc. He is now also
an International Academic Advisor for OPPO mobile.
He has authored or coauthored over 100 papers in scientific and technical journals
and conference proceedings.
He has coauthored several books, including Batteryless mm-Wave Wireless Sensors (Springer,
2018). He holds several US and China patents.
Dr. Gao was a recipient of the Philips Semiconductor Scholarship, Delft, in 2006.
He was the recipient of the IMS and ISCAS grants. He was the recipient and co-recipient
of several best paper rewards, including IEEE MTT-S Radio Wireless Week Award, International
Conference on Information and Communications Signal Processing Award, IEEE MTT-S International
Wireless Symposium Award, IEEE IMS student design competition award.
He was also the co-recipient of the 2015 ISSCC Distinguished Technical Paper Award,
CATRENE Innovation Award with the EAST Project and others. He has served as a TPC
co-chair of RFIT, and now a TPC for IEEE RFIC, ISSCC SRP and others.
He is also with the Editor board of Cambridge Wireless Power Transfer Journal.