I. INTRODUCTION

Internet of Things (IoT) has become an emerging and fast-growing heterogeneous network that can interconnect a variety of devices, people, data, and processes for a wide range of applications. Recently, sub-GHz low power wide area network (LPWAN) technologies such as SigFox, long-range wide area network (LoRaWAN), narrowband IoT (NB-IoT), and long-term evolution (LTE)-M have been introduced to ensure a long transmission range of more than multiple kilometers with low power consumption.

The front-end circuit for sub-GHz IoT applications must be capable of handling signals with broadband input frequencies ranging from 50 MHz to 900 MHz in order to support multiple LPWAN technologies with a single hardware. This wideband nature of input signals can cause the odd local oscillator (LO) harmonic mixing problem. Because the undesired channels located at LO harmonic frequencies are aliasing into the wanted channel and thus this directly degrades signal-to-noise ratio (SNR) of the receiver, the harmonic rejection functionality is required absolutely for sub-GHz IoT front-end. In addition, the front-end should provide a sufficiently high voltage gain and a low noise figure (NF) to satisfy the stringent sensitivity requirement for various sub-GHz IoT standards. Depending on the interference environment, it also should have high linearity represented by input-referred IP3 and IP2 (IIP3 and IIP2) because the second- and third-order intermodulation distortion (IMD2 and IMD3) caused by the multiple interferers in a crowded sub-GHz spectrum can fall at the same frequency of the desired channel. In this paper, a low noise and highly linear wideband CMOS RF front-end is designed for sub-GHz IoT applications. The single-ended resistive feedback LNA, the wideband differential LNA employing thermal noise cancellation, and the in-phase and quadrature (I/Q) harmonic rejection mixer (HRM) employing IMD3 cancellation are designed in a 0.18-μm CMOS technology.

II. CIRCUIT IMPLEMENTATION

Fig. 1 shows the block diagram of the proposed RF front-end for sub-GHz IoT applications. The LNA is composed of the single-ended resistive feedback LNA (SLNA) and differential noise canceling common gate (CG) LNA (DLNA). At high sensitivity mode, the SLNA is operated as the first amplification stage of the receiver to compensate the power loss of external wideband balun and achieve sufficiently high voltage gain. This leads to excellent sensitivity performance of the receiver. On the other hand, for high selectivity mode, the operation of SLNA and DLNA is dominated by IIP2 performance because the LNA with single-ended input and output shows very poor IIP2. It was reported in ⁽¹⁾ that the required IIP2 of the wideband LNA exceeds more than +90 dBm without filtering under the condition that 1.8 GHz GSM interferer and 2.4 GHz WLAN interferer generate IMD2 in the wanted frequency of 600 MHz. Although some out-of-band (OOB) rejection characteristic of the filter can relax the required specification, it is almost impossible for the single-ended LNA to achieve this level of IIP2 performance.

Several linearization techniques to improve IIP2 of the single-ended LNA have been devised in ^(2-4), however, the amount of improvement is very sensitive to process, temperature, and voltage (PVT) variations. The complex calibration circuit to compensate PVT variations should be integrated with LNA core circuit, and this increases the hardware complexity and power consumption of the receiver. As a result, it is desirable to adopt the fully differential LNA having an excellent IIP2 as the first amplification stage of the receiver at high selectivity mode. In this work, concerning for high selectivity mode, the SLNA is powered down and it is bypassed into the DLNA without any amplification. Namely, the DLNA becomes the first amplification stage of the receiver. One of the concerns in this scheme is that the sensitivity degradation resulting from the additional power loss caused by by-pass switch and external wideband balun is inevitable at the price of high IIP2 performance. Fortunately, this is not significant because the sensitivity specification at high selectivity mode is relaxed than high sensitivity mode. In conclusion, by selecting the SLNA or the DLNA as the first amplification stage according to the mode of the receiver, the stringent requirements of sensitivity and selectivity for sub-GHz IoT receivers can be satisfied simultaneously.

For the SLNA of Fig. 2(a), the resistive feedback LNA is chosen because of its wide input impedance matching, low NF, and reasonable voltage gain with the advantage of using no external input matching components. For linearity, the feedback LNA provides good linearity because the negative feedback reduces distortion components by a factor of loop gain ⁽⁵⁾. The external transformer is employed as the output load of the SLNA, and it operates as an RF choke to provide a sufficiently high gain and ensure a good linearity. In addition, it converts a single-ended signal into a differential signal for the DLNA. The use of an external transformer is inevitable because it is almost impossible to implement a broadband on-chip transformer working over the entire frequency bands from 50 MHz to 900 MHz due to the limitation of silicon area and power loss.

Fig. 2(b) shows the proposed broadband LNA employing thermal noise cancellation based on current amplification. By adopting the structure combining the CG amplifier (M₁) with the common source (CS) amplifier (M₂) thorough the current mirror, the dominant noise source from M₁ is cancelled out at the LNA output. This is when total transconductance (g_m1N) of the CG transistor with current amplification is equal to the transconductance (g_m2) of the CS transistor. The wideband input impedance matching (Z_IN = 2/g_m1) is easily obtained by the CG amplifier. In addition, the proposed LNA has relatively high IIP3 due to current amplification, which can eliminate voltage-to-current (V-I) conversion process resulting in nonlinearity. The adopted current mirror in this work is on the basis of a modified current mirror configuration. In the modified current mirror, instead of dc coupling, two current mirror transistors M₃ and M₄ are ac-coupled through the capacitor C2. Because the width of the transistor M₄ can be increased under allowed gain bandwidth without dc current amplification, the modified current mirror shows higher current mirror ratio N = (W/L)4/(W/L)3 with low dc power consumption compared to conventional current mirror.

Fig. 3 shows the schematic of the HRM composed of a transconductance stage, a phase-shifting stage, and two coefficient scaling and summing stages for in-phase (I) and quadrature-phase (Q) path. Because the linearity burden of the RF front-end lies in the down-conversion mixer, it is important to design a highly linear wideband down-conversion HRM. In order to improve the linearity of the mixer in wideband without additional power consumption, the micro-mixer topology with the CG input stage employing IMD3 cancellation technique is adopted as shown in Fig. 3. The IMD3 current (It.3rd) of the linearized input transconductor in Fig. 3 can be expressed as

where vin is the small signal input voltage of the mixer and g_m⁽²⁾ is the second derivative of the transconductance gm. In order to obtain high IIP3, the magnitude of g_m1⁽²⁾ - g_m2⁽²⁾ + g_m3⁽²⁾ should be minimized by choosing the proper size and dc bias of the transistors M₁, M₂, and M₃ ⁽⁶⁾. The 45° phase-shifted multiphase LO signals drives the HRM. The four switching mixers to generate I and Q baseband signals is used in the HRM. The phase-shifting stage plays the role of the phase rotation of an input signal using 45° phase-shifted LO signals as well as down-conversion through four individual switching mixers. In the coefficient scaling and summing stage, three phase-shifted baseband signals down-converted from RF bands are combined with weighted size ratio of 1:√2:1 through current mirror pairs (M₂₀ and M₂₈ : M₂₂ and M₂₉ : M₂₄ and M₃₀). The coefficient scaling and summation in the baseband domain reduces the gain mismatch compared to that in the RF domain of ⁽⁷⁾.

III. MEASUREMENT RESULTS

The proposed RF front-end was fabricated in a 180 nm RF CMOS technology. Fig. 4 shows a photograph of the proposed RF front-end. The chip size is 1 mm x 0.7 mm, including pads. The proposed RF front-end including LO generation circuit draws 11.6 mA for high selectivity mode and 15.6 mA for high sensitivity mode from a 1.8 V supply voltage, respectively.

Fig. 5 shows the simulated and measured conversion gain (A_v), input return loss (S₁₁), NF, IIP3, and IIP2 of the proposed RF front-end when the SLNA is activated and bypassed, respectively. The filled and blank symbols denote the measurement and simulation results, respectively. The simulated IIP2 result is omitted because it depends on the amount of mismatch of the differential structure in the layout. The reported NF is the double-sideband NF, and the two tone spacing is 1 MHz for the linearity test.

At high sensitivity mode where the SLNA is enabled, the RF front-end shows an A_v of greater than 38 dB, a NF of less than 2.1 dB, an IIP3 of greater than -23 dBm, and an IIP2 of greater than +15 dBm in the measurement. Concerning for high selectivity mode where the SLNA is powered down, the RF front-end achieves an A_v of greater than 22.5 dB, a NF of less than 4.7 dB, an IIP3 of greater than –6.8 dBm, and an IIP2 of greater than +50 dBm in the measurement. On the whole, the measurement result is well matched to the simulation result. Compared to the simulation result, due to a narrower bandwidth of the front-end circuit, the measured A_v slightly drops as the operating frequency increases. Because the gain of the DLNA is not high enough to suppress the noise contribution of the following HRM, the difference between the simulated and measured NF at high selectivity mode becomes slightly higher than that at high sensitivity mode. In case of the measured S₁₁, the proposed front-end shows a S₁₁ of lower than -10 dB over the entire operating frequency bands.

Fig. 6 presents the measured 3rd LO harmonic rejection ratio (HRR) of the proposed front-end. The LO signal of 250 MHz, desired input signal of 251 MHz, and undesired interferer of 751.1 MHz were applied to the input of the receiver. Then, the fundamental component of 1 MHz and 3rd LO harmonic mixing component of 1.1 MHz were detected for the measurement of the 3rd LO HRR. The measured 3rd LO HRR is 57.3 dBc without any calibration. Fig. 7 shows the measured 3rd and 5th LO HRR over the operating frequency range. The front-end circuit achieves quite high HRR performance ranging from -55 dBc to -60 dBc due to accurate coefficient scaling and summation in the baseband domain through current mirrors.

In Table 1, experimental results are summarized and compared to the traditional front-end circuits for sub-GHz IoT receivers. The proposed front-end shows an excellent NF at high sensitivity mode and linearity (IIP3 and IIP2) at high selectivity mode with lower power consumption in comparison with the conventional front-end circuits.

IV. CONCLUSIONS

A low noise and highly linear wideband RF front-end with the harmonic rejection mixer is implemented as a part of the low power sub-GHz IoT receiver. Depending on the interference environment, the proposed front-end supports two operation modes having high sensitivity and selectivity performance by enabling or disabling the first building block of the single-ended LNA. By selecting the SLNA or the DLNA as the first amplification stage according to the mode of the receiver, the stringent requirements of sensitivity and selectivity for sub-GHz IoT receivers can be satisfied simultaneously.