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1. (KAIST - School of Electrical Engineering, Yuseonggu, Daehakro Daejeon 34141, Korea)

Hf$_{\mathbf{0.5}}$Zr$_{\mathbf{0.5}}$O$_{\mathbf{2 }}$(HZO), DE/FE stack remanent polarization, leakage current, thermal stability

## I. INTRODUCTION

Ferroelectricity in undoped and doped HfO$_{2}$ has been exploited substantially in recent years due to its abundant advantages such as wide bang gap, excellent scalability, admirable endurance, reliability and most importantly its adaptability with the current CMOS technology (1-10).

Especially, ferroelectric HfO$_{2}$ based materials have been studied widely as gate for FET based ferroelectric non-volatile memory applications to achieve steep-slope switching by utilizing its negative capacitance property (11-17). In such devices, a ferroelectric (FE) and dielectric (DE) bilayer stack is usually applied as the gate stack. Apart from non-volatile memory applications, the bilayer stack of DE/FE materials has also been explored for capacitance enhancement to attain higher energy storage and capacitance density in electrostatic storage and DRAM applications respectively (18-22). Considering the tremendous attention received by the DE/FE stack, it is very important to understand the influence of the DE layer on the ferroelectric properties of the FE materials in such stacks. In case of Metal Ferroelectric Metal (MFM) capacitor, the charges due to the spontaneous polarization of the FE material are screened by the metal electrode. On the contrary, insertion of a dielectric layer in between the ferroelectric layer and the metal electrode results in unscreened charges which in turn leads to an internal and depolarization field across the DE and FE layer respectively thereby effecting the ferroelectric properties of the FE layer (23). Recently, Al$_{2}$O$_{3}$/Hf$_{\mathrm{0.5}}$Zr$_{\mathrm{0.5}}$O$_{2}$ DE/FE stack has received significant attention. Wang et. al has proposed Al$_{2}$O$_{3}$ interlayer as an alternate to the metallic cathode for achieving ferroelectricity in HZO (24). Similarly, Si et. al. has studied the ferroelectric switching mechanism in such stacks although they used considerably higher thickness of both HZO and Al$_{2}$O$_{3}$ interlayer. The role of such dielectric interlayer on the thermal stability of DE/FE stack is also less explored (25).

Fig. 1. Variation of P$_{\mathrm{r}}$ value of the DE/FE stack for different DE layer thickness at RTA temperature of (a) 600 ˚C, (b) 700~˚C, (c) 800 ˚C, (d) 900 ˚C.

Fig. 2. P-E curves of the MFM capacitors with and without the Al$_{2}$O$_{3}$ DE layer at RTA temperature of (a) 600 ˚C, (b) 700 ˚C, (c) 800 ˚C, (d) 900 ˚C.

In this report, we have investigated the role of thin (< 3 nm) DE layer thickness and the annealing temperature on the ferroelectric properties of Al$_{2}$O$_{3}$/Hf$_{\mathrm{0.5}}$Zr$_{\mathrm{0.5}}$O$_{2}$ bilayer stack and its thermal stability. The DE layer thickness was found to play a crucial role in defining the remanent polarization of the fabricated capacitors. The DE/FE stack showed enhanced remanent polarization (P$_{\mathrm{r}}$) as compared to the reference HZO capacitor for very thin DE layer whereas for higher DE layer thickness, the ferroelectricity in the DE/FE stack was suppressed. The E$_{\mathrm{c}}$ of the DE/FE based capacitors were found to increase with DE layer thickness. Moreover, the addition of Al$_{2}$O$_{3}$ layer was also found to increase the thermal stability of the DE/FE capacitors.

## II. Experimental

In this study, capacitors in TiN/Hf$_{\mathrm{0.5}}$Zr$_{\mathrm{0.5}}$O$_{2}$/Al$_{2}$O$_{3}$/TiN structures were fabricated on Si/SiO$_{2}$ substrates where the Hf$_{\mathrm{0.5}}$Zr$_{\mathrm{0.5}}$O$_{2}$ FE layer thickness was fixed at 100 Å and the Al$_{2}$O$_{3}$ DE layer thickness was varied in the range of 0-30 Å. The TiN top and bottom electrodes were fabricated by using DC sputtering technique. The FE and DE layers were deposited using thermal atomic layer deposition technique where growth rate of HfO$_{2}$, ZrO$_{2}$ and Al$_{2}$O$_{3}$ was maintained at 1 Å/cycle. Hf, Zr and Al were deposited from Tetrakis(ethylmethylamido) hafnium (IV) (TEMAHf), tetrakis(ethylmethylamido) zirconium (IV) (TEMAZr) and trimethyl aluminum (TMA) precursors respectively. The top TiN electrode patterning was done by wet etching technique and a capacitor area of 100 ${\mathrm{\mu}}$m x 100 ${\mathrm{\mu}}$m was defined. The electrical characterization such as polarization-electric field (P-E) curve, current density-voltage curves of the as fabricated capacitors were measured using Precision LCII and keithley 4200 source meter respectively. Prior to measurement, rapid thermal annealing (RTA) of the capacitors was performed in N$_{2}$ ambient at 600 ˚C, 700~˚C, 800 ˚C and 900 ˚C.

## III. Results and Discussions

Fig. 1(a)-(d) shows the experimental P-E curves of the FM capacitors with and without the Al$_{2}$O$_{3}$ DE layer at RTA temperature of 600 ˚C - 900 ˚C respectively. The DE layer thickness was varied as 5 Å, 10 Å, 15 Å, 20 Å and 30 Å and the MFM capacitors without the DE layer was used as reference device. The variation of P$_{\mathrm{r}}$ for the aforesaid capacitors at different RTA temperature is shown in Fig. 2.

From Fig. 1 and Fig. 2, it can be observed that upon inserting Al$_{2}$O$_{3}$ DE layer on the top of the HZO layer in the MFM capacitor, there is a significant change in its ferroelectric property. The remanent polarization of the MFM capacitor increases for the insertion layer of 5 Å thickness and decreases thereafter. The MFM capacitor with 30 Å Al$_{2}$O$_{3}$ insertion layer was found to show no ferroelectricity. When the Al$_{2}$O$_{3}$ insertion layer is used in series with the HZO layer, it acts as a voltage divider and certain portion of the applied voltage is dropped across the Al$_{2}$O$_{3}$ insertion layer. Consequently, the applied field across the HZO layer decreases. Therefore, one of the reasons that the P$_{\mathrm{r}}$ decreases at the higher Al$_{2}$O$_{3}$ insertion layer thickness is the less applied electric field across the HZO layer due to the voltage drop across the Al$_{2}$O$_{3}$ insertion layer. However, when Al$_{2}$O$_{3}$ insertion layer thickness is 5 Å, it does not act as capacitive layer at such as low thickness, instead it acts as a leaky resistive layer and we believe the increase in P$_{\mathrm{r}}$ at lower Al$_{2}$O$_{3}$ insertion layer thickness is due to the leakage current flowing through it. It is worth to mention here that in case of MFM capacitor, the charges due to the spontaneous polarization is screened by the metal electrode. On the contrary, insertion of a dielectric layer in between the ferroelectric layer and the metal electrode results in unscreened charges which in turn leads to an internal field and depolarization field across the DE and FE layer respectively. As a result, the ferroelectricity in the FE layer gets suppressed. However, the insulating nature of the DE layer plays a very important role in defining the unscreened charges at the DE/FE interface. For thin dielectric layer, these unscreened charges can be compensated by the inflow of compensating charges due to the leakage current through the DE layer giving rise to full polarization switching of the FE layer. In contrast, at higher thickness the additional charge through leakage current is not possible, and ferroelectricity is suppressed. It was observed that the P$_{\mathrm{r}}$ of all the devices increases with increasing the annealing temperature. It can be further seen that the relative increment in P$_{\mathrm{r}}$ in case of DE/FE system as compared to that of reference HZO capacitors for thinner DE layer increases with increasing the annealing temperature. This might be due to two reasons,

Fig. 3. (a) The representative deconvoluted GIXRD spctra of the HZO films annealed at 600 $^{\mathrm{o}}$C, (b) the calculated o-phase ration of the different stacks.

(1) Higher annealing temperature results in better nucleation of the FE HZO layer resulting in the formation of more o-phase and thereby resulting in higher ferroelectricity.

(2) At higher annealing temperature the leakage through the thin DE layer can allow more compensating charges.

Further to study the variation of the o-phase with respect to Al$_{2}$O$_{3}$ thickness and annealing temperature GIXRD analysis of the different stacks were carried out. Although, it is difficult to accurately distinguish m-, o-, and t-phase in HZO film, the GIXRD spectra were deconvoluted assuming the peaks corresponding to two theta value of 28.54$^{\mathrm{o}}$, 30.40$^{\mathrm{o}}$, 30.80$^{\mathrm{o}}$ and 31.65$^{\mathrm{o}}$ to be of m[-111], o[111], t[011] and m[111] respectively (26). The o-phase of fraction of the films was then calculated based on the areal density of the peak in the deconvoulted spectra. The representative deconvoluted GIXRD spectra of the HZO films annealed at 600 $^{\mathrm{o}}$C is shown in Fig. 3(a) and the calculated o-phase ratio of the different stacks at are shown in Fig. 3(b) respectively. As can be seen from Fig. 3(b), the o-phase fraction of the films was found to increase with insertion of Al$_{2}$O$_{3}$ layer till a thickness of 5Å and decrease thereafter irrespective of the annealing temperature. This might be due to the variation of the crystallization of HZO films due to the presence of the Al$_{2}$O$_{3}$ layer. It was also observed that the o-phase fraction of the HZO films increases with increasing annealing temperature till 800 $^{\mathrm{o}}$C. This is assumed to be due to the fact that at higher annealing temperature more t-phase to o-phase conversion takes place. However, increasing the annealing temperature beyond 800 $^{\mathrm{o}}$C was found to result in lesser o-phase in the HZO films probably due to the degradation of the HZO layer at such higher annealing temperature. This can be also justified by the fact that at 900 $^{\mathrm{o}}$C annealing temperature, the HZO capacitors without Al$_{2}$O$_{3}$ interlayer was found to degrade completely [represented by a horizontal line in Fig. 1(d)]. The observed trend in the o-phase formation inside HZO films matches well with that of the observed experimental remanent polarization data.

The variation of E$_{\mathrm{c}}$ values of the MFM capacitors for all DE layer thickness at different RTA temperature is shown in Fig. 4. From Fig. 4, it can be observed that the E$_{\mathrm{c}}$ values of the capacitors increases with increasing the DE layer thickness. In case of DE/FE stack, the voltage applied across the capacitors gets divided and a significant amount of voltage drop takes place across the DE layer. This in turn increases the voltage required for the polarization switching of the FE layer resulting in the enhanced E$_{\mathrm{c}}$ value. It was also observed that the E$_{\mathrm{c}}$ values of the capacitors are reduced at higher annealing temperature. It has been reported that coercive field is related to the domain wall density inside the ferroelectric layer. Lesser ferroelectric domains lead to higher coercive field. Nucleation affects the domain formation, hysteresis loop and the slope of the hysteresis loop. A steeper P-E loop suggests fast change of the polarization and nucleation adjacent to the domain wall leads (27). We believe the lower E$_{\mathrm{c}}$ obtained in our study at higher annealing temperature is probably due to the formation of higher ferroelectric domains in the FE layer.

Fig. 4. Variation of E$_{\mathrm{c}}$ value for different DE layer thickness at RTA temperature of (a) 600 ˚C, (b) 700 ˚C, (c) 800 ˚C, (d) 900~˚C.

Fig. 5. J-V curve of the MFM capacitors with DE layer of different thickness at RTA temperature of (a) 600 ˚C, (b) 700~˚C, (c) 800 ˚C, (d) 900 ˚C.

In terms of effect of annealing temperature on device stability, all the MFM capacitors were found to be stable till 800 ˚C. However, when annealed at 900 ˚C, only MFM capacitors with Al$_{2}$O$_{3}$ insertion layer was found to show ferroelectric property and the reference device was found to be dead [represented by a horizontal line in Fig. 1(d)]. The J-V curves of the fabricated capacitors for different annealing temperature are shown in Fig. 5. From Fig. 5, it can be observed that the leakage current decreases with increasing the DE thickness. Also, leakage current of all the capacitors were found to increase with increasing annealing temperature. Especially, at 900 ˚C, the leakage current through the reference device were found to be severe enough to cause breakdown of the device.

## IV. CONCLUSIONS

In conclusion, we have elucidated the role of DE layer thickness and annealing temperature on the ferroelectric property of Al$_{2}$O$_{3}$/Hf$_{\mathrm{0.5}}$Zr$_{\mathrm{0.5}}$O$_{2}$ bilayer stack. The remanent polarization of Hf$_{\mathrm{0.5}}$Zr$_{\mathrm{0.5}}$O$_{2}$ was found to increase when a very thin layer of Al$_{2}$O$_{3}$ was incorporated due to the leakage assisted polarization switching. For higher DE thickness, the ferroelectricity was suppressed due to the depolarizing field resulted from the unscreened charges at the DE/FE interface. The addition of Al$_{2}$O$_{3}$ layer was also found to increase the thermal stability of the capacitors by reducing the leakage current. Despite the HZO capacitors being dead at annealing temperature beyond 800 ˚C, the DE/FE stack-based capacitors were found to demonstrate descent ferroelectricity.

### ACKNOWLEDGMENTS

This work was supported by the Korea Semiconductor Research Consortium Support Program for the development of the future semiconductor device under Grant No. 10067789. This work was also supported by Grant Nos. NRF-2019M3F3A1A02071969 and NRF- 2020M3F3A2A01081916. Also, this work was supported by Samsung Electronics.

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## Author

##### Dipjyoti Das

was born in Assam, India, in 1989.

He received his B.E. degree in Electronics and Tele-communication Engineering from Assam Engineering College, Gauhati University, Assam, India, and the Ph.D. degree in Organic Opto-electronic Devices from Indian Institute of Technology Guwahati, Assam, India in 2018.

He is currently a postdoctoral fellow in Electrical Engineering Department, Korea Advanced Institute of Science and Technology (KAIST).

His current research interests include high-k ferroelectric HZO capacitors, energy storage capacitors and neuromorphic engineering.

was born in 1984, India.

He received Ph.D degree from Indian Institute of Science (IISc), Bangalore in 2016.

He worked as Research associate at Dept. of Instrumentation & Applied Physics, Indian Institute of Science, Bangalore during 2016 and 2017.

Presently, he is working as Postdoctoral Research Fellow at School of Electrical Engineering, KAIST, South Korea.

His fields of interests are on ferroelectric memory devices including MFM capacitors, Ferroelectric Tunnel Junctions etc.

##### Sanghun Jeon

(M’03{--}SM’14) received the Ph.D. degree in electronic materials program from the Gwangju Institute of Science and Technology, Gwangju, South Korea, in 2003. In 2013, he joined Korea University, Sejong, South Korea.

Since 2018, he has been a Tenured Associate Professor with the School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea.