DoKyoung-Il1
KooYong-Seo1*
-
(Dept. of Electronics and Electrical Eng,. Dankook University)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Electrostatic discharge(ESD), high current driving capability, lateral insulated gate bipolar transistor (LIGBT), silicon controlled rectifiers(SCR)
I. INTRODUCTION
The degree of integration improves with the development of novel semiconductor process
technologies, resulting in reduced robustness to electrostatic discharge (ESD) in
terms of the reliability of integrated circuits (ICs). This is because of the decreased
thickness of the gate oxide film and the metal line at the junction depth. Damage
to internal ICs due to inflowing ESD accounts for approximately 30% of all defects,
which is a growing concern regarding the quality and reliability of semiconductors
(1,2).
The ESD protection circuit typically comprises input/output (I/O) and power clamps.
The gate-ground n-channel MOSFT (GGNMOS), which is the most widely used ESD clamp,
has various applications owing to its excellent snapback characteristics. However,
the GGNMOS should be designed with a multi-finger, stacked configuration to improve
its current driving ability and optimize the target voltage, which requires a larger
area for the ESD protection circuit. Furthermore, silicon controlled rectifiers (SCR)
has an excellent current driving ability owing to the latch operation of two parasitic
bipolar transistors that are NPN and PNP. However, because conventional SCR has a
high trigger voltage of approximately 17-20 V and a very low holding voltage owing
to a high avalanche breakdown voltage generated between well regions, conventional
SCR requires optimization of the electrical characteristics through circuit addition
or area increase prior to its application to actual ICs (3,4). Furthermore, because an ESD has positive or negative charge polarity, it can have
a total of five types of discharge modes for VDD, VSS, and pads, depending on the
polarity (PD, ND, PS, NS, and DS). In addition, conventional ESD clamps based on GGNMOS
and SCR are vulnerable to an ESD with negative charge characteristics because of their
unidirectional characteristics, and the whole-chip ESD protection circuit comprises
two clamps in consideration of the polarity of each ESD mode (5-7). Therefore, an ESD protection circuit comprising clamps having unidirectional characteristics
occupies a relatively large area, which is a growing concern in applications requiring
high ESD robustness in a small chip area. To address this issue, this study proposed
and fabricated an all-directional whole-chip ESD protection circuit design, including
input/output (I/O) and power clamps.
II. PROPOSED ESD PROTECTION CIRCUIT
Fig. 1. Cross sectional view of conventional ESD clamps (a) GGNMOS, (b) SCR.
Fig. 1 is a cross-sectional view of conventional GGNMOS and SCR together with the proposed
ESD clamps. Conventional SCR operates owing to the latch mode of two parasitic bipolar
PNP and NPN transistors possessing an excellent current driving ability compared with
GGNMOS. However, the SCR-based I/O ESD clamp is as extremely vulnerable as is the
GGNMOS because the clamp forms the discharge path of the ESD current only with the
diode generated between the N- and P-well regions when an ESD with negative charge
characteristics is applied. Furthermore, when this type of clamp is used as a power
clamp that must have a relatively large operating area, the area must be increased
by implementing structural improvements or introducing additional circuits owing to
the significantly low holding voltage of SCR
(8,9).
The proposed whole-chip ESD protection circuit comprises an SCR-based I/O clamp with
bidirectional characteristics and a lateral insulated gate bipolar transistor (LIGBT)-based
power clamp, as shown in Fig. 2.
Fig. 2. Cross sectional view of proposed (a) SCR-based I/O ESD clamp and LIGBT-based
power ESD clamp.
The proposed I/O ESD clamp shown in
Fig. 2(a) has bidirectional characteristics owing to its symmetrical structure, and its operation
principle is as follows: When a forward ESD pulse is applied to Terminal A, the potential
of the N-well region in the middle rises, and when the threshold is reached, an avalanche
breakdown with the P+ bridge region on the right occurs. The hole current that occurs
owing to the generated electron hole pair (EHP) flows through the P-well region on
the right and forms a forward junction with the N+ region on the right. This process
turns on the parasitic bipolar NPN and PNP transistors (Q1 and Q2).
Fig. 3. Whole chip ESD protection circuit with (a) one-directional, (b) dual-directional
characteristics.
Furthermore, the PMOS structure is inserted in the middle, thereby lowering the avalanche
breakdown point and further reducing the trigger voltage by minimizing the base of
the transistor (Q1) to the gate region. In addition, each P well region includes a
P+ floating region, which reduces the emitter injection efficiency of the NPN parasitic
bipolar transistor to improve the holding voltage characteristics. When reverse ESD
is applied, parasitic bipolar transistors (Q1 and Q3) are operated similarly, forming
a similar ESD discharge path.
Fig. 3 shows the circuit diagram and four characteristics of the proposed bidirectional
ESD protection circuit at the input unit, which can utilize four ESD discharge modes
(PD, ND, NS, and PS) with two clamps in discharge.
Fig. 2(b) shows the proposed LIGBT-based power ESD clamp. Power ESD clamps must have a substantially
high holding voltage for a relatively high operating voltage and latch-up immunity;
in addition, they also require relatively high ESD robustness for the reliability
of electronic devices. The proposed LIGBT has a double-emitter and includes an N+
floating region. In the normal operating region, the power clamp does not operate
owing to the reverse junction between the P-well and the deep N-well. When an ESD
surge is injected into the P+ collector region, a punch-through occurs and a current
is formed in the two emitter regions. The formed Hall current induces forward bias
with the two N+ emitter regions and further forms two SCR paths. In contrast with
conventional SCR, the base region of the parasitic bipolar transistor in the proposed
clamp is significantly long, and the forward feedback is relatively low because of
the N+ floating region. As a result, the proposed clamp allows a high holding voltage,
and two parallel SCR paths allow better ESD robustness. Thus, the proposed structure
has characteristics that are highly suitable for its application as a power ESD clamp.
The proposed I/O and power clamps constitute a whole-chip ESD protection circuit,
and
Fig. 4 shows the equivalent circuit. The equivalent circuit considers one input unit and
two output units and composes an ESD protection circuit with five clamps in total.
Thus, the proposed whole-chip ESD protection circuit possesses excellent electrical
characteristics and area efficiency in comparison to a conventional ESD protection
circuit comprising nine clamps.
III. MEASUREMENT RESULTS AND DISCUSSION
1. TLP Measurement
The proposed ESD clamps and comparison devices were fabricated using a 0.18 um process.
Furthermore, this study applied a TLP measurement method with a 10 ns rising time
and a 100 ns pulse width to verify the electrical characteristics (9). The TLP is typically represented as a current versus voltage plot showing the turn-on
point parameters (Vt1, It1) of the snapback protection structure. In addition, the
TLP I-V curve can easily reveal the on-resistance and secondary breakdown current.
The configuration of the TLP system used in the measurement is shown in Fig. 5. Fig. 6 shows the layout and fabrication results of the proposed ESD clamp, and Fig. 7 shows the arrangement according to the configuration of a whole-chip ESD protection
circuit. The TLP measurement results in Fig. 8 show that the proposed ESD I/O clamp has a 12.4 V trigger voltage, a 6.8 V holding
voltage, and a secondary trigger current of 8.1 A. The proposed I/O clamp has excellent
snapback characteristics in comparison to a conventional SCR having a 19.8 V trigger
voltage and a 2.4 V holding voltage.
Fig. 4. Equivalent circuit of (a) a typical whole-chip ESD protection circuit (GGNMOS-based),
(b) the proposed whole-chip protection circuit.
Fig. 5. The experiment environment for the TLP measurement.
Fig. 6. Layout of the proposed (a) I/O clamp, (b) power clamp.
Fig. 7. Placement of proposed ESD clamps for power lines and internal circuits.
It also has a higher secondary trigger current of 4.1 A compared with that of GGNMOS.
In addition, unlike a conventional ESD protection circuit comprising two I/O clamps
for positive and negative ESD surges, the proposed I/O clamp forms a similar discharge
path for positive and negative ESD surges with a single structure because of its symmetrical
structure. Furthermore, the proposed whole-chip ESD protection circuit includes a
power clamp with a 21.5 V trigger voltage and a 16.1 V holding voltage, and the proposed
power clamp has a very high holding voltage and a very high secondary trigger current
of 9.7 A.
Table 1 summarizes the electrical characteristics of the proposed clamp and conventional
ESD protection devices.
Fig. 8. TLP-IV curve of the proposed ESD protection circuit by ESD discharge mode
(a) NS, PS, ND, and PD, (b) DS modes.
2. Optimization of Electrical Properties
Fig. 9 shows a TLP I-V characteristic curve for each design variable of the proposed I/O
and power ESD clamp. This study selected two design variables, D1 and D2, for the
I/O clamps with bidirectional characteristics (10,11). D1 represents the length of the two central P+ bridge regions on the I/O clamp,
which can be used to adjust the effective base region of the parasitic NPN bipolar
transistor (Q3). D2 is the length of the gate region and it can simultaneously increase
the effective base regions of the two PNP parasitic bipolar transistors (Q1 and Q2).
Fig. 2(a) shows that the holding voltage increases to 14.8 V as D1 changes from 7 to 21 µm,
and Fig. 2(b) shows that the holding voltage of the I/O clamp increases up to 10.7 V when D2 increases
from 2 to 8 µm. The design variable D3 represents the length of the N+ floating region
on the power clamp, which can be used to control the emitter injection efficiency
of two parasitic PNP bipolar transistors. Fig. 9(c) shows that the holding voltage of the power clamp increases up to 23.1 V when D3
increases from 8 to 18 µm. Table 2 summarizes the changes in electrical properties according to design variables.
Fig. 9. TLP measurement results according to changes in design variables (a) D1, (b)
D2, (c) D3.
Table 1. Summary of the electrical characteristics of the proposed clamp and conventional
ESD clamps
|
Structure
|
Electrical Characteristics
|
|
VT[V]
|
VH[V]
|
IT2[A]
|
Direction
|
|
SCR
|
19.9
|
2.1
|
8.9
|
One
|
|
GGNMOS
|
9.4
|
6.1
|
4.0
|
One
|
|
2-Stacked
GGNMOS
|
18.0
|
12.4
|
3.6
|
One
|
|
Proposed
I/O ESD Clamp
|
12.4
|
6.8
|
8.1
|
Dual
|
|
Proposed
Power ESD Clamp
|
21.5
|
16.1
|
9.7
|
One
|
Thus, the proposed whole-chip ESD protection circuit can optimize the electrical characteristics
as appropriate for the ESD design window by considering the target protection voltage
and the gate oxide breakdown point using design variables D1, D2, and D3.
3. Measurement of ESD Robustness
This study measured HBM and MM to verify the ESD robustness of the proposed whole-chip
ESD protection circuit. Fig. 10 shows the experimental environment used to measure ESD robustness. To measure the
ESD robustness, a 370 curve tracer and an ESS-6008 pulse generator were used. The
ESD robustness was evaluated by considering all ESD discharge modes combined with
VDD, VSS, and I/O pads, and the results are outlined in Table 3. The proposed ESD protection circuit has excellent robustness exceeding 8 kV HBM
and 800 V MM for all ESD modes.
Fig. 10. The ESD robustness experiment environment.
Table 2. Summary of electrical characteristics of the proposed whole-chip ESD protection
circuit according to the design parameters (D1-D3)
|
Structure
|
Design Parameter
[um]
|
Electrical Characteristics
|
|
VT[V]
|
VH[V]
|
IT2[A]
|
|
The Proposed
I/O ESD Clamp
|
D1
|
7
|
12.4
|
6.8
|
8.1
|
|
14
|
15.1
|
11.1
|
6.7
|
|
21
|
17.2
|
14.8
|
6.1
|
|
D2
|
2
|
12.4
|
6.8
|
8.1
|
|
5
|
12.9
|
7.9
|
6.5
|
|
8
|
13.2
|
10.7
|
6.1
|
|
The Proposed
Power ESD Clamp
|
D3
|
8
|
21.5
|
16.1
|
9.7
|
|
13
|
22.2
|
17.7
|
8.4
|
|
18
|
23.1
|
20.0
|
7.3
|
Table 3. Summary of ESD Robustness measurement results by ESD discharge mode
|
ESD MODE
|
ESD Robustness
|
|
HBM [V]
|
MM [V]
|
|
ND
|
> 8000
|
> 800
|
|
PD
|
> 8000
|
> 800
|
|
PS
|
> 8000
|
> 800
|
|
NS
|
> 8000
|
> 800
|
|
DS
|
> 8000
|
> 800
|
IV. CONCLUSIONS
This paper proposed the design of an all-directional whole-chip ESD protection circuit.
The proposed all-directional SCR-based I/O ESD clamp has excellent area efficiency
owing to its bi-directional characteristics; in addition, it provides an ESD discharge
path with a high holding voltage for each ESD stress mode (PD, ND, PS, and NS). Furthermore,
the LIGBT-based ESD power clamp provides a discharge path for VDD-VSS (DS) and possesses
excellent latch-up immunity to power a clamp voltage. Moreover, design variables D1,
D2, and D3 can be used to optimize the electrical characteristics of the I/O and power
clamp according to the target voltage. The proposed all-directional whole-chip ESD
protection circuit is fabricated using a 0.18 µm BCD process, and its electrical characteristics
are verified through a TLP system and an ESD pulse generator. The proposed all-directional
whole-chip ESD protection circuit is highly robust, requiring 8 kV HBM and 800 V MM
for all ESD modes. Therefore, the proposed all-directional whole-chip ESD protection
circuit can contribute toward improving the reliability of integrated circuits.
ACKNOWLEDGMENTS
This work was supported by Korea Evaluation Institute of Industrial Technology(KEIT)
grant funded by the Ministry of Trade, Industry & Energy (20009739, “Development of
Low Noise 3phase BLDC Motor Drive SoC for Electric Vehicles with Power Switch and
Hall Sensors” and the MSIT(Ministry of Science and ICT), Korea, under the ITRC(Information
Technology Research Center) support program(IITP-2018-0-01421) supervised by the IITP(Institute
for Information & communications Technology Promotion)
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Author
Kyoung-Il Do was born in Seoul, Republic of Korea, in 1989.
He was M.S and PhD.-course since 2016 in Electronics and Electrical Engi-neering,
Dankook University.
His current research interests include electrostatic discharge (ESD) protection circuit
design and semiconductor devices, such as power BJTs, LDMOSs, and IGBTs; and electrostatic
discharge (ESD) protection circuit design.
received the BS, MS. and Ph.D. degrees in the Department of Electronic Engineering from Sogang University, Seoul, Rep. of Korea, in 1981, 1983 and 1992, respectively. From 1983 to 1993, He had worked at Electronics Tele-communications Research Institute as senior researcher. In 2009, He joined the Department of Electronics and Electrical Engineering, Dankook University as a Professor. His research interests include electrostatic discharge (ESD) protection circuit design, silicon carbide(SIC) power device, high-efficiency power management integrated circuits(PMICs).