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  1. (School of Electrical and Electronic Engineering, Hongik University, Seoul, 04066, Korea)
  2. (Department of Electrical and Computer Engineering, Seoul National University, Seoul 151-744, Korea)

AlGaN/GaN heterojunction, p-GaN gate, selective plasma etching


Gallium nitride (GaN) is a wide energy bandgap material with high breakdown field and high electron mobility, which can overcome the limitations of conventional Si-based power semiconductor devices (1). AlGaN/GaN heterojunctions have two-dimensional electron gas (2DEG) channels with high carrier densities enabled by the spontaneous and piezoelectric polarization effects (2). However, these strong polarization effects cause difficulties when implementing the enhancement-mode (E-mode) operations. Several methods have been developed for E-mode operations, including p-GaN/AlGaN/GaN, recessed metal–insulator–semiconductor (MIS) gate, and thin-AlGaN/GaN structures (3-5), among which the p-GaN gated AlGaN/GaN heterojunction field-effect transistors (HFETs) have been commercialized successfully.

The most important process step in the fabrication of the p-GaN gated AlGaN/GaN HFET is the etching process for the p-GaN layer outside the gate region; during this step, not only must the p-GaN etch depth be controlled precisely but the plasma-induced damage must also be minimized. Because the thickness of the AlGaN barrier layer is very thin, even a small amount of over-etching of the AlGaN layer and/or plasma damage would reduce the current density significantly owing to the reduced 2DEG density. While a conventional time-controlled etching process or an atomic layer etching process can be utilized to etch the p-GaN layer (6,7), a selective etching process between the p-GaN and AlGaN is highly recommended from the point of view of process reproducibility. A high selectivity was previously reported between GaN and AlGaN employing inductively coupled plasma (ICP) etching using Cl2/N2/O2 or Cl2/Ar/O2 gas mixtures where adding O2 formed an etch-resistive oxide layer on the AlGaN surface (8-10). However, a high self-bias voltage required to achieve the high selectivity would cause plasma induced damage at the surface. Since the AlGaN barrier layer under the p-GaN layer is very thin, the plasma damage caused during the selective etching process plays a critical role in device characteristics. In order to minimize such surface damage and over-etching issues, we proposed a two-step etching process to etch the p-GaN layer, wherein the p-GaN layer was first partially etched using a low damage BCl3/Cl2 nonselective etching process and then the remaining thin p-GaN layer was etched using an optimized Cl2/N2/O2 selective process to reduce the over-etching time.


1. Optimization of Selective Etching Process

The selective etching process used in this work involved an oxidation reaction mechanism. Adding the O2 gas into the Cl2/N2 gas mixture oxidizes the GaN or AlGaN surface, and the strong binding energy of the oxidized AlGaN then stops the etching process. The binding energy of Al-O is higher than those of Al-N and Ga-N (9). In addition, the Ga-O bonding is chemically more reactive than the Al-O bonding (11), which also helps the selective etching process.

Two epitaxial structures were used for the selectivity measurements: one with a p-GaN layer on the top surface and the other with an AlGaN layer on the top surface. The etching process was performed using an Oxford Plasmalab 100 ICP system with a Cl2/N2/O2 gas mixture. The gas flow rates of Cl2/N2 were fixed at 40/10 sccm, while the O2 flow rate, chamber pressure, and chuck temperature were varied in the ranges of 0–4 sccm, 5–25 mTorr, and 5–60°C, respectively.

Fig. 1. Etch rates and selectivities between p-GaN and Al0.24Ga0.76N as functions of (a) chamber pressure, (b) O2 gas flow rate, (c) chamber temperature.



The etch rates and selectivities as functions of the chamber pressure are shown in Fig. 1(a), where the O2 flow rate, source radio frequency (RF) power, bias RF power, and chuck temperature are 2.5 sccm, 1750 W, 25 W, and 20°C, respectively. The selectivity is defined as the ratio of the p-GaN etch rate to the AlGaN etch rate. The etch rates for both p-GaN and AlGaN were observed to decrease as the chamber pressure increased. A selectivity of 23:1 (for p-GaN:AlGaN) was achieved at a chamber pressure of 20 mTorr, where the self-bias voltage was 213 V and the etch rates for p-GaN and AlGaN were 2.3 and 0.1 Å/s, respectively.

The etch rates and selectivities as the function of the O2 flow rate are shown in Fig. 1(b), where the chamber pressure, source RF power, bias RF power, and chuck temperature are 20 mTorr, 1750 W, 25 W, and 20°C, respectively. The etch rates for both p-GaN and AlGaN were observed to decrease as the O2 flow rate increased up to 2 sccm, which was associated with more oxidation at the surface. The etch rate for AlGaN did not decrease further at O2 flow rates of >2 sccm. For the O2 flow rate of 2 sccm, the etch rates for the p-GaN and AlGaN were 4 and 0.1 Å/s, respectively, resulting in a selectivity of 40:1 (for p-GaN:AlGaN). The self-bias voltage was recorded as 224 V.

The etch rates and selectivities as functions of the chamber temperature are shown in Fig. 1(c), where the chamber pressure, the O2 flow rate, source RF power, and bias RF power are 20 mTorr, 2 sccm, 2000 W, and 25 W, respectively. A relatively higher source RF power was used in this case because of the unstable matching issues of the system at elevated temperatures. It should be noted that the etch rates for the p-GaN increased as the chamber temperature increased, whereas the etch rates for the AlGaN decreased with increase in chamber temperature. Owing to this contrasting behavior, the selectivities increased as the chamber temperature increased. However, the etch rate became saturated at a chamber temperature of 60°C. The highest selectivity recorded was 53:1 (for p-GaN:AlGaN) at a chamber temperature of 60°C, where the etch rates for p-GaN and AlGaN were 3.6 and 0.068 Å/s, respectively, and the self-bias voltage was 198 V.

2. Fabrication of p-GaN Gated AlGaN/GaN HFET

The epitaxial structure consisted of a 70 nm p-GaN layer, a 15 nm Al0.2Ga0.8N layer, a 320 nm i-GaN layer, and a 3.6 µm GaN buffer layer on a Si(111) substrate. After cleaning with solvent and acid, the p-GaN layer outside the gate region was etched via a two-step plasma etching process. As the self-bias voltage of the optimized selective etching process was much higher than that of the low damage BCl3/Cl2 etching process used here, the two-step etching process was designed to etch the p-GaN layer. First, the p-GaN layer was partially etched using the low damage BCl3/Cl2 etching process with an etch depth target of 50 nm. The self-bias voltage for this low damage process was 20 V. Then, the remaining p-GaN layer was etched using the optimized Cl2/N¬2/O2 selective etching process to minimize the over-etching time. Because the remaining p-GaN layer was very thin, the over-etching time could be reduced significantly in comparison with a single-step selective etching process. Therefore, any plasma induced damage at the etched AlGaN surface can be minimized by the two-step etching process as well. After the selective etching process, the oxidized surface was treated by a buffered oxide etchand solution, and the sample was annealed at 500°C for 5 min in an N2 ambient for damage recovery. The ohmic contacts were formed by a fully recessed Au-free ohmic process, and the ohmic metal stack of Ti/Al/TiN was annealed at 550°C for 1 min in an N2 ambient. Mesa isolation was then carried out by the BCl3/Cl2 based plasma etching. TiN metal stacks were evaporated for the gate and pad electrodes, and the surface was passivated with a 180 nm SiN¬x film using ICP chemical vapor deposition. A source-connected field-plate was formed using a TiN/Ti metal stack, and the source-to-gate distance, p-GaN gate length, and gate-to-drain distance were fabricated as 2, 4, and 11 μm, respectively, where the gate length inside the p-GaN region was 2 μm. The cross-sectional schematic of the p-GaN gated AlGaN/ GaN HFET is shown in Fig. 2.

Fig. 2. Cross-sectional schematic of the p-GaN gated AlGaN/GaN E-mode HFET.



To validate the selective etching process, capacitance–voltage (C-V) measurements were conducted using a C-V test-element-group pattern fabricated on the AlGaN surface where the p-GaN layer was etched. Fig. 3(a) shows the electron distribution versus the depth derived from the C-V characteristics (12). The thickness of the AlGaN layer extracted from the C-V characteristics is 15 nm, which is in agreement with the initial AlGaN barrier thickness. Data from an atomic force microscopic image in Fig. 3(b) also confirmed that the etch depth was the same as that of the p-GaN layer.

Fig. 3. (a) Carrier distribution versus AlGaN depth for the etched region as derived from C-V measurements, (b) atomic force microscopy data for the p-GaN etched region.


The transfer current–voltage (I-V) characteristics of the fabricated device were measured at Vds = 10 V. As shown in Fig. 4(a), the fabricated p-GaN gated HFET exhibited excellent normally-off E-mode operation with negligible hysteresis characteristics. A threshold voltage of 2.45 V, an on/off ratio of ~109, and a maximum drain current density (Id.max) of 182 mA/mm at Vgs = 8 V were achieved. Further, the off-state drain leakage current was < 10-10 A/mm.

The output current–voltage characteristics are shown in Fig. 4(b), from which the specific on-resistance extracted at Vds = 2 V was 5.55 mΩ·cm2 by taking into account the intrinsic channel region between the source and drain.

Fig. 4. (a) Transfer characteristics, (b) output current–voltage characteristics of the fabricated p-GaN gated AlGaN/GaN HFET.


To evaluate the trapping effects, the current collapse phenomenon was investigated by pulsed measurements with a pulse width of 200 ns and a period of 1 ms. The pulsed characteristics with different quiescent drain bias voltages are shown in Fig. 5, where the quiescent gate bias voltage was fixed at 0 V. Owing to the field plate, only a little current collapse was observed to occur under the short pulse conditions.

Fig. 5. Pulsed I-V characteristics of the fabricated p-GaN gated AlGaN/GaN HFET.


Off-state breakdown voltage was measured with Vgs = 0 V, using the Keithley 2410 and 2651A sourcemeters. As shown in Fig. 6, a slight increase in the leakage current and no breakdown were observed up to Vds = 1100 V, which was the limit for the equipment.

Fig. 6. Off-state breakdown characteristics of the fabricated p-GaN gated AlGaN/GaN HFET.



A selective p-GaN etching process was developed in this study using a Cl2/N2/O2 based ICP etching scheme. A selectivity of 53:1 (for p-GaN/AlGaN) was achieved using the following process conditions: gas flow rates of Cl2/N2/O2 = 40/10/2 sccm, source RF power of 2000 W, bias RF power of 25 W, and chuck temperature of 60°C. To minimize the plasma induced damage at the etched surface, a two-step etching process was utilized to fabricate the p-GaN gated AlGaN/GaN HFET, where the upper p-GaN layer was etched using a low damage nonselective etching process and the remaining thin p-GaN layer was etched via a selective etching process developed in this work. The fabricated p-GaN gated AlGaN/GaN HFET exhibited excellent E-mode operation with a high threshold voltage of 2.45 V, low specific on-resistance of 5.55 mΩ·cm2, and high off-state breakdown voltage of > 1100 V. Thus, it is suggested that the two-step etching process proposed in this work can be utilized for p-GaN gated AlGaN/GaN HFET fabrication to not only minimize etching damage but also improve process reproducibility.


This work was supported by the Basic Science Research Program (No. 2015R1A6A1A03031833 and No. 2019R1A2C1008894) and Material Component Development Program of MOTIE/KEIT (10080736).

We thank Tae-Hyun Kim, Jun-Hyeok Yim, and Chan-Hee Jang of Hongik University, who provided the fabrication support for this research.


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Won-Ho Jang

Won-Ho Jang received the B.S. and M.S. degrees in Electronic and Electrical Engineering from Hongik University, Seoul, Korea, in 2016 and 2018, respectively.

He is currently pursuing the Ph.D. degree at Hongik University.

His research intereswnsts include the analysis of Gallium nitride devices.

Kwang-Seok Seo

Kwang-Seok Seo received the B.S. in electrical and computer engi-neering at Seoul National University, Seoul, Korea, in 1976, M.S. degree in electrical engineering at Korea Advanced Institute of Science and Technology in 1978.

And Ph.D. degree in electrical engineering from the University of Michigan Ann Arbor, USA, in 1987.

He was a senior research engineer at the Korea Institute of Electronics Technology until 1982.

He was a Postdoctoral Research Associate at the IBM T.J. Watson Research Center until 1988.

He is currently a Professor with the department of electrical and computer engineering,Seoul National University, Seoul, Republic of Korea.

His research interests include high speed device physics and technology, compound semiconductor devices.

Ho-Young Cha

Ho-Young Cha received the B.S. and M.S. degrees in Electrical Engineering from the Seoul National University, Seoul, Korea, in 1996 and 1999, respectively, and the Ph.D. degree in Electrical and Computer Engineering from Cornell University, Ithaca, NY, in 2004.

He was a Postdoctoral Research Associate with Cornell University until 2005, where he focused on the design and fabrication of wide bandgap semiconductor devices.

He was with the General Electric Global Research Center, Niskayuna, NY, from 2005 to 2007, developing wide-bandgap semiconductor sensors and high-power devices.

Since 2007, he is currently Professor in the School of Electronic and Electrical Engineering.

His research interests include wide-bandgap semiconductor devices.

He has authored over 100 publications in his research area.