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a-IGZO TFT, channel defect, DOS, c-t, carrier lifetime


With the advent of the Internet-of-Things (IOT), the importance of flexible display-based application compatibility technology is increasing, and the need for wearable devices in the medical field is increasing (1). Recently, a-IGZO has been attracting attention as a good material for next-generation flexible TFTs because it can be processed at low temperatures, has good uniformity, and exhibits high field effect mobility (2). To improve the performance of IGZO TFTs, research has been conducted to improve the film quality characteristics such as changing the oxygen partial pressure ratio and changing the IGZO composition ratio (3). However, if these process conditions change, physical analysis such as X-ray photoelectron spectroscopy (XPS) and photoluminescence spectroscopy (PL) is performed to confirm the oxygen vacancy (V$_{\mathrm{o}}$ and V$_{\mathrm{o}}$$^{2+}$) and metastable defects ($p p \pi^{*}$) of the IGZO layer (4,5) . This study proposes a method that can easily and quickly check the channel characteristics of IGZO TFTs electrically without physical analysis. To confirm the consistency of the experimental results, TFTs with two different OFRs were used in the experiments with the IGZO sputtering process. The interfacial properties of IGZO and the insulator were confirmed by DOS extraction using the PECCS method. The channel region characteristics of the IGZO were confirmed through the minority carrier lifetime extracted through c-t measurements. The consistency of the analysis method was verified by confirming the final measurement results with the results reported through existing physical analysis methods.

Fig. 1. Schematic image of a flexible a-IGZO TFT.



Fig. 1 is the schematic cross section of the top gate a-IGZO TFT used in the experiment. 300 nm of SiO$_{2}$ was deposited as a buffer layer on the polyimide (PI) substrate. The 50 nm thick active layer (a-IGZO) was formed by sputtering using an alloy target (In$_{2}$O$_{3}$: Ga$_{2}$O$_{3}$: ZnO =1: 1: 1) at 200 °C. During the sputtering process, the gas flow rates were Ar: O$_{2}$ = 30:20 sccm (O-Poor) and 30:60 sccm (O-Rich). 50 nm-SiO$_{2}$ film used in the gate insulator was grown by atomic layer deposition (ALD) using tris(dimethylamino)-silane as a silicon precursor and oxygen plasma as an oxidant. ALD processes were carried out at a temperature of 250 ℃. Ti/Au (20 nm/30 nm) source/drain electrodes were deposited by sputtering and patterned by dry etching. The gate electrode of Ti/Pt (4 nm/8 nm) was first deposited by sputtering. The final step was annealing at 300 °C in a vacuum for 1h. Finally, IGZO TFTs with different OFR were produced. The structure of the MOS capacitor used in the experiment is PI/buffer/IGZO/SiO$_{2}$/gate. For the TFT, a W/L = 10 $\mu \mathrm{m}$/10 $\mu \mathrm{m}$ device was used, and for the MOS capacitor, a 200 $\mu \mathrm{m}$ /200 $\mu \mathrm{m}$ device was used. The electrical parameters were obtained from I-V and C-V measurements. The PECCS was measured by examining the monochromatic light at intervals of 5 nm, from 350 nm to 700 nm on the IGZO TFTs. The interface density of states [(DOS); D$_{\mathrm{it}}$] according to the incident photon energy (ε) can be extracted from Eq. (1)(6):

$$ D_{i t}\left(E_{c}-\varepsilon\right)=\frac{C_{o x}}{q} \times \frac{\partial V_{t h}(\varepsilon)}{\partial \varepsilon} $$

where C$_{\mathrm{ox}}$ is the capacitance of the gate insulator per unit area, q is the electron charge, and E$_{\mathrm{c}}$ is the conduction band minimum. Using the c-t method, the generation lifetime was measured at 100 kHz.


Fig. 2 shows the results of the I-V measurements of TFTs with different OFRs. Table 1 shows the parameters extracted from the I-V measurement results. The subthreshold swing (SS) indicates the gate voltage needed to increase the drain current by a factor of 10 times, and can be obtained by analyzing the subthreshold region. The field effect mobility ($\mu$$_{\mathrm{FE}}$) was extracted from the transfer curve in the linear regime (V$_{\mathrm{D}}$=0.1 V), and is related to the transconductance ($g_{m}$) at a low drain voltage as obtained using Eq. (2).

$$ \mu_{F E}=\frac{g_{m}}{C_{o x} \times W / L^{\times V_{D}}} $$

Similar to the results of previous papers, $\mathrm{V}_{\mathrm{th}}$ shifted positively as the OFR increased, and the $\mu_{F E}$, SS, and current ratio ($\mathrm{I}_{\mathrm{on}} / \mathrm{I}_{\mathrm{O} \mathrm{ff}}$) did not change significantly (3). The reason for the $\mathrm{V}_{\mathrm{th}}$ positive shift is that as the OFR increases, more oxygen vacancies are compensated for by the injected oxygen and the conductivity of the channel is lowered, leading to a decrease in carrier concentration.

Fig. 2. Transfer curves of IGZO TFTs according to OFRs.


Table 1. Electrical parameters of a-IGZO TFTs with different OFRs.


$\mathrm{V}_{\mathrm{th}}$ (V)

$ \mu_{\mathrm{FE}}\left(\mathrm{cm}^{2} / \mathrm{V} \mathrm{s}\right) $

SS (V/dec)

$\mathrm{I}_{\mathrm{on}} / \mathrm{I}_{\mathrm{O} \mathrm{ff}}$











Fig. 3 shows the carrier concentration according to the C-V measurement results of the MOS capacitor and the depth extracted from the C-V data. Through the C-V measurement results, it was confirmed that the higher the OFR, the more that $\mathrm{V}_{\mathrm{FB}}$ shifts positively in accordance with the TFT's $\mathrm{V}_{\mathrm{th}}$ shift trend. The inversion capacitance

Fig. 3. (a) C-V plot of the MOS capacitors, (b) Carrier concentration according to IGZO depth (nm).


of the O-poor rate was increased because the carrier concentration of a-IGZO was increased. The total capacitance of the MOS capacitor is determined based on the electron capacitance ($\mathrm{C}_{\mathrm{n}}$), hole capacitance ($\mathrm{C}_{\mathrm{p}}$), interface trap capacitance ($\mathrm{C}_{\mathrm{it}}$), and space charge region bulk capacitance ($\mathrm{C}_{\mathrm{b}}$). However, under the inversion bias condition, electrons move away from the surface, where holes and interface traps are only present in small amounts that do not respond at high frequency, so the effects of $\mathrm{C}_{\mathrm{n}}$, $\mathrm{C}_{\mathrm{p}}$, and $\mathrm{C}_{\mathrm{it}}$ are ignored. Therefore, the influences of $\mathrm{C}_{\mathrm{ox}}$ and $\mathrm{C}_{\mathrm{b}}$ are dominant relative to the total capacitance and can be expressed as Eq. (3)(7):

$$ \begin{array}{l} C_{\text {total}}=\frac{1}{1 / C_{\text {ox}}+1 /\left(C_{n}+C_{p}+C_{i t}+C_{b}\right)} \approx \frac{C_{\alpha x} C_{b}}{C_{\alpha x}+C_{b}} \\ C_{b}=\frac{\kappa_{s} \varepsilon_{0}}{W_{i n v}} \end{array} $$

where K$_{\mathrm{s}}$ is the semiconductor dielectric constant, $\varepsilon_{0}$ is the permittivity of free space, and $\mathrm{W}_{{inv }}$ is the inversion space-charge region width. $\mathrm{W}_{{inv }}$ decreases due to the electrons originating from the increased oxygen vacancy of the O-poor. Fig. 3(b) shows that the carrier concentration increased with a lower OFR. It can be seen that as the oxygen supply decreases, the oxygen vacancy increases, and thus the carrier concentration increases.

Fig. 4 shows the PECCS measurement results of TFTs with different OFRs. The neutral, ionized oxygen vacancy and metastable ($p p \pi^{*}$) defects of IGZO exist in the E$_{\mathrm{v}}$ + 1.1 eV, E$_{\mathrm{c}}$ - 0.05 eV, and E$_{\mathrm{v}}$ + 0.15 eV energy level states (1). It was confirmed that as the OFR increased, the oxygen vacancy decreased and the O-O bond increased. The DOS extracted through PECCS was identical to previously reported XPS results (4). Through these results, it is possible to identify the cause of the $\mathrm{V}_{\mathrm{th}}$ positive shift of the O-rich TFTs in the $\mathrm{I}_{\mathrm{D}}-\mathrm{V}_{\mathrm{G}}$ plot and the

Fig. 4. DOS in IGZO TFTs, extracted by photoexcited charge collection spectroscopy.


Fig. 5. (a) C-V and c-t behavior of bias applied to MOS capacitors by deep depletion, (b) Zerbst plot.


increase of the inversion capacitance value of the O-poor in the C-V curve.

Fig. 5(a) shows the C-V and c-t behavior in the deep depletion state of a bias (±5 V) applied MOS capacitor. The generation lifetime measurement taken using the c-t method relies on the fact that the IGZO channel reaches the deep depletion state when a momentary reversal voltage is applied. Deep depletion is formed in the channel region when the device is switched to the inversion voltage momentarily after the accumulation voltage is applied. Over time, electron hole pairs (EHP) generation occurs from impurities in the IGZO (oxygen vacancy defect), and as the number of majority carriers charged in the capacitor increases, the reverse capacitance (C$_{\mathrm{inv}}$) gradually recovers, leading to state C. The recovery time (t$_{\mathrm{f}}$) in the c-t plot is determined by the amount of EHP in IGZO. The recovery time of the O-poor TFT appeared short, which means that more defects are distributed in the channel region. As such the generation lifetime ($\tau_{g}$), defined as Eq. (4), can be measured via c-t characterization (7):

$$ \tau_{g}=\frac{2 n_{i} C_{o x}}{N_{A} C_{i n v} \text { slope }} $$

where n$_{\mathrm{i}}$ is the IGZO intrinsic carrier density (1.71 x 102 cm-3) (2), N$_{\mathrm{A}}$ is the acceptor doping density, and S is the slope in the -d(C$_{\mathrm{ox}}$/C)$^{2}$/dt-(C$_{\mathrm{inv}}$/C)$^{-1}$ plot. Fig. 5(b) shows the results of the c-t measurements and Zerbst plot extraction. The $\tau_{g}$ extracted through this process was higher with an increasing OFR, the $\tau_{g}$ of the O-poor sample was 5.86 ${\times}$ 10$^{-14}$ (s), and the $\tau_{g}$ of the O-rich sample was 5.54 ${\times}$ 10$^{-13}$ (s).


We proposed a method to identify the channel characteristics of IGZO TFTs through electrical analysis without physical analysis. By fabricating devices with different OFRs that have been reported previously, the interface characteristics of the IGZO and gate insulator were analyzed through PECCS to compare the number of defects according to the energy level. Bulk IGZO was investigated by extracting the carrier lifetime through c-t measurements. Finally, by verifying the same results as previously reported through physical analysis, the effectiveness of the electrical analysis method presented in this paper was confirmed. In future studies, the quality index can be affirmed when IGZO film quality is improved using the electrical property evaluation presented in this paper.


This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. 2019R1F1A1051493). And, this research was funded and conducted under ‘the Competency Development Program for Industry Specialists’ of the Korean Ministry of Trade, Industry and Energy (MOTIE), operated by Korea Institute for Advancement of Technology (KIAT) (No. P0012453, Next-generation Display Expert Training Project for Innovation Process and Equipment, Materials Engineers).


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Hyo-Jung Kim

Hyo-Jung Kim received his M.S. degree in the Department of Infor-mation and Communication Engi-neering from Sungkyunkwan Univer-sity, Suwon, South Korea, in 2013.

He is currently a Ph.D. candidate with the Department of Semiconductor and Display Engineering in Sungkyunkwan University, Suwon, South Korea.

In 2013, he joined the Samsung Display Company where he has been working in the area of quality and reliability.

His interests are the reliability of Oxide TFTs and LTPS for flexible displays.

Soon-Kon Kim

Soon-Kon Kim received his B.S. and M.S. degrees in the Department of Information and Communication Engineering, Sungkyunkwan Univer-sity, Suwon, South Korea., in 2013 and 2015, respectively.

He is currently a Ph.D. candidate in Sungkyunkwan University, Suwon, south Korea.

His current research interests include display devices.

Jung-Min Park

Jung-Min Park received his B.S. degree in Materials science engi-neering from Korea University, Seoul, South Korea, in 2002 and his M.S. degree in Materials Science Engineering from the Gwangju Institute of Science and Technology, Gwangju, South Korea, in 2004.

He is currently a Ph.D. candidate with the Department of Semiconductor and Display Engineering in Sungkyunkwan University, Suwon, South Korea.

Since 2004, he has been with the Samsung Electronics Company, Ltd., Gyeonggi-Do, South Korea, and has been engaged in the development of high-k gate dielectric and metal gates for advanced logic devices.

Ki-Hwan Kim

Ki-Hwan Kim received his B.S. and M.S. degrees in the Department of Physics from Korea University, Seoul, south Korea, in 2004 and 2006, respectively.

He is currently a Ph.D. candidate with the Department of Semiconductor and Display Engineering in Sungkyunkwan University, Suwon, South Korea.

In 2006 he joined Hynix (now, SK-hynix) and in 2011 he joined the Samsung Display Company where he has been working in the area of computer aided engineering.

His interests include TCAD analysis and the reliability of oxide TFTs LTPS for displays.

Jang-Kun Song

Jang-Kun Song received his B.S. and M.S. degrees in physics from Korea University, Seoul, South Korea in 1994 and 1996, respectively.

He also received his Ph.D. degree in electronic engineering from the University of Dublin, Dublin, Ireland in 2008.

He worked in the R&D department of Samsung Electronics Company as a principal engineer from 1996 to 2010.

In Samsung, he invented the patterned vertical alignment LCD technology, which is currently the main technology used in LCD applications produced by the Samsung Company.

In 2010, he moved to Sungkyunkwan University, Suwon, South Korea, and he is currently an associate professor in the School of Electronics and Electrical Engineering.

Byoung-Deog Choi

Byoung-Deog Choi received the Ph.D. degree in electrical engi-neering from Arizona State Univer-sity, Tempe, AZ, USA, in 2002.

He is currently a Professor with the School of Information and Com-munication Engineering, Sungkyun-kwan University, Suwon, South Korea.

He has authored over 100 articles in SCI journals and holds 50 patents.

His current research interests include display devices and C-MOS technology.