ParkBeomyu
KwonKuduck
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Bluetooth low energy, commongate amplifier, image rejection ratio, I/Q mismatch, lowIF receiver, quadrature LNA, quadrature generator
I. INTRODUCTION
In recent decades, the internet of things (IoT) market has been growing rapidly, and
the demand for IoT sensor devices has also been increasing. Most of the currently
commercialized IoT sensor devices use a 2.4 GHz ISM band. One of the most popular
communication protocols is Bluetooth low energy (BLE). BLE requires relaxed specifications
in terms of sensitivity or noise figure (NF), compared to cellular applications. However,
BLE receivers require lowpower consumption for a low replacement period of the battery
and long term use. Therefore, to reduce power consumption while maintaining key performances,
research works for the lowpower receiver are actively being conducted ^{(1}^{12)}.
Most BLE receivers adopt a simple singlequadrature architecture for low cost and
low power consumption. Because of its narrow channel bandwidth, the lowIF architecture
is widely employed. The lowIF structure is suitable for its low 1/f noise level,
but suffers from the finite image signal problem. To solve the image problem, the
lowIF receiver should perform quadrature mixing. The BLE standard requires an image
rejection ratio (IRR) of 21dB, which is not difficult to achieve ^{(13)}. For lowpower consumption, the receiver prefers generating quadrature signals using
the quadrature lownoise amplifier (LNA) or G_{m}stage, rather than additional circuitry such as dividebytwo or quadrature voltagecontrolled
oscillator in a local oscillator (LO) path. Therefore, the quadrature LNA can be an
alternative for providing quadrature signals to lowpower singlequadrature receivers.
In this paper, a 2.4GHz BLE receiver adopting a quadrature LNA, which was recently
proposed in ^{(8)}, is considered and analyzed in detail. The proposed quadrature LNA is composed of
a commonsource (CS) amplifier with inductive degeneration and a quadrature generator
based on a commongate (CG) amplifier with a single RC network. In Section II, the
proposed quadrature transconductor topology is introduced. The detailed circuit implementation
of the BLE receiver is presented in Section III. The simulation results are discussed
in Section IV. Finally, Section V concludes this paper.
Fig. 1. Conventional quadrature transconductor topologies (a) CS transconductor with
capacitive degeneration, (b) CG transconductor with a single RC network.
II. PROPOSED QUADRATURE TRANSCONDUCTOR TOPOLOGY
In this section, the conventional and proposed quadrature transconductor topologies
are introduced. To avoid additional power consumption in the LO chain, the quadrature
transconductor can be used to implement the singlequadrature lowIF receiver. Fig. 1 shows conventional quadrature transconductor topologies. In the quadrature transconductor
with the CSbased topology shown in Fig. 1(a), quadrature signals are generated using the degeneration capacitors of C and C_{1}. When g_{m1} << sC_{1} and g_{m1} = ωC_{0}, I_{RF,I} and I_{RF,Q} have a quadrature relationship of I_{RF,I}I_{RF,Q} = 1 and ${\angle}$(I_{RF,I}I_{RF,Q}) = 90 $^{\circ}$ ^{(9,}^{10,}^{14)}. It is beneficial that the CSbased transconductor does not induce severe loading
effects on the preceding block when used as an interstage block because of the capacitive
input impedance. However, the transconductor requires input power matching to a 50ohm
terminal impedance interface when used as the first block of the receiver such as
the LNA and lownoise transconductance amplifier (LNTA). In ^{(9)}, the CSbased transconductor used an additional resistor for input matching. Consequently,
the quadrature LNTA of ^{(9)} demonstrated poor NF performance. The CGbased quadrature transconductor topology
is shown in Fig. 1(b). Lowpass and highpass filters are implemented in the CG and CS stages, respectively,
through the single RC network. The output currents of I_{RF,I} and I_{RF,Q} are given by
Fig. 2. Proposed quadrature transconductor topology
where R_{0} and C_{0} are the resistance and capacitance of the RC network, respectively ^{(11)}. When ωR_{0}C_{0} = 1 and g_{m0} = g_{m1}, the output currents of I_{RF,I} and I_{RF,Q} have a quadrature relationship. The CGbased quadrature transconductor has the advantage
of broadband input matching when used in the first block such as LNA and LNTA. However,
in terms of noise performance, the CGbased transconductor cannot achieve excellent
NF.
Fig. 3. Block diagram of the proposed BLE receiver
The proposed quadrature transconductor topology is shown in Fig. 2. The proposed quadrature transconductor combines the CS amplifier with inductive
degeneration and the CGbased quadrature generator with a single RC network. It takes
advantage of both low NF of the CS amplifier and quadrature generation of the CGbased
transconductor. It performs simultaneous noise and input power matching by employing
an additional capacitor of C_{EX} ^{(15)}. The output currents of the proposed quadrature transconductor can be expressed by
where Q_{IN} is the quality factor of the input matching network when an input matching condition
is met. When g_{m1} = g_{m2} and ωR_{0}C_{0} = 1, I_{RF,I} and I_{RF,Q} have a quadrature relationship of I_{RF,I} I_{RF,Q}=1 and ${\angle}$(I_{RF,I}I_{RF,Q}) = 90$^{\circ}$. The proposed quadrature transconductor has lower NF performance
than the previous CGbased quadrature transconductor in ^{(11)} with the same power consumption. Therefore, the proposed quadrature transconductor
topology is a suitable solution for designing the quadrature LNA for lowpower BLE
receivers.
III. CIRCUIT IMPLEMENTATION
In this section, the detailed circuit design of the implemented BLE receiver is presented.
The block diagram of the proposed BLE receiver is shown in Fig. 3. A lowIF singlequadrature receiver topology, which consists of the quadrature LNA,
a doublebalanced active mixer, and the secondorder G_{m}C complex filter, is employed for low 1/f noise and high integration.
Fig. 4. Schematic of the proposed quadrature LNA.
Fig. 5. Simulated gain and phase error of the quadrature LNA according to PVT variations
1. Quadrature LNA
The proposed quadrature LNA is shown in Fig. 4. The LNA employs the proposed quadrature transconductor to achieve low noise performance
and provide quadrature output currents. It also uses an LC tank as a load. M_{N1} and M_{N2} improve reverse isolation as well as the generation of the quadrature signals. To
minimize the die area, a wire bonding inductor is used to implement L_{S}. A 4bitcapacitor array, which is digitally controlled, is used in the LC tank to
compensate for the variation in the 2.4GHz resonant frequency of the LC tank caused
by variations in the process, voltage, and temperature. The external inductor L_{M} is used for input impedance matching. Fig. 5 shows the simulated gain and phase error of the proposed quadrature LNA in the BLE
operating frequencies according to the process, voltage, and temperature (PVT) variations.
The LNA can provide accurate quadrature signals in the BLE band at the typical corner
case (Case #1), with gain and phase error less than 0.3 dB and 4.3$^{\circ}$, respectively.
It is sufficient to meet the IRR requirement of 21 dB for the BLE standard. In addition,
the gain and phase mismatch can be calibrated by tuning R_{0}.
The noise factor of the proposed quadrature LNA can be expressed to
where k is the Boltzmann’s constant, T is the absolute temperature, R_{S} is a source resistance, A_{Vtot} is the voltage gain from the voltage source V_{S} to the output. V_{MN0}, V_{MN1}, V_{MN2}, V_{MN3}, and V_{R0} represent the outputreferred noise voltage generated by M_{N0}, M_{N1}, M_{N2}, M_{N3}, and R_{0}, respectively ^{(15)}. When it is assumed that ωR_{0}C_{0} = 1, and r_{o} >> Z_{L}, A^{2}_{Vtot} can be approximately given to
where Q_{IN} is the quality factor of the input matching network and Z_{L} is the impedance of the LC tank. The noise factor F is approximately given to
where the second to fourth terms represent noise contributions of M_{N0}, M_{N1}, and M_{N2}, respectively, and the last term represents the noise contribution of the R_{0}. The noise contribution of M_{N3} is neglected because the drain node of M_{N3} is AC grounded. As shown in (7), M_{N0} determines an overall NF, and the noise contribution of M_{N2} and R_{0} are also dominant. In this design, appropriate values of g_{m}, R_{0} and C_{0} are chosen to have an excellent NF and IRR performance through thorough layout parasitic
extraction simulation.
Fig. 6. Schematic of singletodifferential doublebalanced active mixer.
Fig. 7. Schematic of the secondorder GmC complex filter.
2. Doublebalanced Active Mixer
Fig. 6 shows the implemented active mixer, which is designed based on a gilbert cell. One
of the differential inputs is connected to an AC ground to perform a single to differential
conversion. The current bleeding technique is used to reduce the contribution of the
1/f noise. Because the quadrature signals are generated in the quadrature LNA of the
RF signal path, the switching stage of the active mixer is driven by inphase differential
signals, rather than inphase and quadraturephase differential signals.
Fig. 8. Layout of the proposed BLE receiver.
Table 1. Power breakdown of the implemented BLE receiver
Block

Current
consumption

Power
consumption

Quadrature LNA

1 mA

0.8 mW

Active mixer

0.9 mA

0.72 mW

Complex filter

0.3 mA

0.24 mW

Total

2.2 mA

1.76 mW

3. Secondorder GmC Complex Bandpass Filter
The secondorder G_{m}C complex bandpass filter, which is introduced in ^{(16)}, is employed in the implemented BLE receiver and is shown in Fig. 7. It simultaneously performs image rejection and channel selection without having
a loading effect on the preceding circuit. The G_{m}C filter topology is advantageous in terms of power consumption. The filter has a
realpole (ω_{RE}) and an imaginary pole (ω_{IM}), which are expressed by (g_{m,RE}  g_{m,NEG})/C_{0}and g_{m,IM}/C_{0},respectively. The realpole determines the 3dB bandwidth of the filter, and imaginarypole
shifts the real poles to the complex location in ω_{RE}jω_{IM},. Consequently, the filter has a bandpass frequency response. A twostage secondorder
G_{m}C filter is designed to satisfy the 21 dB IRR requirement for the BLE standard.
IV. SIMULATION RESULTS
The proposed lowpower receiver adopting a quadrature LNA for BLE applications was
designed in a 65nm CMOS process. The layout of the BLE receiver is depicted in Fig. 8. The active area without the bond pads is 2.24 mm$^{2}$. It draws a DC bias current
of 2.2 mA from a supply voltage of 0.8 V. The power breakdown of the designed BLE
receiver is shown in Table 1. The current consumptions of the LNA, mixer, and complex filter are 1 mA, 0.9 mA,
and 0.3 mA, respectively.
Fig. 11. Simulated frequency response.
Table 2. Simulated performance summaries of the proposed BLE receiver and comparison
with previous stateoftheart works

Unit

TMTT2017
^{(2)}

JSSC2018
^{(3)}

TMTT2019
^{(5)}

JSSC2010
^{(10)}

JSSC2015
^{(11)}

MWCL2019 ^{(12)}

This Work

Application



BLE

BLE

BLE

Zigbee

BLE

IoT

BLE

Process



28 nm CMOS

28 nm CMOS

130 nm CMOS

90 nm CMOS

130 nm CMOS

65 nm CMOS

65 nm CMOS

Architecture



LowIF

LowIF

LowIF

LowIF

LowIF

LowIF

LowIF

Frequency

GHz

2.42.48

2.42.48

2.42.48

2.42.48

2.42.48

0.90.92

2.42.48

Gain

dB

46

41.3

42

76

56.1

40.7

53.2

NF

dB

6.5

8.8

7.2

10

15.1

1.94

4.81

IRR

dB

26

25.1

40

35

30.5

NR^{2)}

38

Pdc

mW

2.75^{1)}

1.3

1.7^{1)}

3.6

0.6

3.6

1.76

Supply Voltage

V

1

0.3

1.2

1.2

0.8

1.8

0.8

Area

mm^{2}

1.92

1.65

0.7

0.23

0.25

0.559

2.24

1) It includes power consumption of the demodulator.
2) NR: Not Reported
Fig. 12. Simulated conversion gain, IRR, and NF versus RF frequencies.
Fig. 9 shows the input return loss (S11) of the receiver. The simulated S11 is lower than
8 dB over the BLE band from 2.4  2.48 GHz. The simulated NF of the receiver in the
2 MHz IF frequency is shown in Fig. 10. The designed BLE receiver has a minimum NF of 4.81~dB in 2.44 GHz RF frequency.
Fig. 11 shows the frequency response of the receiver. The simulated maximum gain is 53.2
dB in an IF frequency of 2 MHz. The simulated maximum IRR over the BLE operating frequencies
is 38 dB. Fig. 12 shows the maximum conversion gain, IRR, and NF versus RF frequencies. The maximum
conversion gain and IRR are obtained as 51.7 to 53.2 dB, and 34.2 to 39 dB, respectively.
The receiver achieves an NF performance of less than 5.45 dB in all the BLE operating
frequencies. Fig. 13 shows the simulated IRR performance according to PVT variations at 2.44 GHz RF frequency.
The obtained IRRs are more than 33 dB for all corner cases. These are sufficient to
meet the IRR requirement of 21 dB. Table 2 summarizes and compares the performance of the proposed receiver with previous stateoftheart
works. As shown in the Table 2, the proposed receiver demonstrates lower NF performance compared to previous works
using the quadrature LNA and LNTA of ^{(10,}^{11)}.
Fig. 13. Simulated IRR versus PVT variations.
V. CONCLUSIONS
A lowpower lowIF singlequadrature receiver employing a quadrature LNA for BLE applications
was designed and implemented in 65nm CMOS process. The implemented quadrature LNA
achieves excellent NF performance by simultaneously performing the noise and input
power matching of the CS amplifier with inductive degeneration and provides an accurate
quadrature signals using the CGbased quadrature generator with a single RC network.
Consequently, the proposed quadrature LNA demonstrated a significantly lower NF performance
than the previous quadrature LNAs with similar current consumption. The proposed quadrature
LNA topology is suitable for designing lowpower lownoise quadrature LNAs. The implemented
BLE receiver achieves a maximum conversion gain, minimum NF, and an IRR of 53.2 dB,
4.81 dB, and 38 dB, respectively, with power consumption of 1.76 mW.
ACKNOWLEDGMENTS
This work was supported in part by the Basic Science Research Program through the
National Research Foundation of Korea (NRF) funded by the Ministry of Education under
Grant NRF2018R1D1A1B07042804 and in part by the Ministry of Science and ICT, Korea,
under the Information Technology Research Center Support Program supervised by the
Institute for Information and Communications Technology Promotion (IITP) under Grant
IITP20202018001433. The chip fabrication and EDA tool were supported by the IC
Design Education Center (IDEC), Korea.
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Author
Beomyu Park is currently working toward the integrated B.S. and M.S. degree in Department
of Electronics Engineering, Kangwon National University, Chuncheon, Korea.
His research interests include CMOS RF/analog integrated circuits and RF system design
for wireless communications.
Kuduck Kwon received the B.S. and Ph.D. degrees in Electrical Engineering and Computer
Science from Korea Advanced Institute of Science and Technology (KAIST), in Daejeon,
Korea, in 2004 and 2009, respectively.
His doctoral research concerned digital TV tuners and dedicated shortrange communication
(DSRC) systems.
From 2009 to 2010, he was a PostDoctoral Researcher with KAIST, where he studied
a surface acoustic wave (SAW)less receiver and developed RF transceivers for DSRC
applications.
From 2010 to 2014, he was a Senior Engineer with Samsung Electronics Co. LTD., Suwon,
Korea, where he was involved in studying softwaredefined receiver and developing
silicon tuner and cellular RFICs.
In 2014, he joined the Department of Electronics Engineering, Kangwon National University,
Chuncheon, Korea, where he is currently an Associate Professor.
His research interests include CMOS mmWave/RF/analog integrated circuits and RF system
design for wireless communications.