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Bluetooth low energy, common-gate amplifier, image rejection ratio, I/Q mismatch, low-IF receiver, quadrature LNA, quadrature generator


In recent decades, the internet of things (IoT) market has been growing rapidly, and the demand for IoT sensor devices has also been increasing. Most of the currently commercialized IoT sensor devices use a 2.4 GHz ISM band. One of the most popular communication protocols is Bluetooth low energy (BLE). BLE requires relaxed specifications in terms of sensitivity or noise figure (NF), compared to cellular applications. However, BLE receivers require low-power consumption for a low replacement period of the battery and long term use. Therefore, to reduce power consumption while maintaining key performances, research works for the low-power receiver are actively being conducted (1-12).

Most BLE receivers adopt a simple single-quadrature architecture for low cost and low power consumption. Because of its narrow channel bandwidth, the low-IF architecture is widely employed. The low-IF structure is suitable for its low 1/f noise level, but suffers from the finite image signal problem. To solve the image problem, the low-IF receiver should perform quadrature mixing. The BLE standard requires an image rejection ratio (IRR) of 21dB, which is not difficult to achieve (13). For low-power consumption, the receiver prefers generating quadrature signals using the quadrature low-noise amplifier (LNA) or Gm-stage, rather than additional circuitry such as divide-by-two or quadrature voltage-controlled oscillator in a local oscillator (LO) path. Therefore, the quadrature LNA can be an alternative for providing quadrature signals to low-power single-quadrature receivers.

In this paper, a 2.4-GHz BLE receiver adopting a quadrature LNA, which was recently proposed in (8), is considered and analyzed in detail. The proposed quadrature LNA is composed of a common-source (CS) amplifier with inductive degeneration and a quadrature generator based on a common-gate (CG) amplifier with a single RC network. In Section II, the proposed quadrature transconductor topology is introduced. The detailed circuit implementation of the BLE receiver is presented in Section III. The simulation results are discussed in Section IV. Finally, Section V concludes this paper.

Fig. 1. Conventional quadrature transconductor topologies (a) CS transconductor with capacitive degeneration, (b) CG transconductor with a single RC network.



In this section, the conventional and proposed quadrature transconductor topologies are introduced. To avoid additional power consumption in the LO chain, the quadrature transconductor can be used to implement the single-quadrature low-IF receiver. Fig. 1 shows conventional quadrature transconductor topologies. In the quadrature transconductor with the CS-based topology shown in Fig. 1(a), quadrature signals are generated using the degeneration capacitors of -C and C1. When gm1 << sC1 and gm1 = ωC0, IRF,I and IRF,Q have a quadrature relationship of |IRF,IIRF,Q| = 1 and ${\angle}$(IRF,IIRF,Q) = 90 $^{\circ}$ (9,10,14). It is beneficial that the CS-based transconductor does not induce severe loading effects on the preceding block when used as an inter-stage block because of the capacitive input impedance. However, the transconductor requires input power matching to a 50-ohm terminal impedance interface when used as the first block of the receiver such as the LNA and low-noise transconductance amplifier (LNTA). In (9), the CS-based transconductor used an additional resistor for input matching. Consequently, the quadrature LNTA of (9) demonstrated poor NF performance. The CG-based quadrature transconductor topology is shown in Fig. 1(b). Low-pass and high-pass filters are implemented in the CG and CS stages, respectively, through the single RC network. The output currents of IRF,I and IRF,Q are given by

Fig. 2. Proposed quadrature transconductor topology


$$ I_{R F, I}=\frac{-1}{1+s R_{0} C_{0}} g_{m 0} V_{I N} $$


where R0 and C0 are the resistance and capacitance of the RC network, respectively (11). When ωR0C0 = 1 and gm0 = gm1, the output currents of IRF,I and IRF,Q have a quadrature relationship. The CG-based quadrature transconductor has the advantage of broadband input matching when used in the first block such as LNA and LNTA. However, in terms of noise performance, the CG-based transconductor cannot achieve excellent NF.

Fig. 3. Block diagram of the proposed BLE receiver


The proposed quadrature transconductor topology is shown in Fig. 2. The proposed quadrature transconductor combines the CS amplifier with inductive degeneration and the CG-based quadrature generator with a single RC network. It takes advantage of both low NF of the CS amplifier and quadrature generation of the CG-based transconductor. It performs simultaneous noise and input power matching by employing an additional capacitor of CEX (15). The output currents of the proposed quadrature transconductor can be expressed by


$$I_{RF,Q}=- Q_{IN}g_{m0}\frac{sR_{0}C_{0}}{g_{m1}+sC_{0}}g_{m2}V_{IN}$$

where QIN is the quality factor of the input matching network when an input matching condition is met. When gm1 = gm2 and ωR0C0 = 1, IRF,I and IRF,Q have a quadrature relationship of |IRF,I IRF,Q|=1 and ${\angle}$(IRF,IIRF,Q) = 90$^{\circ}$. The proposed quadrature transconductor has lower NF performance than the previous CG-based quadrature transconductor in (11) with the same power consumption. Therefore, the proposed quadrature transconductor topology is a suitable solution for designing the quadrature LNA for low-power BLE receivers.


In this section, the detailed circuit design of the implemented BLE receiver is presented. The block diagram of the proposed BLE receiver is shown in Fig. 3. A low-IF single-quadrature receiver topology, which consists of the quadrature LNA, a double-balanced active mixer, and the second-order Gm-C complex filter, is employed for low 1/f noise and high integration.

Fig. 4. Schematic of the proposed quadrature LNA.


Fig. 5. Simulated gain and phase error of the quadrature LNA according to PVT variations


1. Quadrature LNA

The proposed quadrature LNA is shown in Fig. 4. The LNA employs the proposed quadrature transconductor to achieve low noise performance and provide quadrature output currents. It also uses an LC tank as a load. MN1 and MN2 improve reverse isolation as well as the generation of the quadrature signals. To minimize the die area, a wire bonding inductor is used to implement LS. A 4-bit-capacitor array, which is digitally controlled, is used in the LC tank to compensate for the variation in the 2.4-GHz resonant frequency of the LC tank caused by variations in the process, voltage, and temperature. The external inductor LM is used for input impedance matching. Fig. 5 shows the simulated gain and phase error of the proposed quadrature LNA in the BLE operating frequencies according to the process, voltage, and temperature (PVT) variations. The LNA can provide accurate quadrature signals in the BLE band at the typical corner case (Case #1), with gain and phase error less than 0.3 dB and 4.3$^{\circ}$, respectively. It is sufficient to meet the IRR requirement of 21 dB for the BLE standard. In addition, the gain and phase mismatch can be calibrated by tuning R0.

The noise factor of the proposed quadrature LNA can be expressed to


where k is the Boltzmann’s constant, T is the absolute temperature, RS is a source resistance, AVtot is the voltage gain from the voltage source VS to the output. VMN0, VMN1, VMN2, VMN3, and VR0 represent the output-referred noise voltage generated by MN0, MN1, MN2, MN3, and R0, respectively (15). When it is assumed that ωR0C0 = 1, and ro >> ZL, A2Vtot can be approximately given to

$$A_{Vtot}^{2}\approx Q_{IN}^{2}\frac{\left(g_{m0}R_{0}\right)^{2}}{1+\left(g_{m1}R_{0}\right)^{2}}\left(g_{m2}Z_{L}\right)^{2}$$

where QIN is the quality factor of the input matching network and ZL is the impedance of the LC tank. The noise factor F is approximately given to

$$F\approx 1+\frac{\gamma }{Q_{IN}^{2}g_{m0}R_{S}}\left(1+\frac{g_{m1}}{g_{m0}}+\frac{1+g_{m1}^{2}R_{0}^{2}}{g_{m0}g_{m2}R_{0}^{2}}\right)$$ $$+\frac{1}{Q_{IN}^{2}g_{m0}R_{S}}\left(\frac{1+g_{m1}^{2}R_{0}^{2}}{g_{m0}R_{0}}\right)$$

where the second to fourth terms represent noise contributions of MN0, MN1, and MN2, respectively, and the last term represents the noise contribution of the R0. The noise contribution of MN3 is neglected because the drain node of MN3 is AC grounded. As shown in (7), MN0 determines an overall NF, and the noise contribution of MN2 and R0 are also dominant. In this design, appropriate values of gm, R0 and C0 are chosen to have an excellent NF and IRR performance through thorough layout parasitic extraction simulation.

Fig. 6. Schematic of single-to-differential double-balanced active mixer.


Fig. 7. Schematic of the second-order Gm-C complex filter.


2. Double-balanced Active Mixer

Fig. 6 shows the implemented active mixer, which is designed based on a gilbert cell. One of the differential inputs is connected to an AC ground to perform a single to differential conversion. The current bleeding technique is used to reduce the contribution of the 1/f noise. Because the quadrature signals are generated in the quadrature LNA of the RF signal path, the switching stage of the active mixer is driven by in-phase differential signals, rather than in-phase and quadrature-phase differential signals.

Fig. 8. Layout of the proposed BLE receiver.


Table 1. Power breakdown of the implemented BLE receiver






Quadrature LNA

1 mA

0.8 mW

Active mixer

0.9 mA

0.72 mW

Complex filter

0.3 mA

0.24 mW


2.2 mA

1.76 mW

3. Second-order Gm-C Complex Bandpass Filter

The second-order Gm-C complex bandpass filter, which is introduced in (16), is employed in the implemented BLE receiver and is shown in Fig. 7. It simultaneously performs image rejection and channel selection without having a loading effect on the preceding circuit. The Gm-C filter topology is advantageous in terms of power consumption. The filter has a real-pole (ωRE) and an imaginary pole (ωIM), which are expressed by (gm,RE - gm,NEG)/C0and gm,IM/C0,respectively. The real-pole determines the 3-dB bandwidth of the filter, and imaginary-pole shifts the real poles to the complex location in ωRE-jωIM,. Consequently, the filter has a bandpass frequency response. A two-stage second-order Gm-C filter is designed to satisfy the 21 dB IRR requirement for the BLE standard.


The proposed low-power receiver adopting a quadrature LNA for BLE applications was designed in a 65-nm CMOS process. The layout of the BLE receiver is depicted in Fig. 8. The active area without the bond pads is 2.24 mm$^{2}$. It draws a DC bias current of 2.2 mA from a supply voltage of 0.8 V. The power breakdown of the designed BLE receiver is shown in Table 1. The current consumptions of the LNA, mixer, and complex filter are 1 mA, 0.9 mA, and 0.3 mA, respectively.

Fig. 9. Simulated S11.


Fig. 10. Simulated NF.


Fig. 11. Simulated frequency response.


Table 2. Simulated performance summaries of the proposed BLE receiver and comparison with previous state-of-the-art works












MWCL2019 (12)

This Work












28 nm CMOS

28 nm CMOS

130 nm CMOS

90 nm CMOS

130 nm CMOS

65 nm CMOS

65 nm CMOS























































Supply Voltage


















1) It includes power consumption of the demodulator.

2) NR: Not Reported

Fig. 12. Simulated conversion gain, IRR, and NF versus RF frequencies.


Fig. 9 shows the input return loss (S11) of the receiver. The simulated S11 is lower than -8 dB over the BLE band from 2.4 - 2.48 GHz. The simulated NF of the receiver in the 2 MHz IF frequency is shown in Fig. 10. The designed BLE receiver has a minimum NF of 4.81~dB in 2.44 GHz RF frequency. Fig. 11 shows the frequency response of the receiver. The simulated maximum gain is 53.2 dB in an IF frequency of 2 MHz. The simulated maximum IRR over the BLE operating frequencies is 38 dB. Fig. 12 shows the maximum conversion gain, IRR, and NF versus RF frequencies. The maximum conversion gain and IRR are obtained as 51.7 to 53.2 dB, and 34.2 to 39 dB, respectively. The receiver achieves an NF performance of less than 5.45 dB in all the BLE operating frequencies. Fig. 13 shows the simulated IRR performance according to PVT variations at 2.44 GHz RF frequency. The obtained IRRs are more than 33 dB for all corner cases. These are sufficient to meet the IRR requirement of 21 dB. Table 2 summarizes and compares the performance of the proposed receiver with previous state-of-the-art works. As shown in the Table 2, the proposed receiver demonstrates lower NF performance compared to previous works using the quadrature LNA and LNTA of (10,11).

Fig. 13. Simulated IRR versus PVT variations.



A low-power low-IF single-quadrature receiver employing a quadrature LNA for BLE applications was designed and implemented in 65-nm CMOS process. The implemented quadrature LNA achieves excellent NF performance by simultaneously performing the noise and input power matching of the CS amplifier with inductive degeneration and provides an accurate quadrature signals using the CG-based quadrature generator with a single RC network. Consequently, the proposed quadrature LNA demonstrated a significantly lower NF performance than the previous quadrature LNAs with similar current consumption. The proposed quadrature LNA topology is suitable for designing low-power low-noise quadrature LNAs. The implemented BLE receiver achieves a maximum conversion gain, minimum NF, and an IRR of 53.2 dB, 4.81 dB, and 38 dB, respectively, with power consumption of 1.76 mW.


This work was supported in part by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education under Grant NRF-2018R1D1A1B07042804 and in part by the Ministry of Science and ICT, Korea, under the Information Technology Research Center Support Program supervised by the Institute for Information and Communications Technology Promotion (IITP) under Grant IITP-2020-2018-0-01433. The chip fabrication and EDA tool were supported by the IC Design Education Center (IDEC), Korea.


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Yoonji Park

Beomyu Park is currently working toward the integrated B.S. and M.S. degree in Department of Electronics Engineering, Kangwon National University, Chuncheon, Korea.

His research interests include CMOS RF/analog integrated circuits and RF system design for wireless communications.

Ji-Hoon Kim

Kuduck Kwon received the B.S. and Ph.D. degrees in Electrical Engi-neering and Computer Science from Korea Advanced Institute of Science and Technology (KAIST), in Dae-jeon, Korea, in 2004 and 2009, respectively.

His doctoral research concerned digital TV tuners and dedicated short-range communication (DSRC) systems.

From 2009 to 2010, he was a Post-Doctoral Researcher with KAIST, where he studied a surface acoustic wave (SAW)-less receiver and developed RF transceivers for DSRC applications.

From 2010 to 2014, he was a Senior Engineer with Samsung Electronics Co. LTD., Suwon, Korea, where he was involved in studying software-defined receiver and developing silicon tuner and cellular RFICs.

In 2014, he joined the Department of Electronics Engineering, Kangwon National University, Chuncheon, Korea, where he is currently an Associate Professor.

His research interests include CMOS mmWave/RF/analog integrated circuits and RF system design for wireless communi-cations.