A. Solution: Increasing width of EM Wire:

Given the EM current density limit for each metal layer, a set of current sources, a set of sink sources, selection of appropriate width of the EM affected wire segment controls the current density bound to the EM limit in early stages of routing. ICT (that contains current limits to all the metal layers for a technology node. It helps to identify the EM affected nets) and QRC (that contains the information about the design rules of technology node) files contain the EM current density limit and rules for each technology.

To minimize the EM violations, this project carefully increases the width of the EM wire as shown in Fig. 1 Mathematically, it can be written as

In this above Eq. (2.1)), J$_{EM }$stands for EM current density limit, I refer to necessary current, w refers to the width of an interconnect, and h is the thickness of the wire. Hence, for a unit length of EM affected wire, an increase in width w helps to acquire the necessary EM current limit.

The prior works like ^(20,35,36) mentioned in the literature, constructs a suitable wiring methodology to address this problem.

B. Solution: Splitting of EM wire:

Fig. 2. Splitting wire (a) long wire, (b) splitting wire.

Fig. 3. Downsizing of cells (a) load cell with high drive strength, (b) Downsizing of standard cell with buffer inserted in the interconnect.

Given an EM long wire belong to a metal layer and it is associated with connected interconnect segments, dividing the length of this long EM affected wire into multiple segments helps to control the EM current density. Fig. 2(a) depicts an EM affected wire, dividing the wire into short segments as in Fig. 2(b) reduces the speed flow of electrons. In ⁽¹⁷⁾, Gracieli Posser et al. implements these short segments in different metal layers, however, this complicates the routing process and affects timing. Hence, this project uses short segments arising from a long wire of different metal layer.

C. Solution: Downsizing of cells:

Given an EM interconnect whose sink nodes containing standard cells of higher drive strength, downsizing the drive strength of this standard cell reduces the transient current flow through the interconnect; thus it helps in avoid EM in the interconnect. On the other hand, the slow transition due to downsizing of cells will introduce delay in the path that may affect the performance of the design. To meet the desired timing constraint, this project uses a greedy methodology in the allocation of the standard cell to these sink nodes. In this greedy methodology, in addition to downsizing it adds buffers in interconnects as shown in Fig. 3. Insertion of buffers in the EM affected interconnects reduces the load on the down sized driving cell. In case of timing critical nets, this paper first performs STA that involves addition and sizing of standard cells in the path. To verify the current flow in this timing path, this paper performs EM analysis and corporate the proposed methodology if the current flow exceeds the technology EM limit.

Fig. 4. Greedy choice property (a) EM net, (b) Downsizing of source s$_{2}$ and sink t$_{1}$, (c) Insertion of buffers in the path between s$_{1}$ to sink s$_{2}$ and s$_{2}$ to t$_{1}$.

D. Greedy Methodology

Fig. 5. Greedy choice property on multi-terminal nets (a) multi-terminal EM net, (b) Achieving EM limits using proposed technique.

The proposed greedy-choice property is based on the various methodologies described in subsections II-A, II-B, and II-C. Suppose there exist a net that satisfies the timing constraint but affected due to EM rules or any more complicated multi- terminal EM nets, implementation our proposed generic form greedy-choice property controls the current limit of the wire and avoid EM violations.

Observation- Greedy-Choice : Single terminal nets:} Let us consider the motivational example in ⁽²⁰⁾ that has two sources s$_{1}$, s$_{2}$, and one sink T$_{1}$ an EM net shown in Fig. 4(a).

Solution: This project aims to handle the EM current in the net without changing its routing guide obtained after static timing analysis. Without loss of generality, the required current density can be obtained from the following options given below,

1) Option 1: widening of wires.

2) Option 2: downsizing the source s$_{2}$ and sink T$_{1}$.

3) Option 3: insertion of buffers in the path between s$_{1}$ to sink s$_{2 }$ and s$_{2 }$ to t$_{1}$.

4) Option 4: wire splitting.

For the EM critical net shown in Fig. 4(a), using the option 1, wire widening may create geometrical issues due to increase in width. Though, implementing option 2 shown in Fig. 4(b) (downsizing of cells) will give a finite solution, however, in some cases it creates timing violation. Hence, this project adds necessary buffer cells in between the nodes shown in Fig. 4(c) to satisfy the timing. The option 4 is used when the length of a net is long or with high current density in an interconnect.

Observation-- Greedy-Choice theorem: Multi-terminal nets:} Consider the Fig. 5(a) that has multi-terminal EM net whose current density is greater than the expected EM limit. Similar to the previous case in Fig. 4, greedy methodology is followed in this case to handle EM violations. Generally, the usage of standard cells with smaller drive strength will limit the current flow in the interconnect. Since these standard cells also drives the remaining cells in the path, iterative resizing methodology plays a significant role to achieve necessary the static timing constraints.

In this paper, we perform the following steps iteratively to govern the EM current and reduce the slack time.

·Firstly, we analyse the AC current flow in the given placed layout. This verification method identifies the EM violating nets beyond the technology specified current limit.

·Secondly, we impose our proposed methodology to reduce the EM violations.

·Thirdly, the static timing analysis is performed to verify the static timing constraints.

·Finally, we optimize the layout for reducing the design rule violations of the technology.

The above steps are repeated iteratively, to reduce the EM violations and maintain the design within the timing constraints.

A. Design Flow

Fig. 6. Customized design flow in commercial EDA tool.

Fig. 6 shows the flowchart of the proposed customized design flow in a commercial software tool to apply the proposed technique. First, the initial floorplan is modified into a contiguous layout that places modules operating at similar voltage levels in a region. The resulting floorplan is further optimized for the reduction in wire length. Secondly, the layout is power planned, followed by placement of the standard cell present in the design RTL netlist. Static Timing Analysis (STA) is performed to meet the desired timing constraint. Verification of AC limit in the interconnects is performed in the timing satisfied layout. Finally, using the proposed greedy methodology presented in this project, the desired current density limit is obtained in the EM affected nets.

B. Simulation Results

Assumptions: The following assumptions are considered in this paper,

·For a given RTL composite digital circuit, this article assumes that voltage assignment is performed using effective methods provided in the literature.

·For better analysis, this article considers that the design has been assigned three voltage levels, 0.9, 1.0 and 1.1 V.

Fig. 7. Floorplans of AES core circuit on iterative optimization.

·The initial floorplan is modelled using B * tree, and all modules of the voltage island are laid out within the island width of wI ⁽³⁸⁾. Further, the specification of the floorplan is given in the Table 3.

·Given a placed design, the static timing analysis performed in the MSV layout for achieving the positive Worst case negative slack (WNS).

·For verification of AC current limit this paper extracts the electromigration current limit for each metal layer from the technology library using ICT models.

To determine the EM current in the interconnect, in this work, after static timing analysis we will verify the AC current limit of each net. Table 2 gives simulation results using the proposed method to resolve EM violations. The proposed method starts with 2,094 EM violating nets as shown in Fig. 7(a). This method is applied iteratively on various nets mentioned in the second column of the Table 2 and the EM violations are reduced to zero. In each iteration, we explore critical networks with large wire length (WL), and perform up-sizing of logic cells, splitting of interconnect, and modify the spacing and width of the interconnect to reduce the EM violations and the slack time. Fig. 7 shows the layout of AES core design with iterative reduction of EM violations. Columns 4 and 5 give the peak current limit and peak current obtained in each iteration, respectively.

Furthermore, the Table 4 presents the effect of blech length before and after implementing the proposed solutions. Table 4 presents the metal layers affected due to EM in the column ”Layer”, the average on current in various EM nets with respect to metal layers in the column ”I(mA)”, blech length in μ m, ”Std. cell area” refers to the standard cell area, “WL” denotes the total wirelength and the technology specific EM current limit as ”I$_{\mathrm{Limit}}$”. The results reveal that the presented ideology 10% and 25% reduction in standard cell area and wirelength with 5% increase in the blech length of the EM affected net while maintaining I$_{\mathrm{Limit}}$ specific to each metal layer. It understood from the Table 1 that most of the works focuses on improving the wirelength, run time, measurement of current, and managing Biased Temperature Instability (BTI) on analog circuits.

However, the research work ⁽²⁵⁾ implements the proposed methodology in AES core circuit using adaptive voltage scaling method for low power. Similarly, the research work ⁽³⁹⁾ perform study in order to understand the impact of non-default layout rules in the AES core circuit in three wire segments. From the Fig. 8, it is clear that our proposed method offers 43% improvement in the Irms with ⁽³⁹⁾ and 6% current power saving with ⁽²⁵⁾.

Fig. 8. Impact of Iterative optimization.