1. ATPG-based Approaches

ATPG-based approaches are techniques, in which test vectors are manipulated to reach an optimization goal with no hardware changes or overhead (e.g. rerouting, splitting of scan chains). Generally, the manipulation of test vectors is performed via ‘X-filling’ or ‘don’t care-filling’ in such a manner that reduces the overall switching in the test vectors, resulting in optimization of power consumption during testing. The other common method is the application of test vector in a manner that minimizes the switching between two test vectors.

Test vectors consist of almost 90% ‘don’t-care’ or ‘X’ bits. These X-bits can be used for several goals such as test vector compression and test power reduction. Thus, filling the ‘X’ bits in test vectors can significantly reduce the test power consumption. S. Sivanantham et al. ⁽¹⁷⁾ proposed an algorithm to reduce both the capture power and shift power by using the X-filling technique. Similarly, S. B. Ch. et al. ⁽¹⁸⁾ defined the X-filling problem as the variant of interval coloring problem and achieved reduction in peak power. However, as stated earlier, these ‘don’t care’ bits are also used for test vector/data compression, thus using these X-bits to reduce the test power will affect the efficacy of the automatic test equipment (ATE).

The other technique used in ATPG-based approaches is test vector re-ordering. Test vector re-ordering reduces the test power consumption by minimizing the number of transitions between neighboring test vectors. T.Wu et al. ⁽¹⁹⁾ used the Ant Colony Optimization (ACO) heuristic algorithm after scan partitioning to reorder the test vector and reduce scan-shift power. Likewise, S. Mitra et al. ⁽²⁰⁾ introduced enhanced ACO to further reduce the power consumption. Despite these advantages, finding the optimal sequence for the test vectors is NP-hard and often requires significant time for computation.

2. DFT-based Approaches

DFT-approaches modify hardware architecture by either re-routing the scan chains or adding some circuitry to achieve the desired goal of reducing power. Reducing test data volume has also been considered as an effective approach under several built-in self-test (BIST) architecture.

Scan chain reordering method reorders the scan flip-flops to minimize the transition between adjacent scan cells during the shifting phase. S. Seo et al. ⁽²¹⁾ and S. Pathak et al. ⁽²²⁾ proposed scan chain reordering methodologies for the relocation of scan flip-flops. However, the complexity of reordering is a NP-hard problem and increases routing congestion consideration during the physical layout process. Scan chain splitting or partitioning methods divide scan chain into multiple smaller scan chains where additional control circuitry is required to exclusively access those scan chains. T. Yoshida et al. ⁽²³⁾ and T. Wu et al. ⁽²⁴⁾ proposed scan partitioning of the scan chain and achieved reduction in overall power consumption. Nevertheless, the additional circuitry causes area overhead and may result in performance degradation.

To prevent the propagation of transitions to the combinational circuitry, several techniques are studied. One such method includes the introduction of combinational gate at the output of the flip-flops, also known as the gating technique. The gating logic insertion prevents the switching activity of combinational circuit, thus reducing the total power consumption. Although the test power reductions are significant, this gating method requires large volume of test data and area overhead. To reduce the volume of test data, C. Barnhart et al. ⁽²⁸⁾ introduced OPMISR, which compresses the ATPG vectors based on MISR architecture. Additionally, the MISR reset operation after each scan operation provides independence of test patterns. This provides efficiency in the test without re-generating or re-simulating the test set to compute new signatures. Furthermore, test buffer that holds either the expected signature or expected test result is also reduced, resulting in a reduction of the data volume. Despite their apparent benefits, drawbacks to these techniques still exist, including large area overhead, timing overhead, and significant computational time required to manage test patterns and scan chain reordering. Even though the volume of test data and test time has been reduced, still the issue of excessive test power consumption should be handled. Therefore, in this study we present a modified scan test method with an exclusive shift-in and shift-out mechanism that is less intrusive to the circuit design, which significantly reduces test power consumption regardless of the design characteristics and bears small area overhead with reordering based on the number of fan-outs of the scan flip-flops.

1. Exclusive Shift-in and Shift-out Mechanism

In order to reduce test power consumption, an exclusive shift-in and shift-out mechanism is introduced which can significantly reduce the average number of transitions during the scan test. As depicted in Fig. 1(a), in a conventional scan test, the test stimuli of the current scan test pattern (i.e., s1~s6) and captured test results of the prior scan test pattern (i.e., r1~r6) are simultaneously loaded and unloaded to and from the scan flip-flops. On the other hand, the proposed scan test exclusively performs the shift-out and shift-in processes, as depicted in Fig. 1(b). To avoid overwriting the logic states of the scan flip-flops using the shift-in process before observing the captured test results, the shift-out process precedes the shift-in process. The proposed exclusive scan test can be summarized as follows:

1) A tester loads the test stimuli of the 1st scan test pattern into scan chains via external test channels (i.e., input and output (I/O) pads) using a shift-in process.

2) The test results from the functional paths corresponding to the loaded test stimuli are captured in the scan flip-flops.

3) The tester unloads the captured test results from scan chains through external test channels (i.e., shift-out). At the same time, the tester compares the unloaded test response with the expected response. To avoid unnecessary transitions by input value to the scan chain during shift-out process, the scan flip-flops, which unloads the valid test results, are initiated.

4) The tester loads the test stimuli of the next scan test patterns into scan chains.

Steps 2) to 4) are repeatedly performed until the last scan test operation is completed.

Fig. 2(a) and (b) present examples of the conventional shift process and proposed exclusive shift-in and shift-out mechanism, respectively. In this example, a design has 8 scan flip-flops. ‘H’ and ‘L’ indicate high and low logic levels of the captured data to be unloaded, respectively. And ‘1’ and ‘0’ indicate high and low logic levels of the test pattern to be loaded. Each arrow indicates either a 0${\rightarrow}$1 or 1${\rightarrow}$0 transition on a scan flip-flop. The example intuitively shows that the exclusive shift-in and shift-out mechanism results in a smaller number of transitions than the conventional scan test. During shift process of the conventional scan test, the next pattern bits are loaded into the scan chain simultaneously as the captured bits are unloaded. Thus, transitions occur across the entire chain of scan flip-flops. The exclusive shift-in and shift-out mechanism suppresses the transitions in the scan flip-flops by initializing those scan flip-flops. Therefore, the proposed scan test can significantly reduce the average number of transitions. However, this test requires twice the test time of the conventional scan test due to the exclusive shift-in and shift-out procedure.

2. Half-split Scan Chains with Test Channel Sharing

As depicted in the previous section, the test time doubles with the proposed technique due to the exclusive shift-in and shift-out processes of the test stimuli and their results. However, this problem is resolved because there are twice as many pins available for shift-in and shift-out processes, unlike the conventional test architecture (i.e. separate scan-in and scan-out port). The question then becomes how to divide the scan chains between the twice number of pins available now. Intuitively, dividing the scan chains in half would be the best solution which results in twice as many bi-directional pins and scan chains. Therefore, we divided the scan chains into two scan chains of equal length as depicted in Fig. 3.

With this division of scan chains, three facts can be observed. (1) The test time which may have been doubled remains the same as conventional scan test. (2) By using exclusive shift-in and shift-out method with the half-split scan chains, the same number of clock cycles is required for the proposed technique as the conventional test. (3) As a result, the number of transitions of proposed scan test is reduced, resulting in less scan test power.

Another problem that comes with lengthy scan chains is the supply voltage drop, which is also known as IR drop. Because of this voltage drop, the reliability of test cannot be guaranteed. T. Yoshida et. al. ⁽²³⁾ has shown that by splitting the scan chain length in half and applying the clock with the different duty cycle can significantly reduce the voltage drop problem. It is implied that voltage drop problem can also be resolved by reducing the concurrent switching activity. Likewise, the splitting of scan chains in half results in the reduced switching, thus the voltage drop problem can be solved.

The number of transitions during the conventional scan test, T$_{scan}$, can be calculated using Eq. (1) , where T$_{load}$(k) and T$_{unload}$(k) indicate the number of transitions required to load and unload the k$^{\mathrm{th}}$ test stimuli and result, respectively. T$_{bound}$(k) denotes the number of transitions occurring at the boundary of the k$^{th}$ test result and test stimuli, when the first bit of the k$^{th}$ test stimuli is loaded into the scan chain. Likewise, the number of transitions during the proposed scan test, T’$_{scan}$, can be calculated with Eq. (2) .

The parameters T$_{load}$(k), T$_{unload}$(k), and T$_{bound}$(k) are calculated using Eqs. (3)-(5), where P$_{k}$(i) and R$_{k}$(i) indicate the logic value of the i$^{th}$ bit in the kth test stimuli and the kth test result, respectively. Likewise, the values T’$_{load}$(k), T’$_{unload}$(k), and T’$_{bound}$(k) are calculated with Eqs. (6)-(8).

The difference in the number of transitions between the conventional scan test and the proposed scan test can be calculated by subtracting T’$_{scan}$ from T$_{scan}$, as shown in Eq. (9) .

Observations 1, 2, and 3 and theorem 1 below verify that the half-split scan chain architecture of the proposed scan test always results in fewer or the same number of transitions as the conventional scan test.

Observation 1. If any neighboring two bits in the first half of the kth test results have different logic values, the half-split scan chain architecture results in at least (n/2) fewer transitions than the conventional scan test for the shift-out process, where n is the length of a scan chain.

Proof. Suppose $R_{k}\left(j\right)=x,R_{k}\left(j+1\right)=\overline{x}$

where $1<j<\left(\frac{n}{2}- 1\right)$.

This implies that $\sum _{i=1}^{\frac{n}{2}- 1}(R_{k}(i)\oplus R_{k}\left(i+1\right))\geq 1$.

Then,

\begin{equation*} T_{\textit{unload}}\left(k\right)- T'_{\textit{unload}}\left(k\right)=\frac{n}{2}\times \sum _{i=1}^{\frac{n}{2}}\left(R_{k}\left(i\right)\oplus R_{k}\left(i+1\right)\right) \end{equation*}

Therefore, $T_{\textit{unload}}\left(k\right)- T'_{\textit{unload}}\left(k\right)\geq \frac{n}{2}$.

Observation 2. If any neighboring two bits in the second half of the k$^{th}$ stimuli have different logic values, the half-split scan chain architecture results in at least (n/2) fewer transitions than the conventional scan test for shift-in.

Proof. Suppose $P_{k}\left(j\right)=x,P_{k}\left(j+1\right)=\overline{x}$

where $\left(\frac{n}{2}+1\right)<j<\left(n- 1\right)$.

This implies that $\sum _{\frac{n}{2}+1}^{n- 1}(P_{k}(i)\oplus P_{k}\left(i+1\right))\geq 1$.

Then,

$T_{load}\left(k\right)- T'_{load}\left(k\right)=\sum _{i=\frac{n}{2}}^{n- 1}\left(\frac{n}{2}\times \left(P_{k}\left(i\right)\oplus P_{k}\left(i+1\right)\right)\right)$,

so $T_{load}\left(k\right)- T'_{load}\left(k\right)\geq \left(\frac{n}{2}\right)$.

Suppose $T'_{\textit{bound}}\left(k\right)- T_{\textit{bound}}\left(k\right)>0.$

Now

\begin{equation*} T'_{\textit{bound}}\left(k\right)- T_{\textit{bound}}\left(k\right)=- n\times \left(P_{k}\left(n\right)\oplus R_{k}\left(1\right)\right)+ \end{equation*}

\begin{equation*} \frac{n}{2}\times \left(P_{k}\left(\frac{n}{2}\right)\oplus R_{k}\left(1\right)\right)+\frac{n}{2}\times \left(P_{k}\left(n\right)\oplus R_{k}\left(\frac{n}{2}+1\right)\right) \end{equation*}

Observation 3. If the half-split scan chain results in more transitions than the conventional scan test at the boundary of the k$^{th}$ test results and test stimuli, the first half of the k$^{th}$ test results or the second half of the k$^{th}$ test stimuli has two neighboring bits with different logic values.

Proof. Suppose $T'_{\textit{bound}}\left(k\right)- T_{\textit{bound}}\left(k\right)>0.$

Now $T'_{\textit{bound}}\left(k\right)- T_{\textit{bound}}\left(k\right)=- n\times \left(P_{k}\left(n\right)\oplus R_{k}\left(1\right)\right)+$

$\frac{n}{2}\times \left(P_{k}\left(\frac{n}{2}\right)\oplus R_{k}\left(1\right)\right)+\frac{n}{2}\times \left(P_{k}\left(n\right)\oplus R_{k}\left(\frac{n}{2}+1\right)\right)$.

To satisfy the initial assumption,

$~ ~ P_{k}\left(\frac{n}{2}\right)\oplus R_{k}\left(1\right)=1$ or $P_{k}\left(n\right)\oplus R_{k}\left(\frac{n}{2}+1\right)\left(\frac{n}{2}+1\right)=1$.

where $P_{k}\left(n\right)\oplus R_{k}\left(1\right)=0$.

Assume $P_{k}\left(\frac{n}{2}\right)=x$ and $R_{k}\left(1\right)=\overline{x}$, then $P_{k}\left(n\right)=\overline{x~ }$.

This implies that $\sum _{i=\frac{n}{2}}^{n}(P_{k}(i)\oplus P_{k}\left(i+1\right))\geq 1$,

the second half of the k$^{th}$ test stimuli has neighboring two bits with different logic values.

Assume$P_{k}\left(n\right)=x$ and $R_{k}\left(\frac{n}{2}+1\right)=\overline{x}$, then $R_{k}\left(1\right)=x$

It implies that $\sum _{i=1}^{\frac{n}{2}}(R_{k}(i)\oplus R_{k}\left(i+1\right))\geq 1$,

So, the first half of the k$^{th}$ test result has neighbored two bits with different logic values.

Theorem 1. The half-split scan chain architecture of the proposed scan test always results in fewer or the same number of transitions as the conventional scan test.

Proof. Suppose the proposed scan test results in more transitions than the conventional scan test.

This implies $T'_{scan}- T_{scan}>0$.

Then, $T'_{\textit{bound}}\left(k\right)- T_{\textit{bound}}\left(k\right)>0$

because $T'_{load}\left(k\right)- T_{load}\left(k\right)=- \frac{n}{2}\times \sum _{i=\frac{n}{2}}^{n- 1}\left(P_{k}\left(i\right)\oplus P_{k}\left(i+1\right)\right)<0$ and

\begin{equation*} T'_{\textit{unload}}\left(k\right)- T_{\textit{unload}}\left(k\right)=- \frac{n}{2}\times \sum _{i=1}^{\frac{n}{2}}\left(R_{k}\left(i\right)\oplus R_{k}\left(i+1\right)\right)<0 \end{equation*}

Assume that $T'_{\textit{bound}}\left(k\right)- T_{\textit{bound}}\left(k\right)=\frac{n}{2}$

Then, either $T'_{load}\left(k\right)- T_{load}\left(k\right)\leq - \frac{n}{2}$ or

$T'_{\textit{unload}}\left(k\right)- T_{\textit{unload}}\left(k\right)\leq - \frac{n}{2}$ is found by observations 1, 2, and 3. So, $T'_{scan}- T_{scan}\leq 0$. This contradicts the initial assumption.

Assume $T'_{\textit{bound}}\left(k\right)- T_{\textit{bound}}\left(k\right)=n$

Then, $T'_{load}\left(k\right)- T_{load}\left(k\right)\leq - \frac{n}{2}$ and $T'_{\textit{unload}}\left(k\right)- $ $T_{\textit{unload}}\left(k\right)\leq - \frac{n}{2}$ is found by observations 1, 2, 3.

So, $T'_{scan}- T_{scan}\leq 0$.

This contradicts the initial assumption. Therefore, the proposed exclusive scan test cannot have more transitions than the conventional method.

3. Scan Chain Reordering

During the shift mode, transitions in scan patterns are also propagated to the combinational circuit thus causing the transition at the combinational circuitry level, which also contributes to overall energy consumption.

Fig. 4 shows a typical scan cell attached to a combinational circuit. This figure illustrates that the value of a scan cell is not blocked and propagated to the combinational logic. Alpaslan et al. ⁽²⁵⁾ states that the average number of transitions in the combinational logic of a benchmark circuit during scan shift is found to be 2.5 times more than the average number of transitions during the circuit’s normal functional operation.

Due to this reason, we also propose a simple scan chain re-ordering mechanism to further reduce the energy consumption during shifting operation. Since the number of fan-outs indicates the numbers of gates directly affected by a certain scan cell, we have chosen the number of fan-outs of each scan cell as the re-ordering parameter. If a transition occurs at a scan cell that has large number of fan-outs, it may toggle many gates connected resulting in excessive test power consumption.

Fig. 5(a) shows a typical scan chain attached to the combinational circuit. The number of fan-outs is shown at the output of each scan cell. Fig. 5(b) shows the reordered scan chain according to the number of fan-outs.

After reordering the scan cells based on fan-outs, test result will be shifted out exclusively while the scan cells are filled with ‘1’ or ‘0’ based on the value of the first scan cell. The above observation 4 is generally valid for scan test patterns in which reordered scan cells do not generate more transitions among adjacent cells ⁽²¹⁾. Sophiscated analysis for the scan test power, scan test patterns and scan chain reordering will be provided in the experimental section.

4. Hardware Architecture for the Proposed Scan Test

Fig. 6 illustrates the hardware architecture of the proposed exclusive scan test. All the flip-flops have been stitched into scan chains, which are accessed by external scan channels. The proposed scan test has two noticeable circuits, a shared test channel, and a scan initializer, shown as shaded blocks in Fig. 6.

1. At-speed Scan Test with the Proposed Scan Test

For at-speed testing, a launch process is required between the shift cycle and the capture cycle. Launch-on-capture (LOC) ⁽²⁶⁾ and launch-on-shift ⁽²⁷⁾ are well-known methods for the launch process.

The proposed method supports both LOC and LOS schemes for at-speed testing, as depicted in Fig. 8. Even though the proposed scan test requires a modified shift process for the exclusive shift-in and shift-out mechanism, the capture cycle is always preceded by the shift-in process, like the conventional scan test. Thus, the launch process and capture process are not affected by the exclusive shift-in and shift-out mechanism of the proposed scan test.

2. Scan Compression Technique with the Proposed Scan Test

The scan compression technique is an effective way to increase the number of scan chains. It loads the test stimuli to large number of scan chains and unloads the test results from large number of scan chains using a small number of input and output test channels, respectively. When the length of each scan chain is decreased, the test time can be significantly decreased. Most of the modern EDA (Electronic Design Automation) tools for design-for-testability (DFT), such as Synopsys DFTMAX and Mentor Graphics TestKompress, provide scan compression.

The proposed scan test complies well with the compressed scan architecture, as depicted in Fig. 9(a). Some compressed scan architectures use a fewer input test channels as compression operation mode control signals for the decompressor and compressor. This method increases the controllability and observability of the scan chains. The control channels cannot be shared since they should be driven during both the shift-in and shift-out processes. In this case, the test channels, except the control channels, are shared, as depicted in Fig. 9(b). The control channels drive the control data for the compressor and decompressor during the shift-out and the shift-in processes, respectively.

1. Experimental Descriptions

To check the efficacy of the proposed technique, eight benchmark circuits were used for verification: wb_conmax, usb_funct, pci_bridge, des_perf, ethernet and vga_lcd were selected from the IWLS’05 benchmark set, s38417 was selected from the ISCAS’89 and b19 was selected from ITC’99 benchmark sets. These circuits were carefully selected for experimental purposes as they cover a wide range of circuits, such as different circuit size, ratio of sequential circuits to combinational circuit, number of test patterns, and ratio of don’t care bits in their test pattern. Each circuit was synthesized with a 180nm CMOS process using Synopsys Design Compiler. Basic scan chains were inserted using Synopsys DFT compiler. Test patterns were generated using Synopsys TetraMax ATPG. Then the total transition was calculated using the Weighted Transition Metric (WTM), based on the test pattern generated by the ATPG.

2. Comparison of Transition under Half-split Scan Architecture with the Power-aware X-filling Method

Table 1 shows the number of transitions of a conventional scan test and proposed scan test scheme. The circuits were evaluated for both techniques by comparing the number of switching activities under random filling and adjacent filling technique. Random filling technique was used because it enhances the fault coverage. Adjacent filling method was used since it can be implemented easily and consumes far less time compared to other power-aware “don’t care” bit filling methods. Furthermore, adjacent filling can remove the “don’t care” bits from the test patterns more efficiently.

As shown in fourth column, the most evaluated benchmark circuit, i.e. vga_lcd and ethernet, test pattern consists of 99% don’t care bits. The 5th and 8th columns show the number of scan chains for each scan method. The number of switching activities that occurred while scanning in and out of the test patterns under random filling and adjacent filling techniques for conventional scan test, are tabulated in column six and seven. As previously discussed in section-III.B that the test time does not change when the splitting the scan chain and using the exclusive shift-in of scan patterns and shift-out of subsequent test results. Columns 9 and 11 contain the number of transitions using the proposed half-split scan method. Columns 10 and 12 shows the reduction in percentage between the proposed method and the conventional scan test using both random filling and adjacent filling, respectively.

Two scan chain configurations were applied for each benchmark circuit. (10 and 20) or (20 and 30) scan chains were inserted into each benchmark circuit depending upon the size of circuit. As the proposed half-split scan technique doubles the scan chains in a circuit, (20 and 40) or (40 and 60) scan chains were inserted depending upon the configuration selected for the conventional scan test. For small designs, (10 and 20) scan chain configuration were adopted, while for the larger circuits (20 and 30) scan chain configuration were used and accordingly for the proposed low power scan test method.

When using the proposed half-split scan method, most of the test cases showed a reduction in transitions from 45% to 55%. The reduction of switching activity differs depending on the circuits’ characteristics, the ratio of X-bits, and complexity of design. We also observed that complex designs showed lower reduction than smaller circuits with similar ratio of X-bits. Regardless of the ratio of X-bits and the size of the circuit design, the proposed half-split scan method still showed an average of 45% and 50% reduction in switching activity for adjacent filling and random filling, respectively.

3. Comparison of Transitions with Reordering

After splitting the scan chains, we used a scan chain reordering technique to further reduce the transitions. The ATPG patterns were generated with X-filling method, then, the “don’t care” bits were filled with random filling and adjacent filling. Table 2 shows the number of transitions before and after scan cell reordering for eight benchmark circuits. The first column shows the name of the circuit and the number of flip-flops. The second column represents the scan configuration of each design. Columns three and four show the number of transitions before scan cell reordering, and columns 5, 6, 7, 8 present the number of transitions after scan cell reordering and the ratio of reduction in switching activity both with random filling and adjacent filling.

As shown in Table 2, scan cell reordering with random filling was more effective than adjacent filling. Reordering scan cells with random filling and adjacent filling reduces transitions up to an average of 20%. However, the highest reduction of 41% was achieved by adjacent filling with 40 scan chains in wb_conmax module. The only anomaly is in b19 circuit with 60 scan chains, when patterns are filled with adjacent filling.

After reordering the scan chains, we performed the area optimization to reduce the number of scan initializers attached to each scan cells. Table 3 shows the number of transition during scan test, and area overhead caused by scan initializer of reordered scan chain (before optimization) and reordered scan chain (after optimization).

As shown in Table 3, each benchmark circuit requires 5-23% of area overhead caused by additional scan initializer to apply the proposed exclusive scan. Since there are several scan chain segments which has same scan cell order and fanout in each reordered scan chain, the number of scan initializer may reduce as shown in Fig. 7.

As a result of optimization, area overhead caused by additional scan initializer is reduced to 1-11%. In this case, the number of transition may increase, however, still the number of transition is far less compared to traditional scan method. In addition, the increase of transition (after optimization) was less when random filling is applied rather than adjacent filling is used for scan test.