Lee Jong-Yeol1
-
(The Division of Electronic Engineering, Jeonbuk National University)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Rotary variable differential transformer (RVDT), linear variable differential transformer (LVDT), signal conditioner (SC), coordinate rotation digital computer (CORDIC)
I. Introduction
Fig. 1. Example structure of four-wire RVDT
The LVDT and the RVDT sensors measure the linear and angular positions of moving parts,
respectively. The moving part is attached to the movable core of a transformer as
shown in Fig. 1. The core position changes the mutual inductance between the primary and the secondary
windings in proportion to the position of the core.
A sine wave, which is a primary excitation, is applied to the primary coil of a RVDT/LVDT
sensor to produce a double sideband suppressed carrier amplitude modulation (DSBSC-AM)
waveform with the amplitude proportional to the position of the core at the secondary
coil as follows:
where $r(t)$, $c(t)=A \cos \left(\omega_{c} t\right)$ and $m(t)$ are the output of
the RVDT/LVDT sensor, the primary excitation signal, and the angular or the linear
position information of the core, respectively. A signal conditioner is required to
extract the position information of the core, $m(t)$, from the output signal of the
RVDT/LVDT sensor, $r(t)$, which may be a form of DSBSC-AM demodulator (1).
Signal conditioners for RVDT/LVDT sensors can be categorized according to whether
synchronous demodulation is exploited or not. The methods without the synchronous
demodulation include the amplitude detection method (2), the spectral estimation method (3), the oscillator-based method (4,5), the dual slope conversion method (6), and the ratio-based method (7,8). In (2) a LVDT signal conditioner that exploits a peak amplitude detector to generate the
control signal for a sample and hold circuit to detect the core position. Since the
positional information of the core in a LVDT sensor can be found by calculating the
ratio between the output of the LVDT sensor and the primary excitation as in (1) where $m(t)=r(t) / c(t)$, the spectral estimation method calculates the ratio by
using the fast Fourier transform. The oscillator-based method treats the secondary
coils as an unknown differential inductance that is then measured using an oscillator-based
read-out circuitry. In the dual-slope conversion method, the primary coil is excited
with a triangular current waveform derived from a couple of DC reference voltages
producing the square shaped voltages in the secondary coils that are converted into
a digital output by performing the integration and de-integration on the sum of the
secondary voltages.
The figure-of-merit representing the linearity performance of a RVDT/LVDT signal conditioner
is the maximum linearity error that is the maximum deviation of a measured value from
a straight line between the maximum and the minimum values of a measurement. The linearity
performances of the amplitude detection, the spectral estimation, the oscillator-based,
the dual slope conversion methods are moderate. For example, the maximum linearity
errors of the oscillator-based and the dual slope conversion methods are 0.14% and
0.15% of full scale output (%FSO), respectively.
In the ratio-based method either the ratio of the difference and the sum of the secondary
signals or that of the difference of the secondary signals and the primary signal
is calculated.
Since there is the phase shift between the primary and the secondary signals, additional
phase shifting circuits must be used to correctly extract the position information
of the core. The synchronous demodulation methods are based on DSBSC-AM demodulation,
where the product of the RVDT/LVDT sensor output signal and the locally generated
carrier is low-pass filtered. To get the accurate position information of the core
the locally generated carrier must be in phase with the sensor output signal, which
requires the phase compensation. In previous works, the synchronous demodulation methods
are implemented by using blocks such as a peak sensitive demodulator (9), a multi-channel digital demodulator (10) and a Costas-loop based demodulator (11). The peak sensitive demodulator is a modified homodyne detector that carries out
a phase compensated synchronous demodulation of the differential output of a LVDT
sensor, where a direct digitization of the DSBSC-AM output at the carrier peaks is
performed. In (10) the digital adaptive synchronous AM demodulation is performed, where a prediction
technique is employed to recover the position information from the output signal of
a RVDT/LVDT sensor.
The signal conditioner in (11) performs DSBSC-AM demodulation by using a Costas loop, where both the primary excitation
signal and the sensor output signal are used and the phase error between the sensor
output signal and the locally generated carrier signal is corrected by using a feedback
mechanism and hence, the need for the phase matching circuitry is eliminated. Even
though the signal conditioner shows a better linearity performance than other methods
by exploiting digital signal processing techniques and can be used for more demanding
applications, the conditioner has disadvantages in that it requires large computational
efforts and high implementation costs.
This paper proposes a new RVDT/LVDT signal conditioner structure that achieves a smaller
area by removing some blocks in the signal conditioner of (11) which consists of five multipliers, three low-pass filters, one narrowband loop filter,
a threshold block and a numerically controlled oscillator (NCO) (12). The proposed signal conditioner achieves a small area by replacing three multipliers,
one low-pass filter, one narrowband loop filter and a threshold block with a CORDIC
block. The linearity performance of the proposed signal conditioner where the loop
error is calculated directly by evaluating an arctangent function is better than that
of the signal conditioner in (11) where the loop error is calculated indirectly as a sine function of the phase error
(13).
The organization of this paper is as follows. Sections II and III describe the operations
of the Costas-loop based signal conditioner and a general CORDIC algorithm, respectively.
The proposed area-optimized RVDT/LVDT signal conditioner structure and its implementation
are described in Section IV. After the experimental results are explained in Section
V, finally the conclusion is presented in Section VI.
II. Signal Conditioner Based-on Costas Loop
A signal conditioner for a RVDT/LVDT sensor such as the one in Fig. 1 converts the output of the sensor, $r(t)$, to a DC output voltage that represents
$m(t)$. One of the effective structures for RVDT/LVDT signal conditioning is based
on synchronous AM demodulation which exploits Costas loop as shown in Fig. 2.
In Fig. 2 the frequency of the primary excitation signal is fixed and the phase error, $\phi$,
between the output of a RVDT/LVDT sensor and that of the NCO is made zero by using
a feedback mechanism where the loop error, $e_{C O S T A S}(t)$, which indirectly
represents the phase error, is determined by evaluating the sine function that has
$\phi$ as its argument and is proportional to the phase error as follows:
Fig. 2. LVDT signal conditioner based-on Costas loop with blocks for sign (11). MUL3, MUL4, LFP4 and Threshold blocks are used to correct the sign of the demodulated
output.
since $\sin (\phi)$ is approximately equal to $\phi$ for small values of $\phi$, which
may cause the linearity error that is large in RVDT/LVDT applications where the linearity
requirement is very stringent. $\phi$ is typically non-zero upon startup and both
the in-phase and the quadrature signals, $i(t)$ and $q(t)$, are nonzero, which leads
to a non-zero $e_{COS T A S}(t)$ that is input into the phase increment input port
of the NCO and alters the phase of the NCO output waveform to make $\phi$ zero.
When the Costas loop in Fig. 2 is in the locked state, the output signals of the NCO become either $\cos \left(\omega_{c}
t\right)$ and $\sin \left(\omega_{c} t\right)$ or $-\cos \left(\omega_{c} t\right)$
and $-\sin \left(\omega_{c} t\right)$ because the loop error, $e_{COS T A S}(t)$,
is zero in both the cases. Therefore, the NCO output signals in the locked state can
be represented as $\cos \left(\omega_{c} t+\delta\right)$ and $\sin \left(\omega_{c}
t+\delta\right)$ where is either zero or $\pi$ radians. After the loop is locked,
the demodulated output signal can be found by multiplying a constant gain,$\frac{A}{2}$,
with $i(t)$ that has two possible values $\frac{1}{2} \times A \times m(t)$ and $-\frac{1}{2}
\times A \times m(t)$ when$\delta$ is zero and $\pi$ radians, respectively, which
is called a sign ambiguity.
The sign ambiguity is removed and the sign of the demodulated output is determined
by low-pass filtering the product in (3), which is done by using MUL3 and LPF4 in Fig. 2.
where $\cos \left(\omega_{c} t+\phi+\delta\right)$, $\theta$, and $A \cos \left(\omega_{c}
t+\theta\right)$ are the in-phase local carrier signal, the phase shift induced between
the primary and the secondary signals, and the primary excitation signal, respectively,
and $\phi$ is zero radians in the locked state. Low-pass filtering $s(t)$ removes
the high frequency component to produce $\frac{1}{2} A \cos (\theta-\delta)$, which
is positive or negative when $\delta$ is zero or $\pi$ radians, respectively, in the
locked state under the assumption that $|\theta| \leq \pi / 2$, which is valid for
a RVDT/LVDT sensor, and $A>0$. The output of Threshold block, which is $-1$ or $1$
for a negative or a positive input, respectively, is multiplied with the scaled $i(t)$
to produce the sign-corrected demodulated output.
Fig. 3. CORDIC operation in vectoring mode. For an input vector, $\left(x_{0}, y_{0}\right)$,
$\tan ^{-1}\left(\frac{y_{0}}{x_{0}}\right)$ can be calculated by accumulating the
angle of each rotation of which the direction is determined to minimize the y component
of the rotated vector.
Fig. 4. Structure of proposed signal conditioner. By using CORDIC block that is used
to calculate the loop error, the need for the sign ambiguity removal can be eliminated.
For the proper operation of the signal conditioner, the narrowband low-pass filter
whose the output is the approximate value of the phase error must have a small cutoff
frequency. The signal conditioner in (11) has a cutoff frequency of 10 Hz, which leads to a 257-tap digital low-pass filter.
III. Operation of CORDIC
A CORDIC is known to be a simple and efficient algorithm to calculate trigonometric
functions typically converging with one bit per an iteration (14). A CORDIC block can operate either in a rotation mode or a vectoring mode where an
arctangent function can be computed. As shown in Fig. 3, the CORDIC in a vectoring mode rotates the input vector until the resulting vector
is aligned with $\mathcal{X}$ axis by minimizing the $y$ component of the residual
vector at each iteration as follows:
where $d_{i}=1$ if $y_{i}<0$, $d_{i}=-1$ otherwise. When $y_{n}$ becomes zero, the
iteration stops and the residual vectors are as follows:
where $\left(x_{0}, y_{0}\right)$ is an input vector and $z_{n}$ becomes $\tan ^{-1}\left(\frac{y_{0}}{x_{0}}\right)$
if $z_{0}$ is set to zero.
IV. Proposed Signal Conditioner
In this section, the structure of the proposed signal conditioner and its implementation
are described. In the proposed signal conditioner, a CORDIC block is used to find
the phase error instead of a narrowband low-pass filter and a multiplier. By using
the CORDIC block the need for a sign ambiguity removal is also eliminated.
1. Structure
The proposed signal conditioner structure is shown in Fig. 4, where a CORDIC block is exploited to calculate the phase error, $\phi$, between
the local carrier signals and the output signal of a RVDT/LVDT sensor, which results
in the elimination of the blocks for the sign ambiguity removal, a multiplier and
a narrowband loop filter.
In the proposed signal conditioner no sign ambiguity occurs because the loop locks
at one value of a loop error signal, $e(t)$, that is calculated in radians by evaluating
an arctangent function unlike the signal conditioner in Fig. 2, where the loop locks under two different conditions. In Fig. 4 by inputting the in-phase signal,$i(t)=\frac{1}{2} m(t) \times A \cos (\phi)$, and
the quadrature signal, $q(t)=\frac{1}{2} m(t) \times A \sin (\phi)$, into $x(t)$ and
$y(t)$ inputs of CORDIC block, respectively, the block computes the arctangent function
as follows:
Fig. 5. Operation of extended CORDIC. An input is in (a) the second, (b) the third,
(c) the fourth quadrant. The symmetries over the y axis, the origin, and the x axis
are used for (a), (b) and (c), respectively.
The proposed signal conditioner shows a better linearity performance than the signal
conditioner in Fig. 2 because the loop error, which is the phase error, is calculated directly by using
an arctangent function as in (6) unlike Fig. 2 where the loop error is indirectly determined as a sine function of the phase error
based on (2) that results in a bigger linearity error.
The proposed signal conditioner has only one input that is fed with the RVDT/LVDT
sensor output whereas the signal conditioner in Fig. 2 has two input signals, the output signal of the sensor and the primary excitation
signal, which reduces the complexity of the systems that exploit RVDT/LVDT sensors.
By using CORDIC block, one low-pass filter, two multipliers and a threshold block
can be eliminated in the proposed structure since no sign ambiguity removal is necessary.
We can also remove a multiplier and a narrowband low-pass loop filter whose the number
of taps and the area are very large because the filter must have a large stop-band
attenuation and a narrow transition band for high selectivity, which results in further
reduction in the total area because the area of CORDIC block is much smaller than
that of the narrowband low-pass filter.
2. CORDIC Extension
In the proposed structure a first quadrant CORDIC whose the rotation angle is between
0 and $\pi / 2$ is extended to operate over between $-\pi$ and $\pi$ radians. To extend
the rotation angle the initial input vector, $\left(x_{\text {init }}\right.$, $\left.y_{\text
{init}}\right)$, is mapped into the first quadrant by using the symmetries over the
origin, the x axis and the y axis and then the first quadrant CORDIC computes the
arctangent function for the mapped vector, $\left(x_{m a p}\right.$, $\left.y_{m a
p}\right)$, of which the result is adjusted depending on the quadrant to which $\left(x_{\text
{init}}, y_{\text {init}}\right)$ belongs. The result of the first quadrant CORDIC,,
is adjusted by calculating $\pi-\beta$ and $-\beta$ for the second and the fourth
quadrants, respectively. For the vector in the third quadrant, the adjusted result
is $-\pi+\beta$, which is illustrated in Fig. 5.
3. Implementation
Fig. 6. Implementation procedure. High-level functional simulation is performed by
using the software in (15). The design software in (16) is used in the other steps.
Fig. 7. (a) Layout, (b) microphotograph of proposed signal conditioner chip. For the
efficient test of the implemented chip, it also has an ADC, two DACs and a waveform
generator that produces a 16-bit digital primary excitation signal.
Table 1. DAC, ADC and waveform generator specifications
Block
|
Specification
|
DAC
|
Architecture
|
R-2R ladder
|
Input
|
16 bits
|
Offset error
|
+/-0.2 % of $FSR^a$
|
Gain error
|
+/-0.4 % of FSR
|
Differential linearity error (DNL)
|
+/-4 LSB
|
Linearity error (INL)
|
+/-6 LSB
|
Digital input voltage
|
$V_{IH,MIN}$ = 0.7Vdd
$V_{IL,MAX}$ = 0.3Vdd
|
ADC
|
Architecture
|
SAR
|
Resolution
|
16 bits
|
SNR
|
96.8 dB
|
Sample rate
|
Max. 256 kSPS
|
DNL
|
+/0.8 LSB
|
INL
|
+/-0.8 LSB
|
Input offset error
|
+/-5 LSB
|
Waveform generator
|
Architecture
|
Lookup table based, 1/4 cycle compression, frequency and phase hopping
|
Table size
|
16 bits x $2^{16}$ words
|
THD
|
0.1%
|
Clock
|
160 kHz
|
$^a$ Full scale range
Table 2. Design parameters
Parameter
|
Value
|
Bit size (bits)
|
Signal conditioner input and output
|
16
|
Low-pass filter
|
input and output
|
16
|
accumulator
|
34
|
NCO
|
lookup table address
|
13
|
output
|
16
|
phase increment
|
32
|
CORDIC
|
output
|
32
|
lookup table address
|
5
|
look table element
|
32
|
Frequency (Hz)
|
Low-pass filter
|
passband edge freq.
|
250
|
stopband edge freq.
|
3,000
|
Sampling frequency
|
160,000
|
Filter size
|
Number of taps
|
64
|
The implemented signal conditioner chip contains both a digital part, which includes
the proposed signal conditioner and a waveform generator, and an analog part, which
includes an analog-to-digital converter (ADC) and two digital-to-analog converters
(DACs). The specifications of these blocks are summarized in Table 1. The proposed signal conditioner is implemented by following the procedure depicted
in Fig. 6. The first step is high-level functional simulation, where a block diagram based
high-level model is developed and simulated to determine design parameters summarized
in Table 2. After the design parameters are determined, a hardware description language (HDL)
model is developed. The HDL model is synthesized by using a standard 0.18 $\mu \mathrm{m}$
CMOS technology after verifying the HDL model by performing HDL functional simulation.
The synthesized gate-level netlist is verified by gate-level simulation after which
place & route operation is performed to generate the final layout in Fig. 7(a). The microphotograph of the chip implemented based on Fig. 7(a) is shown in Fig. 7(b) where the proposed signal conditioner occupies the area of 0.11 mm0.22 mm.
V. Experimental Results
1. Area
To compare the area of the proposed signal conditioner with that of the signal conditioner
in Fig. 2, the signal conditioner in (11) is modeled in a HDL and synthesized by using the same CMOS technology. The design
parameters and the operating frequency are the same in both cases. The areas of the
synthesis results are summarized in Table 3, where the area is represented in terms of the number of 2-input NAND gates that
is calculated by normalizing the total area of a signal conditioner with that of a
2-input NAND gate. As we can see in Table 3, the reduction in the total area is 44.1%, which is achieved by replacing the blocks
for the sign ambiguity removal, a narrowband low-pass filter and a multiplier with
a CORDIC block.
By using the proposed signal conditioner the number of ADCs can also be reduced. For
the hardware signal conditioner based on (11), two ADCs are needed because both the output of a RVDT/LVDT sensor, $r(t)$, and the
primary excitation signal, $c(t)$, are used as inputs. However, the proposed signal
conditioner needs only one ADC since it has only one input which is the RVDT/LVDT
sensor output.
2. Experimental Setup
In order to verify the function and to measure the performance of the proposed signal
conditioner chip, the experimental environment is set up as shown in Fig. 8, where a computer controlled actuator is used to rotate the shaft of a RVDT sensor
at a uniform speed. The frequency of the primary excitation signal in Fig. 8 is 10~kHz.
3. Functional Verification
The operation of the proposed signal conditioner is verified by following the general
verification procedure for a RVDT signal conditioner where the shaft of the RVDT is
rotated at various rotation frequencies to simulate sinusoidal motion. In the procedure
the output of the signal conditioner is a sinusoidal wave whose frequency is the same
as the rotation frequency.
As shown in Fig. 9 by applying FFT to the outputs of the signal conditioner, it is verified that the
frequencies of the outputs are the same as the rotation frequency. To also verify
the operation of the signal conditioner at a very low rotation frequency the shaft
is rotated with the rotation frequency of 0.22 Hz that corresponds to the angular
speed of $0.44 \pi$ radian/s as shown in Fig. 10.
4. Frequency Response
Fig. 10. Signal conditioner DAC output waveform. The shaft of a RVDT sensor is rotated
with a constant angular speed of $0.44 \pi$ radian/s.
Fig. 11. Frequency response of signal conditioners
The frequency (dynamic) response is measured by controlling the actuator to rotate
the shaft with the rotation frequency between 1 and 250 Hz whose results are plotted
in Fig. 11, where the frequency response of the proposed signal conditioner is almost the same
as that of (11). The maximum attenuations at 250 Hz are 1.35~dB and 1.56 dB in the proposed signal
conditioner and (11), respectively. Both the proposed signal conditioner and (11) show better frequency response than AD698 since they do not experience any significant
attenuation for frequencies below 150 Hz.
5. Noise Performance
Table 3. Areas of proposed signal conditioner and hardware signal conditioner implemented
by using Costas loop in (11)
Structure
|
LPFs
|
Narrowband LPF
|
MULs
|
CORDIC
|
Total area$^a$
|
Proposed
|
235,999
|
0
|
35,948
|
242,324
|
836,189
|
Hardware signal conditioner based on [11]
|
764,636
|
318,598
|
90,069$^b$
|
0
|
1,495,221
|
Reduction (%)
|
44.1
|
$^a$ The areas of the NCO and the constant multiplier, which are the same in both
signal conditioners, are included.
$^b$ The area of Threshold block is included.
Table 4. Noise performance of signal conditioners
|
AD698 in [11]
|
[11]
|
Proposed
|
F(dB)
|
16.5
|
18.5
|
18.8
|
Fig. 12. Example of maximum linearity error calculation by using (8).
The noise performance is measured by adding noise to the output of the RVDT as shown
in Fig. 8. To measure the noise performance input signal-to-noise ratio (SNR) is varied from
-6 dB to 30 dB by adding controlled amount of noise to a fixed power RVDT output signal.
The SNR of the output is also measured and a figure of merits (11) is calculated as follows:
The results are shown in Table 4, where the proposed signal conditioner shows a better noise performance than AD698
and (11).
6. Linearity
The maximum linearity error is calculated as a percentage of full scale output (FSO)
by using (8) as shown in Fig. 12where x and y axes represent the sample number and the angular position of the shaft,
respectively.
where $\mathcal{Y}_{m}$ and $\mathcal{Y}_{c}$ are the measured and the calculated
values of the angular positions, respectively, at the points whose $\mathcal{x}$ coordinate
is $\mathcal{x}_{c}$ where $\left|y_{c}-y_{m}\right|$ becomes maximum. $\left(x_{c},
y_{c}\right)$ is on the line segment connecting $\left(x_{0}, y_{0}\right)$ and $\left(x_{1},
y_{1}\right)$ where $y_{0}$ and $y_{1}$ are the minimum and the maximum angular positions,
respectively, that the RVDT used in the experiment can measure. The example in Fig. 12shows an example of the maximum linearity error calculation when the initial phase
error between the output signals of the sensor and the NCO is $\pi / 8$ radians, where
the maximum linearity error is 0.01%FSO.
he maximum linearity error of the proposed signal conditioner is calculated based
on the data collected from the digital output in Fig. 8. The maximum linearity errors of some signal conditioners are shown in Table 5, where the proposed structure shows a better linearity performance when compared
with other structures. We can see that the proposed structure provides as good linearity
performance as the commercial signal conditioner in (17).
VI. Conclusion
Table 5. Maximum linearity error of signal conditioners
|
[4]
|
[5]
|
[8]
|
[11]
|
[17]
|
Proposed
|
Max. linearity error (%FSO)
|
0.14
|
0.18
|
0.16
|
0.2
|
0.01
|
0.01
|
In this paper, a new area-optimized RVDT/LVDT signal conditioner structure is proposed.
In the proposed signal conditioner a CORDIC block replaces two low-pass filters, three
multipliers and one threshold block that are used to generate the loop error signal
and to determine the sign of the signal conditioner output. By employing the proposed
structure, the total area of the signal conditioner that is synthesized by using a
standard CMOS technology is reduced by 44.1% and the linearity performance comparable
to that of a state-of-the-art commercial signal conditioner is achieved.
ACKNOWLEDGMENTS
This work was supported by Jeonbuk National University.
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Author
Jong-Yeol Lee received the B.S., M.S., and Ph.D. degrees in electrical engineering
from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Republic
of Korea, in 1993, 1996, and 2002, respectively.
From 2002 to 2003, he was with Hynix Semiconductor which is currently SK Hynix.
Since 2004, he has been with Jeonbuk National University, where he is currently a
Professor with the Division of Electronic Engineering.
His research interests include embedded systems and their SoC implemen-tations.