I. INTRODUCTION

Recently, spiking neural network (SNN), which uses spike frequency and spike-timing interval for processing, has attracted attention for its biologically plausible characteristics and high energy efficiency ^(1,2). Spike-timing-dependent plasticity (STDP) is the best known SNN learning algorithm that updates synaptic weight based on the interval between pre-synaptic spike time ($t_{pre}$) and post-synaptic spike time ($t_{post}$) ⁽³⁾. In a non-transposable crossbar synapse memory, a column-wise weight vector can be accessed weight-by-weight only by activating all word lines (WLs) one-by-one, while a row-wise weight vector can be concurrently accessed by activating a single WL. For post-then-pre ($t_{post}$${-}$$t_{pre}$ $<$ 0) STDP learning step, all synaptic weights connected to one pre-synaptic neuron can be updated at the moment when the pre-synaptic spike occurs ($t_{pre}$) ⁽³⁾. Thus, the non-transposable synapse memory provides high throughput for post-then-pre STDP learning step in which each pre-synaptic spike incurs updating a row-wise weight vector. However, the throughput for the pre-then-post ($t_{post}$${-}$$t_{pre}$ $>$ 0) STDP learning, where each post-synaptic spike incurs updating a column-wise weight vector, is severely degraded.

Restricted Boltzmann machine (RBM) is another good exemplary neural network which prefers the transposable synapse memory. RBM is a generative stochastic artificial neural network that generates a probability distribution of the input data for applications including dimensionality reduction, classification, and feature learning ^(4-6). In RBM, the visible ($\boldsymbol{V}=\left[\begin{array}{llll}v_{0} & v_{1} & \cdots & v_{\mathrm{M}-1}\end{array}\right]$) and the hidden ($\boldsymbol{H}=\left[\begin{array}{llll}h_{0} & h_{1} & \cdots & h_{\mathrm{N}-1}\end{array}\right]$) layers form a bipartite graph, allowing inter-layer connections only, and the restricted connections between the two layers ($\boldsymbol{W} \in \boldsymbol{R}^{\mathrm{M} \times \mathrm{N}}$) allow an efficient learning with the gradient-based contrastive divergence (CD) ⁽⁷⁾. In the non-transposable synapse memory, hidden layer state can be computed with scalar-vector multiply-accumulate (MAC) operation because a row-wise weight vector can be accessed concurrently as shown in Fig. 1(a). On the other hand, visible layer state is computed with scalar-scalar MAC operation due to inefficient column-wise access in the non-transposable synapse memory as shown in Fig. 1(b). As a result, backward vector-matrix multiplication for a visible layer computation ($\boldsymbol{H} × \boldsymbol{W}^{T}$) in CD learning takes $O(n^{2})$ cycles, whereas it takes $O(n)$ cycles for forward vector-matrix multiplication for a hidden layer computation ($\boldsymbol{V} × \boldsymbol{W}$) when transposable read access to a synapse memory is not available.

To cope with the limited column-wise access speed in the non-transposable synapse memory, a transposable synapse memory using a custom 8T SRAM bit cell was introduced ⁽⁸⁾. However, the transposable 8T SRAM bit cell incurs significant area overhead compared to 6T SRAM bit cell due to the routing of additional WL and bit line (BL) for transposable access. In our previous work on a digital neuromorphic processing core ⁽⁹⁾, we presented a novel transposable addressing scheme leveraging 6T SRAM macros. However, the area overhead is still substantial due to duplicated periphery circuits and additional routing for clock, address and control signals.

In this paper, we propose a transposable crossbar synapse memory using 6T SRAM bit cell that provides the same bandwidth as the previous transposable synapse memories at the cost of much smaller area overhead.

Section II describes the previous works and section III presents the proposed memory structure. Section IV shows testchip implementation and measurement result and section V describes learning performance estimation. Finally, section VI concludes this work.

Finally, section VI concludes this work.

II. PREVIOUS WORKS

Fig. 2(a) shows an exemplary crossbar synapse memory that fully connects 4 pre-synaptic and 4 post-synaptic neurons, where $W_{i,j}$ represents a single-/multi-bit synaptic weight between a pre-synaptic neuron $v_{i}$ and a post-synaptic neuron $h_{j}$. In the synapse memory using 6T SRAM bit cell shown in Fig. 2(b), a row-wise weight vector, [$w_{i,0}$ $w_{i,1}$ $w_{i,2}$ $w_{i,3}$] where $i$ is the row address, can be concurrently accessed because no weight in the vector shares the same BL with the others in the vector. On the other hand, a column-wise weight vector, [$w_{0,j}$ $w_{1,j}$ $w_{2,j}$ $w_{3,j}$]$^{T}$ where $j$ is the column address, should be accessed weight-by-weight in sequence because all weights in the vector overlap on the same BL. As a result, column-wise access to the synapse memory using 6T SRAM bit cell becomes very slow.

In ⁽⁸⁾, a transposable synapse memory using a custom 8T SRAM bit cell shown in Fig. 2(c) was proposed, which allows concurrent access to a column-wise weight vector through additional WL ($WL^{T}$) and BL ($BL^{T}$). However, the additional routing of WL$^{T}$ and BL$^{T}$ in the custom 8T SRAM bit cell results in significant area increase up to 2.5${\times}$ compared to the 6T SRAM bit cell. Moreover, the custom 8T SRAM bit cell cannot be configured as a multi-bit array due to the routing for transposable access. Therefore, multiple single-bit arrays need to be used to implement multi-bit weight as shown in in Fig. 2(c).

To reduce the area overhead, we presented a transposable synapse memory using 6T SRAM macros ⁽⁹⁾. The transposable synapse memory is based on the two key schemes of synaptic weight relocation and transposable row addressing. The synaptic weight relocation scheme is to shift each row-wise weight vector [$w_{i,0}$ $w_{i,1}$ $w_{i,2}$ $w_{i,3}$] to the right direction by the row address $i$ as shown in Fig. 3. It relocates each weight $W_{i,j}$ at ($r$, $c$) where $r$ and $c$ represent row and column of the physical address in the synapse memory array. The physical address is calculated as

where $n_{col}$ is the number of columns.

In the baseline 6T SRAM bit cell array shown in Fig. 3(a), all weights in a column-wise weight vector [$w_{0,j}$ $w_{1,j}$ $w_{2,j}$ $w_{3,j}$]$^{T}$ overlap on the same BL $BL[j]$. On the other hand, in the bit cell array after the weight relocation shown in Fig. 3(b), no weight in a column-wise weight vector overlaps on the same BL with the other weights in the vector because both physical rows and columns increase by 1 as the logical row address $i$ increases in a column-wise weight vector. As a result, column-wise weights are diagonally relocated as shown in Fig. 3(b). Although each synaptic weight in Fig. 3 is single-bit 6T SRAM cell, it can be easily replaced to $n$-bit weight in Fig. 2(b) while maintaining the structure. In this case, each BL in Fig. 3 is replaced to $n$-bit BLs.

However, even after the relocation, a column-wise weight vector cannot be accessed concurrently because the physical row address, WL in other words, for each weight in the vector is different from each other (Fig. 3(b)). The transposable row addressing scheme splits the 2-dimensional synapse weight array into column chunks and changes the physical row address for each chunk depending on the access direction as shown in Fig. 4. For row-wise access shown in Fig. 4(a), the row addressing scheme sets the physical row addresses for all the chunks same as the logical row address $i$. On the other hand, for column-wise access shown in Fig. 4(b), the scheme calculates the physical row address $r$ for $c$-th chunk using Eq. (1). As a result, the physical row address for the 0-th chunk is 2’s complement of the logical column address $j$, ($n_{col}$ - $j$) in other words, and the row address increases by 1 as the chunk index increases. For example, to access a column-wise weight vector [$w_{0,1}$ $w_{1,1}$ $w_{2,1}$ $w_{3,1}$]$^{T}$ as shown in Fig. 4(b), the physical row addresses for the chunks are set to 3, 0, 1, and 2, respectively.

In our previous work on a digital neuromorphic processing core ⁽⁹⁾, we implemented a transposable synapse memory employing the two key schemes to speed up online learning. We used a barrel shifter to implement the synaptic weight relocation scheme as shown in Fig. 5. The barrel shifter shifts input row-wise (column-wise) weight vector to the right direction by the logical row (column) address $i$ ($j$) for write operation and shifts the read weights to the left direction for read operation. For the transposable row addressing scheme, we used 6T SRAM macros for the memory chunks shown in Fig. 4 and implemented transposable row addressing unit as shown in Fig. 5. However, the area overhead is still 1.83${\times}$ compared to the non-transposable synapse memory due to duplicated periphery circuits in SRAM macros and additional routing for clock, address and control signals. For further area reduction, we propose an integrated transposable synapse memory using 6T SRAM bit cell.

III. PROPOSED MEMORY STRUCTURE

The proposed transposable synapse memory eliminates the need for the periphery circuits and other control overhead by integrating the transposable row addressing scheme inside bit cell array. Fig. 6 shows the overall structure of the proposed transposable synapse memory, in which the transposable row addressing scheme is implemented using the integrated custom address decoder and row-transition multiplexer (MUX). The address decoder activates the WL corresponding to the input address for row-wise access ($Rb/C=0$) and the WL corresponding to 2’s complement of the input address for column-wise access ($Rb/C=1$). Row-transition MUXs are placed between every two adjacent memory chunks. Each row-transition MUX connects the upper input WL to the output WL for row-wise access ($Rb/C=0$) and connects the lower input WL to the output WL for column-wise access ($Rb/C=1$). In other words, the row-transition MUX connects WLs in the same row of two adjacent memory chunks for row-wise access and connects the WL in the lower (left) memory chunk to the WL which is one row above in the upper (right) memory chunk for column-wise access. For example, the address decoder activates the WL for $w_{1,3}$ to access row ⁽¹⁾ weight vector [$w_{1,0}$ $w_{1,1}$ $w_{1,2}$ $w_{1,3}$]. At the same time, all row-transition MUXs connect the upper input WLs to the output WLs to activate WLs for $w_{1,0}$, $w_{1,1}$, and $w_{1,2}$ concurrently. To access col ⁽¹⁾ weight vector [$w_{0,1}$ $w_{1,1}$ $w_{2,1}$ $w_{3,1}$]$^{T}$, the address decoder activates the WL for $w_{3,1}$ and all row-transition MUXs connect the lower input WLs to the output WLs to access $w_{0,1}$, $w_{1,1}$, and $w_{2,1}$ concurrently.

The barrel shifter is placed between IO buffers and write drivers/sense amplifiers and is shared for write and read accesses.

Meanwhile, the proposed integrated transposable row addressing using row-transition MUX needs to be modified for the memory array with column multiplexing. Fig. 7 shows the proposed integrated transposable row addressing for memory configuration with column multiplexing. In the configuration, the input address is divided into two parts, MSBs for WLs and LSBs for column selection lines (CSLs), and the two parts activate WLs and CSLs respectively. The row-transition MUXs for CSLs are placed between every two adjacent memory chunks same as for WLs. The row-transition MUXs for CSLs connect the upper input CSLs to the output CSLs for row-wise access and connect the lower input CSLs to the output CSLs for column-wise access. On the other hand, the row-transition MUXs for WLs connect the lower input WLs to the output WLs only when the MSB of the CSLs in the previous memory chunk is ‘1’ for column-wise access. In this way, the proposed row-transition scheme that integrates the transposable addressing scheme inside memory array works correctly for any configuration of synapse memory using 6T SRAM bit cell.

IV. IMPLEMENTATION AND MEASUREMENT

V. LEARNING PERFORMANCE ESTIMATION

We implemented cycle-based simulators for a SNN and a RBM to estimate STDP and CD learning performance gains. We used the standard MNIST data. The training and testing sets consist of 60,000 and 10,000 gray-scale images of 28${\times}$28 pixels. Because the number of pixels in each image of the MNIST data set is 784, we used 4 synapse memory macro models with 256${\times}$256 weights both for non-transposable and transposable synapse memories. The number of post-synaptic neurons was set to 256 considering the configurations of the synapse memory macros. In both estimations, we considered the cycle time increase of the proposed transposable memory structure.

VI. CONCLUSION

We presented a transposable synapse memory using 6T SRAM bit cell for fast online learning in neuromorphic processors. Based on the synaptic weight relocation using barrel shifter and the transposable row addressing using row-transition multiplexer, the proposed design enables the transposable memory access in the integrated SRAM array structure. The proposed memory shows 6.3${\times}$ and 19.3${\times}$ higher performance for STDP and CD learning algorithms with MNIST data set than the conventional non-transposable memory. The area overhead of the proposed design over the non-transposable memory was 26% only, which is much smaller than the area overheads in the previous works.