I. Introduction

Recently, the use of quad-high-definition (QHD) displays has grown rapidly not only for multimedia systems such as televisions, smart phones, and tablet PCs, but also for high-quality security surveillance camera systems. Those QHD display systems require a digital-to-analog converter (DAC) with high speed, high resolution, and small chip area. Most of high-speed DACs for display applications employ current-steering architect-tures with advantages in terms of their driving capability ^(1-3). Especially, to implement a highly linear current-steering DAC at high speed, a full thermometer-coded architecture is more suitable than binary-weighted or segmented topologies ^(1-3). However, the full thermometer-coded architecture leads to the exponential increase of the number of current cells as the resolution increases. Meanwhile, many calibration schemes have been proposed to improve the static and dynamic performances of high-resolution high-speed DACs ^(4-8), but those schemes cause the issues of increased circuit complexity and large area for digital circuits.

In this work, simultaneously to achieve the required small chip area, high resolution, and fast sampling rate without any calibration scheme, a 12-bit 180 MS/s current-steering DAC is presented with cascaded local-element-matching (C-LEM) techniques.

II. Architecture

The overall schematic of the proposed 12-bit 180 MS/s current-steering DAC employing C-LEM techniques is shown in Fig. 1. The proposed DAC is based on a full thermometer-coded feature to improve static performances and to reduce glitch errors. The current cells of the DAC consist of a total of four sub-current cell arrays, which are the most significant bit (MSB), two intermediate significant bits (ISBs), and the least significant bit (LSB) unary current cells. Each sub-current cell array is responsible for 7-bit thermometer codes. By configuring the bias current of lower sub-current cell arrays using that of the upper sub-current cell array sequentially, the 12-bit resolution DAC can be implemented with only 28 current cells. The bias voltages, BS<3> and BS<4>, required for the ISB1, ISB2, and LSB sub-current cell arrays, are not obtained directly from the global bias circuit. Instead, the two bias voltages are generated by level shifting two common node voltages (TC1 and TC2) of the upper sub-current cell array with a conventional source follower circuit to simplify the entire bias circuits and bias lines.

Fig. 1. Proposed 12-bit 180 MS/s current-steering DAC.

Fig. 2. Required current cells for (a) conventional 12-bit DAC with a full thermometer-coded architecture, (b) proposed 12-bit DAC with a cascaded local-element-matching scheme.

Fig. 3. Layout floor plan of the sub-current cell arrays.

The PMOS transistors of current cells and bias circuits, and the NMOS transistors of level shifters are implemented with 3.3 V high-voltage transistors supported by this CMOS process considering a differential output signal range of 2.0 V$_{\mathrm{P-P}}$ with the proposed bias scheme. On the other hand, digital circuits such as decoders for converting digital inputs to thermometer codes and digital latches for the switch driving circuits are implemented with 1.8 V nominal transistors.

III. Circuit Description

1. Proposed C-LEM Techniques

Commonly, a thermometer-coded topology is more advantageous for achieving high linearity at high speed operation. However, when a conventional 12-bit current-steering DAC is implemented with full thermometer-coded switching, a total of 4095 current cells is needed as shown in Fig. 2(a). In this particular case, it is difficult to implement a 12-bit level high-resolution DAC since the matching characteristics between all current cells should be considered very strictly ^(9-13). In the proposed C-LEM techniques, the 12-bit DAC can be realized using only 28 current cells, a reduction of 99.32 % compared to the number of cells required in a typical full thermometer-coded 12-bit DAC as shown in Fig. 2(b). Since the lower sub-current cell arrays use the bias voltage from the upper sub-current cell arrays, the current of the sequential current cells is automatically reduced to 1/8 times of the previous current cells.

The layout floor plan of the proposed sub-current cell arrays is summarized in Fig. 3. Each sub-current cell array is laid out sequentially to drive the adjacent lower sub-current cell array. Based on the proposed layout scheme, only the matching accuracies between current cells in each of the four sub-current cell arrays need to be considered.

As the DAC resolution increases, the number of the bias voltages for each of the sub-current cell arrays also tend to increase highly and the consequent bias circuits become more complex and require large area. The proposed DAC solves this problem fundamentally by employing a simple source follower-based level shifter to generate the required local bias voltages as described in Fig. 4. Two bias voltages, BS <1> and BS <2>, needed for the MSB and ISB1 sub-current cell arrays, are generated directly by the global bandgap reference (BGR) and bias circuits. Meanwhile, two separate bias voltages, BS <3> and BS <4>, needed for the ISB2 and LSB sub-current cell arrays, are obtained by dropping a constant voltage from two common node voltages, TC1 and TC2, of ISB1 and ISB2 sub-current cell arrays using a simple source follower-based level shifter. If the BS <3> and BS <4> are generated directly in the global BGR and bias circuits, such as the BS<1> and BS<2>, multiple-cascode current mirrors or complex bias circuits using more current branches can be required. It leads to additional device usage and power consumption; in addition, the required global bias lines from the bias circuits to sub-current cell arrays significantly increase implementation complexity and chip area.

Fig. 4. Bias voltages using source follower-based level shifters.

Fig. 5. Unit-current cell design considerations.

Fig. 6. Layout and die photo of the prototype DAC.

Fig. 7. Measured DNL and INL of the prototype DAC.

As a result, the proposed DAC architecture based on the C-LEM techniques is suitable for realizing a high resolution due to a relatively moderate local matching requirement between current cells ⁽¹⁴⁾. In addition, the reduced number of the current cells not only enables the area-efficient DAC implementation, but also minimizes the performance degradation caused by undesirable voltage drops along the power line.

IV. Measurement Results

The prototype 12-bit 180 MS/s DAC is implemented in a 0.18 ${\mathrm{\mu}}$m CMOS process, as shown in Fig. 6. The DAC occupies an active die area of 0.21 mm$^{2}$ and consumes 38.2 mW with an analog voltage of 3.3 V and a digital voltage of 1.8 V.

The measured DNL and integral non-linearity (INL) are within 0.50 LSB and 0.78 LSB, respectively, at a 12-bit resolution as shown in Fig. 7.

The measured DAC output spectrum at 180 MS/s with a 1 MHz input shows spurious-free dynamic range (SFDR) of 65.33 dB, as illustrated in Fig. 8(a). The SFDR variations are shown in Fig. 8(b) with increasing input frequencies at a sampling rate of 180 MS/s. When the input frequency is increased to the Nyquist frequency, the measured SFDR remains above 62.73 dB.

Table 1 shows a comparison between the proposed DAC and most recently reported DACs of similar specifications. The prototype DAC achieves competitive static and dynamic performances without any calibration, occupying a small chip area although implemented with 3.3 V high-voltage transistors in a 0.18 ${\mathrm{\mu}}$m CMOS process.

V. Conclusions

This work proposes a 12-bit 180 MS/s current-steering DAC for high-resolution, high-speed, and small ship area video applications. The proposed DAC employs C-LEM techniques significantly to reduce the required number of current cells in the DAC to 28, a reduction of 99.32 % compared to the number of current cells required in the conventional 12-bit full thermometer-coded switching. The overall bias circuits are highly simplified by generating the required bias voltages with a typical source follower-based level shifter. The prototype DAC is implemented using a 0.18 ${\mathrm{\mu}}$m CMOS process, and the active die area is 0.21 mm$^{2}$. The measured DNL and INL are 0.50 LSB and 0.78 LSB respectively, and the SFDR is a maximum of 65.33 dB at 180 MS/s. Output current and differential output voltage are 10 mA and 2 V$_{\mathrm{P-P}}$, with analog and digital power supplies of 3.3 V and 1.8~V respectively.