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  1. (Inter-University Semiconductor Research Center, Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, Korea)
  2. (Department of Electrical and Computer Engineering, Ajou University, Suwon 16499, Korea)

Tunnel field-effect transistor, TFET, line-edge roughness, LER effect, correlation coefficients


Recently, tunnel field-effect transistors (TFETs) have attracted many researching groups as the promising alternatives for metal-oxide-semiconductor FETs (MOSFETs) due to its low leakage current and small subthreshold swing (SS) (1-8). MOSFETs have theoretical limit of 60 mV/dec-SS at room temperature (i.e., 300 K) because their carrier injections are based on thermionic emission. Meanwhile, TFETs can overcome the limit since the function tail of Boltzmann distribution does not exist with the help of forbidden gap (1-8). In addition, the TFETs can be easily fabricated due to their good complementary MOS (CMOS) process compatibility (9-11). Therefore, there have been various attempts to demonstrate TFETs with the state-of-the-art technologies (12-19).

However, there exist various sources of process-parameter fluctuations such as random discrete dopants, oxide thickness variations and line-edge roughness (LER), which degrade the performance of FETs (16-19). Among them, LER effects are the most significant concerns with an aggressive scaling of minimum feature size (20). Previous papers have focused on changes in electrical characteristics [e.g. threshold voltages ($\textit{V}$$_{\mathrm{th}}$) or ON-state current ($\textit{I}$$_{\mathrm{ON}}$)] by a local dimension-variation from the LER effects (21-23). These studies suggest an easy way for an evaluation and for an insight about the effects of LER on TFETs’ electrical performances. However, there are a fundamental limit in providing quantitative analysis on how much LER effects are correlated to the electrical characteristics. Therefore, an advanced study about the LER effects in terms of the quantitative correlation factor should be performed.

This paper aims to report the influences of design parameters on the LER effects in nanowire TFETs and MOSFETs. Especially, this research focus on the channel LER since TFET’s electrical characteristics rarely depend on the channel length variation caused by gate LER (20). This paper is organized as follows. First, the structure and dimension of TFETs and MOSFETs are explained. Second, the influences of channel LER on nanowire TFETs and MOSFETs are compared comprehensively by using full three-dimensional (3D) technology computer-aided design (TCAD) simulation. Third, the channel LER effects are discussed by investigating the correlation coefficients ($\textit{R}$) for the $\textit{V}$$_{\mathrm{th}}$ and $\textit{I}$$_{\mathrm{ON}}$ with respect to the channel volume, and source-channel junction area.


Fig. 1. Schematic structures of (a) TFET, (b) MOSFET used in TCAD simulations. They feature nanowire channel structures with LER effects.


Fig. 1 shows the structures of nanowire TFET and MOSFET to compare the channel LER effects. The 3D TCAD simulations are performed by using Synopsys Sentaurus$^{\mathrm{TM}}$ and device design parameters are summarized in Table 1 (24). Both FETs are designed to have the same physical dimension except the dopant type of source. In these structures, the LER is randomly applied to make randomized deviation to the straight channel-mask edges. The LER function is made by the power spectrum of a Gaussian autocorrelation function (24). In the Gaussian model, two parameters of root mean square (${\Delta}$) and correlation length (${\Lambda}$) have been assumed to be 2 nm and 10 nm, respectively (19). Therefore, it makes all different mask edges which have same ${\Lambda}$ and standard deviation.

Table 1. The simulation conditions for LER effect



Channel radius ($R_{ch}$)

5 nm

Channel length ($L_{ch}$)

15 nm

Source/Drain length ($L_{S/D}$)

7.5 nm

Oxide thickness ($t_{ox}$)

2 nm

Drain doping conc.

10$^{20}$ cm$^{-3}$ (n-type)

Channel doping conc.

10$^{17}$ cm$^{-3}$ (p-type)

Source doping conc.

10$^{20}$ cm$^{-3}$


10$^{20}$ cm$^{-3}$


In order to rigorously examine TFET’s current-voltage characteristics, a dynamic nonlocal band-to-band tunneling (BTBT) and a Shockley-Read-Hall (SRH) generation-recombination models are used (21,22). In addition, a modified local-density approximation (MLDA) is applied to consider quantum effect. From the simulation results, $\textit{I}$$_{\mathrm{ON}}$ is defined as the drain current ($\textit{I}$$_{\mathrm{D}}$) when gate voltage ($\textit{V}$$_{\mathrm{GS}}$) is 2.5 V and drain voltage ($\textit{V}$$_{\mathrm{DS}}$) is 0.5 V. The $\textit{V}$$_{\mathrm{th}}$ is extracted at the $\textit{V}$$_{\mathrm{GS}}$ where the $\textit{I}$$_{\mathrm{D}}$ is 10$^{4}$ times higher than minimum $\textit{I}$$_{\mathrm{D}}$ ($\textit{I}$$_{\mathrm{OFF}}$).


Fig. 2. Transfer curves of 28 generated TFETs and MOSFETs. The $\textit{V}$$_{\mathrm{th}}$ and $\textit{I}$$_{\mathrm{ON}}$ are extracted and indicated in each figure.


Fig. 2 shows the simulated transfer curves of TFETs [Fig. 2(a)] and MOSFETs [Fig. 2(b)] under the influences of channel LER. In the simulation, 28 device structures of nanowire TFETs and MOSFETs have been generated and simulated, respectively. The SS of TFET and MOSFET are extracted to be 118 mV/dec and 151 mV/dec, respectively. The standard deviations for $\textit{I}$$_{\mathrm{ON}}$ (${σ}$$\textit{I}$$_{\mathrm{ON}}$) and $\textit{V}$$_{\mathrm{th}}$ (${σ}$$\textit{V}$$_{\mathrm{th}}$) can be extracted from the transfer curves. In (21-23), the analysis is performed for each LER case by confirming the variation of energy band diagram, ${σ}$$\textit{I}$$_{\mathrm{ON}}$ and ${σ}$$\textit{V}$$_{\mathrm{th}}$. However, each analysis result cannot provide quantitative correlation for several LER cases and is valid only for cases where the analysis has been performed. In order to obtain the reliable analysis, the correlation through regression analysis should be performed. The correlation coefficient ($\textit{R}$) for quantity $\textit{x}$ and $\textit{y}$ is defined as

$$\begin{equation*} R=\frac{cov\left(x,y\right)}{\sigma _{x}\sigma _{y}} \end{equation*}$$

where $\textit{cov}$($\textit{x}$, $\textit{y}$), ${\sigma}$$_{x}$ and ${\sigma}$$_{y}$ are the covariance and the standard deviations for quantity $\textit{x}$ and $\textit{y}$, respectively (26). The $\textit{R}$ values are assumed to be in the range from ${-}$1 to +1. A +1-$\textit{R}$ means a perfect positive correlation, while a -1-$\textit{R}$ means a perfect negative correlation. On the other hand, a 0-$\textit{R}$ means that there is no relationship (26). The channel LER effects are examined by extracting the $\textit{R}$ for $\textit{V}$$_{\mathrm{th}}$ and $\textit{I}$$_{\mathrm{ON}}$ with respect to the channel volume and source-channel junction area for the MOSFETs and TFETs, respectively (Fig. 3). Fig. 4 summarizes the $\textit{R}$ for each case. First, in the aspect of $\textit{V}$$_{\mathrm{th}}$, TFET shows the highest 0.913-$\textit{R}$ with respect to the source-channel junction area because the channel LER causes significant tunneling barrier width variation (20). On the other hand, MOSFET shows relatively high $\textit{R}$ for both the channel volume (-0.602-$\textit{R}$) and the source-channel junction area (-0.738-$\textit{R}$). It is because the $\textit{V}$$_{\mathrm{th}}$ of MOSFET is determined by an entire energy barrier at the channel. It is noteworthy that, unlike to the TFET, the $\textit{V}$$_{\mathrm{th}}$ of MOSFET shows the negative $\textit{R}$ for both geometrical parameters; the $\textit{V}$$_{\mathrm{th}}$ decreases as the source-channel junction area or the channel volume increases. It is attributed to the increase of short-channel effects (SCE) (e.g., drain-induced barrier lowering) (5). On the other hand, the $\textit{V}$$_{\mathrm{th}}$ of TFET is directly affected by the decrease of gate controllability as the source-channel junction area increases (i.e., positive $\textit{R}$), because it has high immunity to the SCE (8).

Fig. 3. Regression fitting curves between channel volume and (a) $\textit{V}$$_{\mathrm{th}}$, (b) $\textit{I}$$_{\mathrm{ON}}$ in TFETs, between source-channel junction area, (c) $\textit{V}$$_{\mathrm{th}}$, (d) $\textit{I}$$_{\mathrm{ON}}$ in TFETs, between channel volume, (e) $\textit{V}$$_{\mathrm{th}}$, (f) $\textit{I}$$_{\mathrm{ON}}$ in MOSFETs, between source-channel junction area, (g) $\textit{V}$$_{\mathrm{th}}$, (h) $\textit{I}$$_{\mathrm{ON}}$ in MOSFETs.


Fig. 4. $\textit{R}$ value between $\textit{V}$$_{\mathrm{th}}$, $\textit{I}$$_{\mathrm{ON}}$, channel volume, and source-channel junction area obtained from the channel LER effect for (a) TFETs, (b) MOSFETs.


Second, there is a similar correlation in terms of $\textit{I}$$_{\mathrm{ON}}$. In other words, the $\textit{I}$$_{\mathrm{ON}}$ of TFET mainly depends on the source-channel junction area, while the $\textit{I}$$_{\mathrm{ON}}$ of MOSFET depends on both the channel volume and the source-channel junction area. It is interesting that the $\textit{I}$$_{\mathrm{ON}}$ of both FETs are increased although the gate controllability is decreased as the source-channel junction area or the channel volume increases; positive $\textit{R}$. It is attributed to the definition of $\textit{I}$$_{\mathrm{ON}}$ [Fig. 2]. It is well known that the channel surface potential is rarely modulated by $\textit{V}$$_{\mathrm{GS}}$ after inversion layer formation, regardless of TFET and MOSFET (27). In short, the source-channel junction area and/or the channel volume directly determine the $\textit{I}$$_{\mathrm{ON}}$ ($\textit{R}$ > 0), because the $\textit{I}$$_{\mathrm{ON}}$ is extracted at high $\textit{V}$$_{\mathrm{GS}}$.

There is another noteworthy point in TFET that the $\textit{R}$ for $\textit{I}$$_{\mathrm{ON}}$ (0.415) is relatively lower than the $\textit{R}$ for $\textit{V}$$_{\mathrm{th}}$ (0.913) with respect to the source-channel junction area. Therefore, the relative weak correlation is investigated by extracting the source-channel junction area at different positions. If the area is extracted 0.5 nm away from the metallurgical source-channel junction to the source direction, $\textit{R}$ is 0.708 (Fig. 5, red dot line). On the other hand, $\textit{R}$ becomes 0.105 if the area is extracted 0.5 nm away from the metallurgical source-channel junction to the channel direction (Fig. 5, purple dot line). In detail, as $\textit{V}$$_{\mathrm{GS}}$ increases, the source region is depleted and the location of maximum BTBT rate is shifted from the metallurgical junction to the source direction (Fig. 5). Therefore, the $\textit{V}$$_{\mathrm{th}}$ of TFETs shows that it depends on metallurgical junction, while $\textit{I}$$_{\mathrm{ON}}$ depends on effective junction area.

Fig. 5. Cross-sectional view of nanowire-TFET. The color notes the BTBT rate.



The influences of channel LER on the MOSFETs and TFETs have been discussed with the help of $\textit{R}$. Based on the results, we found that the $\textit{I}$$_{\mathrm{ON}}$ and $\textit{V}$$_{\mathrm{th}}$ of the nanowire TFET are determined by the tunneling barrier width. In addition, considering the BTBT rate near source-channel junction, the region affecting $\textit{I}$$_{\mathrm{ON}}$ and $\textit{V}$$_{\mathrm{th}}$ is very narrow. In order to control the variation in nanowire TFET's $\textit{I}$$_{\mathrm{ON}}$ and $\textit{V}$$_{\mathrm{th}}$, more research should be performed on the tunnel junction area where $\textit{R}$ values are affected. In future works, research will have to be conducted to reduce the correlation in channel LER effect by increasing the source-channel junction.


This research was supported in part by the Brain Korea 21 Plus Project, in part by the MOTIE/KSRC under Grant 10080575 (Future Semiconductor Device Technology Development Program), in part by the NRF of Korea funded by the MSIT under Grant NRF-2019M3F3A1 A03079739 and NRF-2019M3F3A1A02072091 (Intelligent Semiconductor Technology Development Program). The EDA tool was supported by the IC Design Education Center (IDEC), Korea.


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Jang Hyun Kim

Jang Hyun Kim was born in Seoul, South Korea, in 1985.

He received B.S. degree in KAIST in Daejeon in South Korea, in 2007.

He received the M.S., and Ph.D. degrees in electrical engineering from Seoul National University, Seoul, South Korea, in 2009, and 2016, respectively.

His interests include low-power CMOS device and Thin film transistor.

Seong-Su Shin

Seong-Su Shin was born in Seongnam, Korea, in 1992.

He received a B.S. degree at Ajou university in 2018.

He is studying for a M.S. degree in electrical and computer engineering at Ajou Univ.

His interests include tunnel fieldeffect transistor (TFET) and contact resistance.

Min-Gyu Lee

Min-Gyu Lee was born in Suwon, Korea, in 1993.

He received a B.S. degree at Ajou university in 2019.

His interests include tunnel fieldeffect transistor (TFET).

Sangwan Kim

Sangwan Kim was born in Daegu, South Korea, in 1983.

He received the B.S., M.S., and the Ph.D. degrees in Electrical Engineering from Seoul National University, Seoul, South Korea, in 2006, 2008, and 2014, respectively.

He had been a postdoctoral scholar from 2014 to 2017 at the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, USA.

Since 2017, he has been a Faculty Member with Ajou University, Suwon, South Korea, where he is currently an Assistant Professor with the Department of Electrical and Computer Engineering.