I. INTRODUCTION

On-chip RC oscillators in a CMOS process have advanced to replace crystal-based oscillators for ultra-low power and small form factor applications, including digital hearing aids and ultrasonic transducers. High frequency stability of CMOS RC oscillators over process, voltage, and temperature variations is required for various sensor applications. A relaxation oscillator scheme is one of the good candidates for a CMOS RC oscillator to acquire high frequency stability over temperature variation ^(1-9). There are two modes to configure an RC relaxation oscillator: one is the voltage mode and the other is the current mode.

Current-mode relaxation oscillators were recently introduced to acquire both higher power efficiency and area compactness compared with voltage mode relaxation oscillators ^(1-3). Current sources and RC networks in current-mode relaxation oscillators have been optimized in previous works to compensate low frequency stability. However, an additional frequency divider can be required to get 50% duty cycle differential output. In ⁽⁴⁾, a relaxation oscillator that adopts a dual-phase mode configuration has obtained 50% duty cycle with extremely low power consumption. However, the oscillator, which has a frequency variation of 2% over 20 to 100 °C, is still not robust to temperature change.

In this letter, we propose a pseudo-differential relaxation oscillator in a 65-nm CMOS process. In order to bring the clock phase close to 50%, we designed a pseudo-differential comparator that can self-calibrate the phase. The temperature compensated RC networks in the comparators were designed to have a constant charge and discharge time according to temperature variation. The stable current references, which are generated by using two types of transistors with different temperature coefficients, reduced the additional frequency variation with regard to temperature. The proposed oscillator achieved a low frequency variation of 41.8 ppm/°C from 20 to 100 °C. The figure of merit (FOM) value of the proposed voltage-controlled oscillator (VCO) was 179.5 dB.

II. ARCHITECTURE

The core of the proposed relaxation VCO is shown in Fig. 1(a). It consisted of a current-mode comparator, set-reset (SR) latch, and inverter chain. Although a current-mode comparator can decrease the area and power ⁽³⁾, it has a single-ended output and high frequency variation with regard to temperature.

Fig. 1. Proposed relaxation VCO (a) architecture, (b) timing diagram.

Fig. 2. Proposed relaxation VCO schematic.

In this design, two identical current-mode comparators with RC networks were introduced to acquire a dual-phase signal with on/off status by switching alternately. When switches $\textit{S}$$_{1}$ and $\textit{S}$$_{3}$ were turned on, the current $\textit{I}$$_{ref}$ charged a capacitor $\textit{C}$$_{C2}$ of the right comparator, as shown in Fig. 1(b). In the opposite case, the current $\textit{I}$$_{ref}$ charged a capacitor $\textit{C}$$_{C1}$ of the left comparator.

The SR latch with the pseudo-differential inverter chain was able to reduce the mismatch between the dual-phase signals from each comparator ⁽⁴⁾.

The RC networks consisted of resistors and capacitors with different temperature coefficients (TC) to mitigate the charge and discharge period variations that occur with temperature change. Fig. 1(b) shows that the voltages $\textit{V}$$_{C1}$ and $\textit{V}$$_{C2}$ of the RC networks are given by

where$V_{{C_{C}}}$is the voltage charged by the capacitor, $\textit{V}$$_{initial}$ is the initial value at the resistor $\textit{R}$$_{C}$, $\textit{I}$$_{ref}$ is the reference current, and $\textit{T}$ is the period of the oscillator. Eq. (1) shows that a period of time at which $\textit{V}$$_{C}$$\textit{(t)}$ and $\textit{V}$$_{ref}$ concide can be maintained regardless of the temperature variation of $\textit{V}$$_{C}$$\textit{(t)}$ if the variations of $\textit{V}$$_{C}$$\textit{(t)}$ of by $\textit{${\Delta}$I}$$_{ref}$ and $\textit{${\Delta}$R}$$_{C}$ with temperature are cancelled.

III. CIRCUIT DESIGN

A schematic of the proposed VCO is shown in Fig. 2. The circuit comprised a pseudo-differential current-mode comparator, current reference with a voltage reference, and clock buffer.

We implemented the combined current source, which was composed of a current source ($\textit{M}$$_{R6}$~$\textit{M}$$_{R10}$) with a positive TC and a weighted current source ($\textit{M}$$_{R1}$~$\textit{M}$$_{R5}$) with a negative TC, by offsetting the two differences ⁽⁵⁾. Each current source was designed with two types of transistors that had different gate-oxide thicknesses to provide low frequency variation. It provided the current to the voltage reference, comparator, and clock buffer with the SR-latch. To compare $\textit{V}$$_{C}$ with $\textit{V}$$_{ref}$ precisely, $\textit{R}$$_{ref}$ had a series connection configuration of a p+ poly resistor and a p+ diffusion resistor that had opposite TC characteristics. As shown in Fig. 2, the voltage reference circuits configured with the combined current source and $\textit{R}$$_{ref}$ function to minimize the temperature change in $\textit{V}$$_{ref}$. The variation of $\textit{V}$$_{ref}$ is simulated to be under 0.2 mV in the temperature from 20 to 100 $^{\circ}$C. The clock buffer was adopted to the pseudo-differential inverter-chain with an ultra-low power current reference to reduce power consumption. The varactors $\textit{C}$$_{var}$ were connected with the RC networks of the comparator to acquire a tuning range of approximately 10%.

IV. MEASUREMENT RESULTS

The proposed relaxation VCO was implemented in a 65-nm CMOS process. Fig. 3 shows a chip photograph of the VCO. The die size of the VCO was 150 μm × 110 μm excluding pads. The chip, which was mounted on a 0.6-mm-thick FR4 printed circuit board (PCB) for DC biases, was connected to a SMA connector for measurement. The output spectrum was measured using an Agilent N9030A signal analyzer. The VCO including 3-stage buffers dissipated 40 μW with a supply voltage of 1 V. As shown in Fig. 4, the covered tuning range of the VCO ranges from 4.75 to 5.09 MHz with a control voltage range of 0 to 1 V. Fig. 5 shows that the average TC is 41.8 ppm/$^{\circ}$C from a temperature of 20 to 100 $^{\circ}$C at the control voltage of 1 V. In the whole control voltage range of 0 to 1 V, the VCO achieved 42-121 ppm/$^{\circ}$C of the low average TC from a temperature of 20 to 100 $^{\circ}$C, as shown in Fig. 6. Table 1 summarizes the performance of the proposed VCO and compares it with

Fig. 3. Chip photo of the implemented oscillator.

Fig. 4. Measured output frequency versus supply voltage.

Fig. 5. Measured output frequency versus temperature.

other state-of-the-art oscillators. The FOM is defined by

Fig. 6. Measured output frequency versus temperature in the whole control voltage range of 0 to 1 V.

where $\textit{P}$$_{DC}$ is DC power consumption in W, area is the chip size in mm$^{2}$, and $\textit{TC}$ is the temperature coefficient in ppm/°C ⁽⁴⁾. The proposed VCO has the highest FOM among published works.

V. CONCLUSIONS

We proposed a 5-MHz CMOS relaxation VCO that was composed of a pseudo-differential current-mode comparator with a low TC RC circuit. The proposed structure reduced the change of the charge and discharge periods. A current reference was configured with two types of gate-oxide transistor combinations to lower the frequency variation of the VCO during low power operation. The VCO achieved a low TC of 41.8 ppm/°C from 20 to 100 °C with a tuning range of 4.75-5.08 MHz. Under a supply voltage of 1 V, the VCO consumed 40~μW.