I. Introduction

CMOS image sensors (CISs) have been widely used in various applications such as mobile computing, security, and surveillance. As the applications of a CIS expands, demand for a small-size, high-resolution, and low-power analog to digital converter (ADC) is increasing for use in pixel column readouts. An incremental delta sigma ADC is considered an appropriate candidate for such applications.

For a fixed order of modulators, the signal to noise ratio (SNR) of incremental delta sigma ADCs can be improved either by increasing the oversampling ratio (OSR) or the quantizer resolution. However, the former requires the ADC to run with a higher clock frequency and the latter complicates the ADC design due to the use of a multi-bit digital to analog converter (DAC). Both methods eventually lead to an increase in the power consumption and the size of the ADC. It is known that the required power consumption or the size of an ADC quadruples for every 6dB increase in SNR.

In order to be employed in a column parallel ADC architecture⁽¹⁾, the ADC power and size should be limited to fit within a small pixel pitch. An extended counting technique which reuses the residual voltage of an ADC to increase the ADC resolution ⁽²⁾ is a good candidate as the column ADC of a CIS. In ⁽³⁾ and ⁽⁴⁾, the extended counting technique was successfully applied in an incremental delta-sigma ADC for an array application such as a biosensor array. However, the ADCs still occupied a large chip area, and they would not be suitable for a column parallel ADC architecture.

In this work, the extended counting technique is applied in a modified form to minimize the circuit components and the control signal for a second-order incremental delta-sigma ADC. The proposed incremental delta sigma ADC has a feedback loop that consists of the two-bit ADC’s MSB. Further, the ADC combines the LSB of the final conversion with the decimation filter output. To further reduce the chip size and power consumption of the ADC, a self-biased amplifier is shared between the two adjacent stages in the modulator.

The extended-counting incremental delta-sigma ADC, which occupies a die area of 0.0026 $mm^2$, has been fabricated in a 0.18-${\mathrm{\mu}}$m CIS process. The ADC achieves a 65 dB signal-to-noise and distortion ratio (SNDR) and consumes a total current of 25 ${\mathrm{\mu}}$A from a 1.8 V supply, resulting in a figure of merit (FOM) of 101 fJ/conversion step.

The remainder of this paper is organized as follows. Section II introduces the proposed extended-counting incremental delta-sigma ADC, and the implementation details of the ADC are explained in section III. Measurement results and conclusions are provided in section IV and V, respectively.

II. Proposed Extended - Counting

Incremental Delta - Sigma ADC

A linearized model of the extended-counting incremental delta-sigma ADC is shown in Fig. 1. It consists of two integrators, a two-bit flash ADC which is used as an internal quantizer, and a decimation filter. The modulator architecture is the same as the one proposed in ⁽⁵⁾ except that, instead of a single-bit quantizer, a 2-bit quantizer is used to implement the proposed extended-counting technique in this work. A Sinc2 filter consisting of a counter and an accumulator is used as a decimation filter.

As shown in Fig. 1, the modulator works as a conventional delta-sigma modulator utilizing a single-bit quantizer. Only the most significant bit (MSB) of the 2-bit quantizer output is fed back to the input node of the first integrator. The least significant bit (LSB) of the quantizer output, which is generated by using the last input sample, is later added to the output of the decimation filter.

The transfer function from the modulator input VIN(z) to the output of the decimation filter $Y_1$(z) can be calculated as follows by using the linear model shown in Fig. 1.

where A(z) and B(z) are the denominator and the numerator of the signal transfer function. These values are determined by the integrator gains ($a_1$ and $a_2$), respectively. $k_1$ is the quantizer gain and is determined by behavioral simulations. $E_1$(z) is the quantization error of the single-bit quantizer. Note that, even though the two-bit quantizer is used in the modulator, only the MSB of the quantizer output is used for the signal feedback. Hence, the effective resolution of the quantizer is one-bit. The transfer function from VIN(z) to Y2(z) can be calculated as follows

where $k_2$ is the gain of the 2-bit quantizer.

The final output $D_{OUT}$(z) can be calculated by adding $Y_1$(z) with Y2(z) as follows

In (7), $E_1$(z) can be removed by setting $a_1$, $a_2$, and $k_2$ equal to 1/3, 1/2, and 1, respectively. This leaves only $E_2$(z) which is theoretically four times smaller than $E_1$(z). However, $E_1$(z) cannot be totally removed in a real implementation mainly due to a low DC gain of the amplifier, and because of capacitor mismatches between the capacitors used in the integrators. The measurement results show that the SNDR and the effective number of bits (ENOB) are improved by 3 dB and 0.5-bit, respectively.

It should be mentioned that the hardware complexity of the ADC has to be carefully considered because the width of the ADC cannot exceed two times the pixel pitch in the column-parallel architecture. This is the main reason for the difficulty in using a multi-bit quantizer in the delta-sigma ADC for a CIS. Table 1 compares the number of circuit components related to the quantizers for a single-bit and two-bit conventional ADCs and the circuit components for this work. In the conventional two-bit quantizer, as shown in Table 1, the required circuit components for the DWA and decimation filter are more than double those for the single-bit quantizer. However, the number of circuit components required in this work, though it uses a two-bit quantizer, is almost identical to that necessary for the single-bit quantizer.

III. Circuit Implementation and Operation

Fig. 2 shows a simplified circuit diagram and clock signals of the modulator. It consists of two integrators and three comparators with a two-bit encoder working as a quantizer. The upper side of the switched-capacitor circuit in the Fig. 2 functions as the first integrator and the lower side is the second integrator. The two integrators are realized in a single-ended configuration because the pixel generates an output voltage in a single-ended fashion. Furthermore, an amplifier is shared by the integrators to reduce chip area and power consumption. As shown in Fig. 3, a self-biased amplifier with switches added for amplifier sharing ⁽⁵⁾ is adopted in this work. To increase the gain of the amplifier, the sizes of the input PMOS and NMOS transistors are enlarged. This enlargement increases the parasitic capacitance associated with the input transistor. The input parasitic capacitance was carefully calculated by using a simulator, and was taken into account when the filter coefficients of the modulator were realized to suppress quantization noise.

The operation of the modulator is as follows. The main clock and the ADC enable signal (EN) are externally applied the reset signal (RST) which is low and non-overlapping clocks ($\phi_{1}$ and $\phi_{2}$) are generated by an internal clock generator. The pixel output is sampled by the sampling capacitor ($C_1S$) of the first integrator when $\phi_{1}$ is high, and transferred to the feedback capacitor ($C_1F$) when $\phi_{2}$ is high. Next, the output of the first integrator is processed by the second integrator in the same manner as did the first integrator using $\phi_{1}$ and $\phi_{2}$. The second integrator output is finally converted into a digital code by using the quantizer. Once the conversion process is finished, the reset signal (RST) toggles and the ADC is reset to an initial state for the conversion of the next pixel signal.

IV. Measurement Results

A 384 ${\times}$ 200-pixel CIS employing the proposed ADC was fabricated in a 0.18-${\mathrm{\mu}}$m 1P4M CIS process. The die micrograph of the CIS, which occupies 5.5225 $mm^2$ (2.35mm ${\times}$ 2.35 mm), is shown in Fig. 4. The ADC takes up a die area of 0.0026 $mm^2$ (8.8 ${\mathrm{\mu}}$m ${\times}$ 300 ${\mathrm{\mu}}$m). A 2-shared four-transistor active pixel architecture is used. The ADCs for even columns and odd columns are placed at the upper and lower sides of the pixel array.

Fig. 5 shows the measured dynamic performance and the FFT plot of the ADC with a sinusoidal input frequency and an amplitude of 1.67 kHz and 0.75 $V_{P-P}$% (peak-to-peak voltage), respectively. The ADC was tested with and without the application of the extended counting for an OSR of 64. The measured FFT result of the ADC with extended counting is plotted using black lines, and the result without the use of extended counting is plotted as gray lines. The measured SNDR and ENOB, which are calculated by the formula (SNDR {--} 1.76)/6.02, are 62 dB and 10-bit, respectively, without the application of extended counting. The SNDR, and hence, the ENOB improve by 3dB and 0.5-bit, respectively, by the application of extended counting. As shown in Fig. 6, the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.49 / ${-}$0.22 and +0.61 / ${-}$0.64 LSB, respectively. The ADC draws a current of 25 ${\mathrm{\mu}}$A from a 1.8 V supply, resulting in a power dissipation of 45 ${\mathrm{\mu}}$W.

It is the amplifier that consumes most of the ADC power. Table 1 compares the results from the state-of-the-art incremental delta-sigma ADCs with a CIS fabricated using similar technologies. Two popular FOMs, which are referred to as ${FoM}_{W}$ and ${FoM}_{A}$ in the Table 2, are used to make a fair comparison of the ADC performance. The FOMs of this work are the smallest among the FOMs of the ADCs fabricated with the same technology. Furthermore, they are comparable to the FOMs of the ADCs fabricated using the advanced processes.

V. Conclusion

A low-power and small-size extended-counting incremental delta-sigma ADC for a CIS has been presented. A new extended counting method is applied to a second-order incremental delta-sigma ADC without increasing hardware complexity and power consumption. To further reduce the ADC size and power consumption, a self-biased amplifier was shared between the adjacent integrators.

A CIS employing the proposed ADC has been fabricated in a 0.18-${\mathrm{\mu}}$m CIS process and occupies a die area of 5.5225 $mm^2$. The ADC itself occupies an active area of 0.0026 $mm^2$ and the measured SNDR and ENOB of the ADC running at a sampling clock of 20 MHz are improved, respectively, from 62 dB and 10-bit to 65 dB and 10.5-bit by using extended counting. The measured DNL and INL are +0.49 / ${-}$0.22 and +0.61 / ${-}$0.64 LSB, respectively. The ADC draws a current of 25${\mathrm{\mu}}$A from a 1.8 V supply and achieves ${FoM}_{W}$ and ${FoM}_{A}$ of 101 fJ/Conv-step and 0.266 fJ·$mm^2$/Conv-step, respectively ^(6-8).