1. Operation

The hysteretic current-mode buck dc–dc converter in Fig. 1 closes a feedback loop that, in keeping output $v_O$ near reference $v_R$, supplies the current that the load requires. Transconductor $G_{OSC}$ is an oscillator that ripples inductor $L_O$'s current $i_L$ across a window that comparator $CP_{OSC}$'s hysteretic thresholds set and about a level that amplifier $A_E$ dictates with $v_{ERR}$. So together, $A_E$ compares $v_O$ and $v_R$ to generate an error $v_{ERR}$ that adjusts the level about which $G_{OSC}$ oscillates $i_L$ to match and supply the current $i_{LD}$ that the load demands.

Fig. 1. Hysteretic current-mode buck.

Fig. 2. Measured inductor current in continuous conduction mode (CCM).

The system delivers power by energizing and draining $L_O$ from the input $v_{IN}$ into $v_O$ in alternating phases of the oscillating period tOSC. When transistor $M_{IN}$ energizes $L_O$ with energizing voltage $v_E$ or $v_{IN}$ – $v_O$, $i_L$ in Fig. 2 rises across energizing period $t_E$\. $i_L$ similarly falls when switch $M_G$ drains $L_O$ with drain voltage $v_D$ or –$v_O$ across drain period $t_D$. $i_L$ ripples this way about the load level the feedback loop sets with $v_{ERR}$

When $L_O$'s and $C_{IL}$'s corner frequencies with $R_{IL}$ and RLESR are well below the oscillating frequency f$_{OSC}$, $sL_O$ and $R_{IL}$ overwhelm RLESR and 1/$sC_{IL}$ near f$_{OSC}$. So $L_O$'s voltage $v_L$ is $i_L$$sL_O$, $v_C$ is $v_L$/$sR_{IL}$$C_{IL}$ or $i_L$$L_O$/$R_{IL}$$C_{IL}$, and $v_I$ is $i_L$(10$L_O$/$R_{IL}$$C_{IL}$) or $i_L$$A_R$ where current sense gain $A_R$ equals:

$v_I$ therefore rises and falls with $i_L$, and when $v_I$ reaches comparator $CP_{OSC}$'s upper threshold, $CP_{OSC}$ trips low to open $M_{IN}$ and close $M_G$, and that way, end $t_E$. The opposite happens when $v_I$ falls to $CP_{OSC}$'s lower threshold to end $t_D$. $i_L$ oscillates this way across the window that $CP_{OSC}$'s hysteresis $V_{HYS}$ sets with V$_{HYS}$/$A_R$ and about the level that $v_{ERR}$ sets with $v_{ERR}$/$A_R$. Together, $R_{IL}$, $C_{IL}$, $CP_{OSC}$, $M_{IN}$, $M_G$, and $L_O$ realize an oscillator $G_{OSC}$ that oscillates $i_L$ about $i_{LD}$.

Fig. 3. Measured inductor current in discontinuous conduction mode (DCM).

Fig. 4. Voltage-mode hysteretic control for buck converters.

When load current $i_{LD}$ falls below half of $i_L$'s ripple Δ$i_L$, $i_L$ can reverse, and that way, burn unnecessary power. Comparator $CP_{ZCS}$ keeps this from happening by sensing and opening $M_G$ when $i_L$ reaches zero. In this way, like Fig. 3 shows, $i_L$ falls to zero and remains at zero in discontinuous-conduction mode (DCM) until the next cycle. But since Δ$i_L$ is less than prescribed by V$_{HYS}$/$A_R$, $v_O$ must rise above $v_R$ to trip $CP_{OSC}$. In other words, $v_O$ rises slightly when $i_{LD}$ falls in DCM.

2. Variants

The voltage-mode counterpart of the hysteretic current-mode buck is the most compact hysteretic buck because $v_O$ and $v_R$ feed directly into $CP_{OSC}$ like Fig. 4 shows ^[10], without using $A_E$ or a current sensor. Unfortunately, the circuit requires a resistive $C_O$, the equivalent series resistance (ESR) of which produces higher ripple in $v_O$. Adding a current sensor without gain and feeding its output $v_I$ into $CP_{OSC}$ remove this requirement ^[11,12]. This way, $CP_{OSC}$ keeps $v_O$ near $v_R$ because $v_I$ is $v_O$ + $v_C$. $v_C$'s $i_L$$L_O$/$R_{IL}$$C_{IL}$, however, appears as an offset in $v_O$. The purpose of $A_E$ in Fig. 1 is to eliminate this offset. The state of the art adds peripheral blocks to Fig. 1 to keep the oscillating frequency constant ^[11-13]. These additions, however, do not alter the stability limits and effects of the hysteretic core.

Fig. 5. System-level block diagram modeling current loop as transconductance G$_{\mathrm{OSC}}$.

Hysteretic current-mode boost and buck–boost configurations are also possible. What changes in these configurations are the voltages $v_E$ and $v_D$ that energize and drain $L_O$. $v_E$, for example, is $v_{IN}$ instead of $v_{IN}$ – $v_O$, and $v_D$ in the boost is $v_{IN}$ – $v_O$ instead of just –$v_O$ ^[14]. So as long as the analysis is with respect to $v_E$ and $v_D$, the mechanics explained here apply to all configurations. The output diode or switch in boost and buck–boost topologies, however, produce the effect of an out-of-phase, right-hand-plane (RHP) zero $z_{RHP}$ that does not appear in buck converters ^[14]. But as long as the unity-gain frequency $f_{0dB}$ is below $z_{RHP}$, which is a necessary requirement for these converters, all stability conditions are the same.

1. Hardware

The 0.6-$mm^2$ 0.18-μm CMOS die in Fig. 7 integrates the error amplifier $A_E$, oscillating comparator $CP_{OSC}$, dead-time logic, power transistors $M_{IN}$ and $M_G$ and their drivers, and zero-current sensing comparator $CP_{ZCS}$. The current sensor, inductor $L_O$, and output capacitor $C_O$ are off chip on the two-layer board alongside test circuits used for experiments. $L_O$ and $C_O$ measure 10.7 × 10 × 5.4 and 1.6 × 0.81 × 0.91 mm3 and incorporate 15 and 4 mΩ, respectively.

Fig. 7. Prototyped 0.18-μm CMOS die and two-layer board.

Fig. 8. Measured output voltage regulation across output load and input voltage.

Fig. 9. Measured response to 40-, 80-, and 180-mA load dumps.

Fig. 8 shows the average output voltage $v_O$ across load level $i_{LD}$ at two input voltage $v_{IN}$ operating points. $v_O$ decreases with increasing $i_{LD}$ due to its finite output resistance at a rate, i.e. load regulation, of 77 mV/A. Across the same loading, the worst-case output voltage difference $\Delta v_O$ is 1.4 mV which results in a line regulation of 4.7 mV/V.

2. Response

The measured output $v_O$ in Fig. 9 ripples 5 to 10 mV and responds within 5.6 μs to rising 40-, 80-, and 180-mA load dumps. Response time tR is basically how long $L_O$ requires to slew $i_L$ across these load steps. The system responds faster (within 3.4 μs) to similar falling load dumps because $L_O$'s drain voltage $v_D$ is higher at $v_O$'s 1.0 V than $L_O$'s energizing counterpart $v_E$, which is $v_{IN}$ – $v_O$ or 1.5 – 1.0 V, which is 0.5 V.

Fig. 10. Measured load-dump response when the input is 1.4 and 1.8 V.

Phase margin essentially quantifies the propensity of a feedback loop to oscillate when perturbed. In this case, $v_O$ in Fig. 5 is more prone to ringing when responding to rising than to falling load dumps. This is because $L_O$ requires more time to respond to rising loads. In other words, the bandwidth pole of the oscillator is lower, and as a result, closer to the unity-gain frequency $f_{0dB}$ of the loop. Similarly, the ringing worsens as the load step increases from 40 to 180 mA because $L_O$ requires more time to slew across wider load steps. Ringing also worsens as input voltage falls in Fig. 10 from 1.8 to 1.4 V for the same reason, because with a lower voltage across $L_O$, $i_L$ slews more slowly.

Using Eqs. (2-8), phase margins for 40-, 80-, and 180-mA load dumps are 75°, 62° and 40°, respectively. These calculated margins correspond well with Fig. 9. The 40-mA load dump response, for example, is closer to the over-damped response that 90° produces. The under-damped response to the 180-mA load dump rings 2–3 times before settling. This corresponds to the response that 45° produces.

3. Efficiency

$A_E$, $CP_{OSC}$, $CP_{ZCS}$, $M_{IN}$, $M_G$, the drivers, and dead-time logic consume quiescent, ohmic, and switching power P$_Q$, PR, and $P_{SW}$. As load current $i_{LD}$ climbs, output power $P_O$ increases linearly, whereas PR rises quadratically. Up to at least 200 mA, however, $P_O$ outpaces PR, so power-conversion efficiency ηC in Fig. 11 generally increases with $i_{LD}$. Although PR is very low below 5 mA, $P_O$ is also low, so P$_Q$ and $P_{SW}$ become large fractions of $P_O$. This is why ηC drops below 88% abruptly when $i_L$ is less than 5 mA.

Fig. 11. Measured power-conversion efficiency.