(Fatemeh Abbassi)
(SungJin Kim)
(Abdolhamid Noori)
(Ji-Hyeon Cheon)
(Kang-Yoon Lee)
1†
-
(Department of Electrical and Computer Engineering, Sungkyunkwan Univ., Suwon, 440-746,
Korea)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Subthreshold region, low power, band gap reference circuit, low-dropout regulator, resistor-less
I. INTRODUCTION
In recent years, many literature and research are focusing on low power design for
micro-scale energy efficient systems that have limitation due to battery lifetime.
Design of these kind of systems i.e., wireless sensor networks, smart sensors, implantable
medical devices and IoT are challenging in terms of various strict requirement to
achieve small chip area, low-power consumption and long term reliability.
Furthermore, a bias current or a reference voltage that is resistant to process variations
and temperature is an essential block for all the analog or mixed signal circuits.
Therefore, there is a high demand for nano-watt bandgap reference (BGR) and Low-Dropout
regulator (LDO) that can meet the stringent constraints forced by low power application.
In conventional bandgap references (BGRs), the complementary-to-absolute temperature
(CTAT) voltage was generated using V$_{\mathrm{BE}}$ of a Bipolar Junction Transistor
(BJT). Then the negative temperature slope of CTAT part was compensated using the
ratio between resistors designed in the proportional-to-absolute-temperature (PTAT)
voltage circuit (1). Current consumption in nano-ampere range needs larger resistors for specified voltage
and occupies larger area. Hence, developing resistor-less references has made low-power
subthreshold region design more efficient (2). In addition, in low voltage references, subthreshold MOSFETs used instead of BJTs
(3). Reference (3) presents a nano-watt MOS-only voltage reference with two stage high-slope PTAT generators
implemented in a 0.18 ${\mathrm{\mu}}$m standard CMOS technology. In this brief, proposed
CTAT structure in (3) is employed and designed in 65 nm CMOS technology. Then temperature coefficient of
CTAT is compensated using only one stage enhanced PSRR high slop PTAT stage. Thus,
much chip area can be saved.
General LDOs include an error amplifier (EA) and pass devices in addition to BGR.
To increase the power efficiency and decrease power consumption of LDO, power dissipation
of the EA needs to be minimized. Operating in subthreshold region leads to less current
consumption in transistors (4). In addition, replacing big resistors in low power designs, decreases chip area significantly.
Combining these two blocks, an ultra-low power MOS-only BGR-LDO are proposed in this
paper exploiting subthreshold operation to reduce power consumption to less than
1${\mathrm{\mu}}$W and chip size.
The paper organization is as follows: In Section II the overall LDO architecture is
presented. Section III discusses the detail idea of each block. The measurement results
are demonstrated in Section IV and Section V is conclusion.
II. ULTRA-LOW POWER LOW-DROPOUT REGULATOR
1. Ultra-low Power LDO Architecture
Fig. 1 shows the top block diagram of the proposed LDO. BGR generates a VREF voltage that
is insensitive to PVT variations, and the LDO receives this voltage to produce a stable
LDO OUT voltage. In order to improve the PSRR at high frequencies, an external capacitor
(C$_{\mathrm{EXT}}$) was added to the LDO OUT.
Fig. 1. The proposed architecture for low power IoT application.
2. Nano-Watt MOS-only Voltage Reference
Fig. 2 demonstrates implemented circuit of the designed Band-Gap voltage reference.
Fig. 2. The implemented circuit of Nano-Watt MOS-Only Band-Gap Voltage Reference.
This structure consists of a nano-ampere current reference circuit provides bias for
single stage of PTAT voltage generators. In addition, it operates as a CTAT voltage
to avoid using extra circuitry, decrease area and power consumption
(3). Following sub-sections, describe the operating principles of the MOS-only Band-Gap
voltage reference circuit.
3. CTAT Voltage Generator and Nano-Ampere Current Reference
Fig. 3 depicts the schematic of the employed CTAT voltage generator and current reference
with startup circuit (3). Except for the start-up circuit and pMOS resistor (M$_{\mathrm{R}}$) that is in
both deep triode and strong-inversion region, all transistors operate in subthreshold
region.
Fig. 3. The schematic of CTAT voltage generator and Nano-ampere current reference(3)
Similar to
(3), V$_{\mathrm{CTAT}}$ can be derived as
(1):
where V$_{\mathrm{TH0}}$ is the threshold voltage at 0 K, mN is the temperature exponent
of electron mobility, ${\mu}$$_{\mathrm{n0}}$ is the mobility at T$_{0}$, and ${\kappa}$
is the TC of V$_{\mathrm{TH}}$, which is negative. In addition, from obtained derivation
of the TC of V$_{\mathrm{CTAT}}$ in
(2), verifying the second term of equation to be much less than that of ${\kappa}$, indeed
k$_{1}$ will be negative.
4. PTAT Voltage Generator
Fig. 4 illustrates the proposed one stage PTAT voltage generator, which has enhanced PTAT
voltage slope (3) and Power Supply Rejection Ratio (PSRR). In this structure, employing two cross-coupled
nMOS/pMOS pairs (M$_{\mathrm{D3}}$/M$_{\mathrm{D5}}$ and M$_{\mathrm{D4}}$/M$_{\mathrm{D6}}$)
in the asymmetric differential cell, lead to higher voltage slope. Also, utilizing
cascode tail current (M$_{\mathrm{B1}}$, M$_{\mathrm{B2}}$), PSRR of one stage PTAT
enhanced.
Fig. 4. The proposed architecture of PTAT voltage generator.
When the tail current source is fixed, size of the transistors determines the share
of current to each branch. The gate-to-gate voltage of this block (V$_{\mathrm{GG}}$
= V$_{\mathrm{out}}$ ${-}$V$_{\mathrm{in}}$) is given by
(3).
Using Eq.
(3), the gate-to-gate voltage in terms of aspect ratios of corresponding transistors
can be obtained as
(4).
where K represent the aspect ratio of the MOSFET and V$_{\mathrm{TH,D21}}$=V$_{\mathrm{TH,D2
}}$${-}$ V$_{\mathrm{TH,D1}}$. As a result, output reference voltage of ULP BGR is
derived, presented in
(5).
PTAT is designed so that using only one stage, T.C. of CTAT is compensated while PSRR
is kept in required value. Considering the effects of sizing and V$_{\mathrm{TH}}$
mismatches of MOS transistors, and process variations on the slopes of the PTAT and
CTAT voltages, besides the reference voltage value, Monte-Carlo simulation and all
corner simulation have been done.
5. Subthreshold based Resistor-less MOSFET Lowdropout Regulator
Fig. 5 shows a schematic of a proposed LDO consisting only of MOSFETs. The proposed LDO
Error Amplifier operates in the subthreshold region, minimizing power consumption.
Unlike conventional LDOs (7), diode-connected MOSFETs (M$_{\mathrm{N10}}$, M$_{\mathrm{N11}}$, M$_{\mathrm{N12}}$),
which replace feedback resistors (8), minimize die area and power consumption of LDO. The output voltage of the LDO is
calculated as follows:
Fig. 5. The schematic of subthreshold based resistor-less LDO Regulator.
IV. MEASUREMENT RESULTS
Fig. 6 illustrates a microphotograph of the proposed LDO. The die size of BGR-LDO is 195
${\mu}$m x 390 ${\mu}$m.
Fig. 6. Chip microphotograph.
Fig. 7 demonstrates Monte-Carlo simulation result of the reference voltage. The average
reference voltage is 707.577 mV and the ${\sigma}$ is 34.18 mV. Monte Carlo simulation
for considering mismatches between transistors and process variation is done for 100
samples.
Fig. 7. The Monte-Carlo simulation result of proposed BGR output.
As shown in
Fig. 8, variation of LDO output voltage affected by varying temperature from -40 $^{\circ}$C
to 80 $^{\circ}$C is 2 mV. Therefore, TC is around 16 ppm/$^{\circ}$C.
Fig. 8. The measurement result of TC of LDO output.
As shown in
Fig. 9, the proposed LDO increases the LDO output voltage by 8 mV when the input voltage
VDD changes from 1.8 V to 3.6 V. Therefore, the line regulation is 4.4 mV/V.
Fig. 9. The measurement result of line regulation of LDO output.
Fig. 10 shows the load regulation characteristics of the measured LDO. When the load current
varies from 0 A to 10 mA, the LDO output voltage changes by 8 mV. Therefore, the line
regulation of LDO is 0.8 mV / mA.
Fig. 10. The measurement result of load regulation of LDO output.
Fig. 11 shows the measured transient response according to VDD variation of the LDO. When
the VDD voltage changes from 1.8 V to 3.3 V, the output of the LDO changes from 1.204
V to 1.212 V.
Fig. 11. The LDO measurement result of transient response of VDD variation.
Fig. 12 depicts the measurement results of the PSRR characteristics of the LDO attached C$_{\mathrm{EXT}}$
of 1 uF. The VDD voltage was measured at 3.3 V and the PSRR value at DC frequency
is -55 dB. The worst PSRR is -22.5 dB at 190 kHz.
Fig. 12. The measurement result of PSRR of LDO output.
Fig. 13 illustrates the measured transient response according to Load variation of the LDO.
When the Load current changes from 0 A to 10 mA, the output of the LDO changes from
1.200 V to 1.192 V.
Fig. 13. The LDO measurement result of transient response of Load variation.
Fig. 14 demonstrates the simulation results of frequency response of the LDO at no load and
full load conditions. When the Load current is 0 A and 10 mA, frequency response of
the LDO are 55$^{\circ}$ and 89$^{\circ}$ respectively.
Fig. 14. Frequency response of the LDO at no load and full load conditions.
Table 1 summarizes the performance of the proposed LDO measurements and compares with previous
works. The proposed BGR and LDO circuit fabricated in a 55 nm CMOS process. The measurement
results of PSRR is -55 dB at DC frequency, a TC of 16 ppm/$^{\circ}$C within a range
of the -40 $^{\circ}$C to 80 $^{\circ}$C and line regulation of 4.4 mV/V for supply
voltage variation from 1.8 V to 3.6 V. Load regulation is 0.8~mV/mA for load current
variation form 0 A to 10 mA. It consumes 747 nW power for input voltage of 3.3 V.
The active area is 190 ${\mathrm{\mu}}$m ${\times}$ 390 ${\mathrm{\mu}}$m.
Table 1. Comparison performance Table
|
Parameter
|
This work
|
[8]
|
[9]
|
|
Process (nm)
|
55
|
55
|
65
|
|
Supply voltage (V)
|
1.8 ~ 3.6
|
2~3.6
|
0.75~1.2
|
|
Output voltage (V)
|
1.2
|
1.2
|
0.5
|
|
Line regulation (mV/V)
|
4.4
|
200
|
6.67
|
|
Load regulation (mV/mA)
|
0.8
|
0.72
|
0.56
|
|
TC (ppm/°C)
|
16
|
-
|
-
|
|
PSRR (dB) @ 100 Hz
|
-55
|
-13.4
|
-46
|
|
Power Consumption (nW)
|
747
|
396
|
19440
|
|
Chip Area (mm2)
|
0.074
|
0.11
|
0.0096
|
V. CONCLUSION
This paper presents the ultra-low power bandgap reference and LDO circuits for low
power applications such as internet of things (IoT) and energy harvesting. This structure
is designed in sub-threshold region and it consumes 747 nW power for input voltage
of 3.3 V. The measurement results illustrate -55 dB power supply rejection ratio,
a TC of 16ppm/$^{\circ}$C within a range of the -40 $^{\circ}$C to 80 $^{\circ}$C
and line regulation of 7.6 mV/V for supply voltage variation from 1.8 V to 3.6 V.
Load regulation is 0.73 mV/mA for load current variation form 0 A to 10 mA. The processed
design of bandgap reference circuit employs high slop PTAT voltage to decrease number
of PTAT stages required for compensating negative TC of CTAT. The processed design
of bandgap reference circuit using low voltage threshold devices is useful for low
power system and sensitive supply voltage.
ACKNOWLEDGMENTS
This was supported by Basic Science Research Program through the National Research
Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning
(2017R1A2B3008718).
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Author
Fatemeh Abbassi received the B.Sc. degree in electrical engineering from the K.N.
Toosi University of technology, Tehran, Iran, in 2011 and the M.Sc. degree in electrical
engineering (Microelectronics) from the Sharif University of Technology, Tehran, Iran,
in 2013. She is currently working toward the Ph.D. degree in School of Information
and Communi-cation Engineering at the IC Lab, Sungkyunkwan University, Suwon, Korea.
Her research interests include CMOS RF transceiver and Power IC design.
SungJin Kim received his B.S. degree from the Department of Electronic Engineering
at Inje University, Kimhea, Korea, in 2014, where he is currently working toward the
Combined Ph.D. & M.S degree in School of Information and Communication Engineering,
Sungkyunkwan University. His research interests include CMOS RF transceiver and wireless
power transfer systems.
Abdolhamid Noori received the B.Sc. degree in electrical engineering from the K.N.
Toosi University of technology, Tehran, Iran, in 2011 and the M.Sc. degree in Photonic
engineering from the AmirKabir University of Technology, Tehran, Iran, in 2014. He
is currently working toward the Ph.D. degree in School of Information and Communication
Engineering at the IC Lab, Sungkyunkwan University, Suwon, Korea. His research interests
include CMOS RF transceiver and Power IC design.
Ji-Hyeon Cheon received his B.S. degree from the Department of Electronic Engineering
at Inje University, Kimhae, Korea, in 2017, where he is currently working toward the
M.S degree in School of Information and Communication Engineering, Sungkyunkwan University.
Her research interests include CMOS RF transceiver and Power IC design.
Truong Van Cong Thuong received his B.S. degree in Electrical and Electronic Engineering
from Ho Chi Minh City University of Technology, Ho Chi Minh, Viet Nam. He is currently
pursuing M.S degree from School of Information and Communication Engineering at Sungkyunkwan
Univer-sity, Suwon, Korea. His research interests include Power IC Front-End, LDO
and DC-DC converter.
Truong Thi Kim Nga received B.S degree from Department of Elec-tronics and Telecommunication
at Danang University of Technology, Danang- Vietnam and M.S degree in School of Information
and Commu-nication Engineering, Sungkyunkwan University, Suwon, Korea. She is currently
working toward the Ph.D degree at School of Information and Communication Engineering,
Sungkyunkwan University, Suwon, Korea. Her research interests include wireless power
transfer system and Power IC design.
Kang-Yoon Lee received the B.S. M.S., and Ph.D. degrees in the School of Electrical
Engineering from Seoul National University, Seoul, Korea, in 1996, 1998, and 2003,
respectively. From 2003 to 2005, he was with GCT Semicon-ductor Inc., San Jose, CA,
where he was a Manager of the Analog Division and worked on the design of CMOS frequency
synthesizer for CDMA/PCS/PDC and single-chip CMOS RF chip sets for W-CDMA, WLAN, and
PHS. From 2005 to 2011, he was with the Department of Electronics Engineering, Konkuk
University as an Associate Professor. Since 2012, he has been with School of Information
and Communication Engineering, Sungkyunkwan University, where he is currently an Associate
Professor. His research interests include implementation of power integrated circuits,
CMOS RF transceiver, analog integrated circuits, and analog/digital mixed-mode VLSI
system design.