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  1. (Department of Electronic Eng., Sogang University, 35 Baekbeom-ro, Mapo-gu, Seoul, Korea)



Terms—Nanoelectromechanical(NEM), NEM memory switch, reliability, stress

I. INTRODUCTION

Reconfigurable logic (RL) circuits such as field-programmable gate arrays (FPGAs) have received much attention due to their advantages: design flexibility and fast development[1-7]. However, conventional RL circuits consisting of CMOS routing blocks (RBs) have shown some limitations in terms of chip density, energy efficiency and performance. To overcome these limitations, some alternative routing switches including nanoelectromechanical (NEM) memory switches have been intensively researched to replace CMOS RBs[3-7]. It is feasible because NEM memory switches can be integrated in back-end-of-line (BEOL) metal interconnection layers. Previously, we have successfully proved that CMOS-NEM RL circuits have lower leakage power, signal delay and chip area than conventional CMOS-only RL ones[5-7].

On the other hand, NEM memory switches suffer from reliability problems due to their operating mechanisms. Fig. 1(a) shows the structure of a conventional NEM memory switch, which acts as a one-to-two multiplexer. It consists of two fixed metal electrodes called Selection Line 1 (SL1), 2 (SL2) and a movable cantilever beam attached to the bit line (BL). The data signal path and logic functions are determined by the position of the cantilever beam. In the initial state, the cantilever beam is not stuck to either SL1 or SL2. Thus, the data signal is not transmitted. Then, the positive or negative voltage ($V_{SL1}$ or $V_{SL2}$) is applied to either SL1 or SL2. It makes the cantilever beam attach to either SL1 or SL2, which means data signal is transmitted. For nonvolatile switching, generally, the contact area between the cantilever beam and SLs is designed to be large[5]. However, large contact area makes stress more concentrated around the anchor. It means that the movable beam becomes weaker than as the number of switching cycle increases, which is problematic in terms of reliability[7,8]. Thus, for reliability improvement, the maximum stress around the beam anchor should be alleviated.

Fig. 1. (a) Schematic of conventional NEM memory switch, (b) Schematic of proposed optimized SL NEM memory switch.

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In this manuscript, we propose that the reliability of NEM memory switches can be improved by optimizing the dimension of SL as shown in Fig. 1(b). The validity of the proposed method is verified by finite-element-method (FEM) simulation. Fig. 2 shows the key process steps of NEM memory switches.

Fig. 2. Key process flow of NEM memory switches.

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II. RESULTS AND DISCUSSION

The quasi-static electromechanical behavior of NEM memory switches is simulated by using three-dimensional (3D) FEM simulation[12]. Table 1 and Table 2 summarize the beam design parameters material properties used in this work. $L_{SL}$ varies from 2.5 μm to 30 μm for optimization. For fair comparison, our proposed NEM memory switch has the identical design parameters except for $L_{SL}$. In order to evaluate stress level, von Mises stress analysis is introduced which is commonly used for the evaluation of metal damage[13-16]. In our work, von Mises stress profile analysis is essential to understand the spatial variations of the stress depending on the beam bending degree determined by the applied voltage. Fig. 3(a) and Fig. 3(b) show the beam displacement in the beam width direction ($L_{\Delta}$) as a function of $L_{SL}$ It is observed that less portion of the movable beam becomes in contact with SLs as $L_{SL}$ decreases. It means more stress is concentrated around the anchor in the pull-in state as $L_{SL}$ increases. To clarify it, Fig. 3(c) and Fig. 3(d) show the stress contours over the beam cross-section at the anchor. The stress increases from the middle part of the beam to the edge, which means that beam fracture occurs from the edge to the center reflecting our experimental results.

Table 1. Parameters of simulated NEM memory switches

Material

Copper

Young's modulus (E)

110 GPa

Poisson ratio

0.34

Density

8.3*10-15 kg·μm-3

Thickness of BL & SL (t)

0.5 μm

Initial gap ($g_{0}$)

0.5 μm

Width of beam ($W_{beam}$)

0.5 μm

Length of beam ($L_{beam}$)

30.0 μm

Length of selection lines ($L_{SL}$)

30.0 ~ 2.5 μm

Table 2. Summarized beam material properties[9-11]

Hamaker constant of Cu beam ($A_{Cu}$)

2.84*10-19

Surface roughness between metal line ($D_{rms}$)

1.6 nm

Van der Waals distance ($d_{vdw}$)

1.5 nm

Real and apparent ratio of contact area ($\alpha$)

0.01

Fig. 3. Beam displacement when $L_{SL}$’s are (a) 29.5 μm, (b) 2.5 μm, respectively. Von Mises stress contours at (c) the anchor cross-section when $L_{SL}$’s are (d) 29.5 μm, (e) 2.5 μm.

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A 1D parallel-plate model is introduced to calculate minimal $L_{SL}$ for nonvolatile switching[17]. Fig. 4 shows the relationship between beam restoring force ($F_{r}$) and van der Waals adhesion force ($F_{ad}$) with the variation of $L_{SL}$. Each force component is defined as

Fig. 4. Relationship between $F_{r}$ and $F_{ad}$ with the variation of $L_{SL}$.

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(1)
$F_{r}=\frac{2 E W_{b e a m} t^{3}}{3 L_{b e a m}^{3}} x$

(2)
$F_{a d}=\frac{2 A_{C u} W_{b e a m} \alpha L_{c o n t}}{12 \pi D_{r m s}^{2} d_{v d w}}$

$F_{r}$ is constant because it is determined only by the structure and material of the cantilever beam. On the other hand, $F_{ad}$ is linearly dependent on $L_{contact}$. The value of $L_{SL}$ when $F_{r}$ is equal to $F_{ad}$ corresponds to the minimal $L_{SL}$ for nonvolatile switching. According to our calculation, the minimal $L_{SL}$ for nonvolatile switching is 4.5 μm.

Fig. 5(a) shows the trade-off between the pull-in voltage ($V_{PI}$) and maximum stress ($\sigma_{max}$) as a function of $L_{SL}$. The data was extracted from FEM simulation. It is observed that $V_{PI}$ increases as $L_{SL}$ decreases. It is easily explained by the 1D parallel-plate model where $V_{PI}$ is derived as

Fig. 5. (a) $V_{PI}$ and $\sigma_{max}$ with the variation of $L_{SL}$, (b) Schematic of NEM memory switches when $L_{SL}$’s are (b) 30~17.5 μm, (c) 17.5 μm, (d) 4.5 μm, (e) less than 4.5 μm, respectively.

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(3)
$V_{P I}=\sqrt{\frac{8 k}{27 \varepsilon_{0} A} g_{0}^{3}}$

where $k$ is the beam spring constant, $g_{0}$ is the air gap between the cantilever beam and the SL, $\varepsilon_{0}$ is the vacuum permittivity and $A$ is the area overlapped between the beam and SLs. $A$ is calculated as $L_{SL}$ * t. Thus, $V_{PI}$ increases continuously as $L_{SL}$ decreases. On the other hand, $\sigma_{max}$ is maintained at ~289 MPa as long as $L_{SL}$ ranges between 17.5 μm and 30 μm. It is because even if $L_{SL}$ decreases, beam contact length ($L_{cont}$) is constant until $L_{SL}$ reaches $L_{cont}$. $L_{cont}$ is defined as the length between the beam tip and the position where the beam displacement is $g_{0}$. Beam noncontact length ($L_{V}$) is defined as $L_{beam}$ - $L_{cont}$. On the contrary, if $L_{SL}$ decreases from 17.5 μm to 4.5 μm, $\sigma_{max}$ becomes steadily lower down to 123.2 MPa maintaining nonvolatile property. In this region, because both $L_{cont}$ is equal to $L_{SL}$, the decrease of $L_{SL}$ makes $V_{PI}$ larger but $\sigma_{max}$ smaller. Finally, if $L_{SL}$ becomes smaller than 4.5 μm, NEM memory switches fail to operate losing nonvolatile property. Fig. 5(a) shows a good example of $L_{SL}$ optimization If 20-% increase of $V_{PI}$ is allowed, $\sigma_{max}$ can be made > 40-% lower when $L_{SL}$ is 7.5 μm.

III. CONCLUSIONS

In this paper, the $L_{SL}$ of NEM memory switches is optimized by FEM simulation considering mechanical reliability and operating voltage. According to the simulation results, as $L_{SL}$ decreases, $V_{PI}$ increases while $\sigma _{max}$ concentrated at the anchor of a movable beam decreases. It is found that the selection of optimized $L_{SL}$ is helpful to make NEM memory switches more reliable with tolerable $V_{PI}$ increase.

ACKNOWLEDGMENTS

This work was supported in part by Samsung Electronics, by the NRF of Korea funded by the MSIT under Grant NRF-2018R1A2A2A05019651 (Mid-Career Researcher Program), NRF-2015M3A7B7046617 (Fundamental Technology Program), NRF-2016M3A7 B4909668 (Nano-Material Technology Development Program), in part by the IITP funded by the MSIT under Grant IITP-2018-0-01421 (Information Technology Research Center Program), and in part by the MOTIE/KSRC under Grant 10080575 (Future Semiconductor Device Technology Development Program).

REFERENCES

1 
Tang X., Gaillardon P. E., Micheli G. D., Dec. 2014, A high–performance low-power near-Vt RRAM-based FPGA, Proc. International Conference Field-Programmable Technology(FPT), pp. 207-214DOI
2 
Hu C., Dec. 1992, Interconnect devices for field programmable gate array, Proc. International Electron Devices Meeting (IEDM), pp. 207-214DOI
3 
Zhou Y., Thekkel S., Bhunia S., Aug. 2007, Low power FPGA design using hybrid CMOS-NEMS approach, Proc. 2007 International Symposium on Low Power Electronics and Design(ISLPED), pp. 14-19DOI
4 
Dong C., Chen C., Mitra S., Chen D., Jun. 2011, Architecture and performance evaluation of 3D CMOS-NEM FPGA, Proc. 13th The System Level Interconnect Prediction Workshop (SLIP), pp. 1-8Google Search
5 
Kim Y. J., Choi W. Y., Feb. 2015, Nonvolatile nanoelectromechanical memory switches for low-power and high-speed field-programmable gate arrays, IEEE Transactions on Electron Devices, Vol. 62, No. 2, pp. 673-679DOI
6 
Choi W. Y., Kim Y. J., Sep. 2015, Three-Dimensional integration 65-nm CMOS-Nanoelectromechanical hybrid reconfifurable circuits, IEEE Electron Device Letters, Vol. 36, No. 9, pp. 887-889Google Search
7 
Kwon H. S., Kim S. K., Choi W. Y., Sep. 2017, Monolithic Threee-Dimensional 65-nm CMOS-Nanoelectromechanical Reconfigurable Logic for Sub-1.2-V Operation, IEEE Electron Device Letters, Vol. 38, No. 9, pp. 1317-1320DOI
8 
Jo H. C., Choi W. Y., Jun. 2018, Encapsulation of NEM Memory Switches for Monolithic Three-Dimensional(M3D) CMOS-NEM Hybrid Circuits, Micromachines, Vol. 9, No. 7DOI
9 
Leite F. L., Bueno C. C., Da Roz A. L., Ziemath E. C., Oliveria O. N., Oct. 2012, Theoretical models for surfaces and adhesion and their measurement using atomic force microscopy, International Jounal of Molecular sciences, Vol. 13, No. 10, pp. 12773-12856DOI
10 
Xu J. Q., Chen L. Y., Choi H., Li X. C., May. 2012, Theorietical study and pathways for nanoparticle capture during solidification of metal melt, Jounal of Physics: Condensed Matter, Vol. 24, No. 25, pp. 255304-255309DOI
11 
Yaung J., Hutin L., Jeon J., Liu T. J. K., Feb. 2014, Adhesive force characterization for MEM logic relays with sub-micron contacting regions, Jounal of Microelectromechancial System, Vol. 23, No. 1, pp. 198-203DOI
12 
ANSYS , 2009, Structural Analysis Guide, ANSYS.inc, Canonos-burgGoogle Search
13 
Beer F., 2002, Mechanics of Materials, 2nded. McGraw Hill, Newyork, NY, USAGoogle Search
14 
Young W. C., Budynas R. G., 2002, Roak’s formulas for stress and strain, 7thed. McGraw Hill, NY, USAGoogle Search
15 
Kim D. H., Kim M. W., Jeon J. W., Lim K. S., Yoon J. B., Oct. 2010, Mechanical reliability of a digital micromirror with integrated cantilevers, J. Microelectromechanical Syst., Vol. 19, No. 5, pp. 1197-1206DOI
16 
Boldeju G., Vasilache D., Mogar V., Stefanescu A., Ciuprina G., Oct. 2015, Study of the von Mises stress in RF-MEMS switch anchors, Proc. 2015 International Semiconductor Conference (CAS), pp. 219-222DOI
17 
Rebeiz G. M., 2003, RF MEMS: Theory, Design, and Technology, Hoboken, NJ, USA, WileyGoogle Search

Author

Hyun Chan Jo
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received the B.S. degree in Advanced Materials Engi-neering from Kyonggi University, Suwon, South Korea, in 2017, where he is currently pursing the M.S. degree in the Department of Elec-tronic Engineering, Sogang Univer-sity, Seoul, South Korea.

His current research interests include nanoelectromechanical (NEM) relays/memory cell.

Min Hee Kang
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received the B. S. degree in 2018 from Sejong Univer-sity, Seoul, South Korea.

She is currently working toward the M. S. degree in the Department of Elec-tronic Engineering, Sogang Univer-sity, Seoul, South Korea.

Her current research interests include nanoelectromechanical (NEM) relays/memory cell.

Woo Young Choi
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received the B.S., M.S. and Ph. D. degrees in the School of Electrical Engineering from Seoul National University, Seoul, Korea in 2000, 2002 and 2006, respectively.

From 2006 to 2008, he was with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, USA as a post-doctor.

Since 2008, he has been a member of the faculty of Sogang University (Seoul, Korea), where he is currently a Professor with the Department of Electronic Engineering.

His current research interests include fabrication, modeling, characterization and measurement of CMOS/novel semiconductor and memory devices.