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1. (Department of Electronic Engineering, Myongji University, Yongin-si, Gyeonggi-do 17058, Korea)
2. (Department of IT Convergence Engineering, Gachon University, Seongnam-si, Gyeonggi-do 13120, Korea)

1T DRAM, middle partial insulation, gate-induced drain leakage(GIDL), TCAD

## I. INTRODUCTION

The conventional dynamic random-access memory (DRAM) cells consisting of one transistor and one capacitor require complicated device structure for obtaining the sufficient storage capacitances[1,2]. This leads to complexity in process architecture and makes it very hard to secure enough room for transistor scaling. For these reasons, capacitorless one-transistor (1T) DRAM is regarded as the breakthrough for the next-generation DRAM technology owing to simple device structure and process integration[3-5]. Many researchers have investigated 1T DRAM devices based on the silicon-on-insulator (SOI) platform[4-9]. However, in a conventional SOI 1T DRAM device, program window tends to be narrow due to recombination of carriers and junction leakages. A middle partial insulation (MPI) structure can be employed in the 1T DRAM device for improvement of retention characteristics. In the MPI 1T DRAM cell, the neutral region for hold accumulation is increased in volume and the recombination is prohibited near the source junction[10]. Moreover, MPI has an effect of suppressing the leakage current by band-to-band tunneling and enhancing the drive current[11,12]. However, previous 1T DRAM devices with the MPI structures have mostly employed impact ionization for program operation. This induces several problems such as high power consumption and lattice defect generation near the drain junction. Program by gate-induced drain leakage (GIDL) can reduce the destructive carrier injections and consequently suppress oxide degradation and power loss in the 1T DRAM operation[13].

In this work, we provide insight and design guidelines of double-gate MPI 1T DRAM device. Double-gate structure has been applied to improve gate controllability and strengthen the immunity against the short-channel effects in the MOSFET operation[14,15]. In order to optimally design the 1T DRAM cell, various parameters including channel width, barrier length, and bias voltage have been controlled and characterized through a technology computer-aided design (TCAD) tool, Sentaurus by Synopsys.

## II. DEVICE STRUCTURE AND SIMULATION APPROACHES

The proposed 1T DRAM device with the MPI and double-gate structures is schematically shown in Fig. 1. The doping concentrations in the p-type channel and n-type source/drain junctions are 1 × 1018 cm-3 and 1 × 1020 cm-3, respectively. The oxide layer near the source junction blocks the leakage current from the body.

Fig. 1. Schematic of the double-gate MPI 1T DRAM.

The proposed 1T DRAM has independent double gates and the read gate reads the memory states and the control gate governs the program and erase operations. Si channel length ($L_{ch}$), overlap length ($L_{overlap}$), barrier oxide thickness ($T_{barrier}$), and barrier oxide height ($H_{barrier}$) are 190 nm, 10 nm, 5 nm, and 14 nm, respectively. A number of physical models including band-to-band tunneling, carrier mobility models, Auger recombination model, Shockley-Read-Hall (SRH) recombination model have been applied simultaneously in cooperation for more accurate simulation results.

## III. RESULTS AND DISCUSSION

Fig. 2(a) shows $I_{D}$-$V_{GS}$ characteristic curves of the proposed 1T DRAM devices with different set of simulation models. The leakage current by GIDL ($I_{GIDL}$) in the presence of the band-to-band tunneling (BTBT) model is extracted at $V_{GS}$ = -0.5 V. By utilizing the GIDL for program operation, mechanically non-destructive and electrically low-power operation can be schemed compared with the impact ionization mechanism[16]. Fig. 2(b) shows the spatial distribution of BTBT generation rates over the device structure. Fig. 3 shows read gate voltage ($V_{RGS}$), control gate voltage ($_{VCGS}$), and drain voltage ($V_{DS}$) waveforms to validate the memory operations. All the operating times for program, hold, read, and erase operations are 10 ns and all the operating voltages do not exceed 1.6 V, which reveals the high-speed and low-voltage operation capabilities of the proposed 1T DRAM cell.

Fig. 2. Current characteristics (a) Validation of the BTBT model by GIDL current, (b) BTBT generation rates over the device.

Fig. 3. Full memory operation scheme for one cycle.

Fig. 4 shows the drain current over three cyclic memory operations and each cycle consists of program, hold, read 1, hold, erase, hold, read 0, and hold operations in sequence. The current ratio between read 1 and read 0 is approximately 3 × 106 and does not vary with cycles. IN case of hold operation, there is no power consumption since no additional voltage is applied to hold the carriers.

Fig. 4. Transient simulation of ID over three cycles.

Table 1 summarizes the possible operating conditions and the energy required for individual operations. The maximum value of $I_{D}$ takes place at the program operation as shown in Fig. 4. Therefore, it can be seen that the energy consumption of the proposed device is determined mainly by the program operation. Comparing with the previous work where the program operation is conducted by impact ionization, the power consumption is drastically reduced about 106 times[17]. The above simulation results confirm that the proposed device is highly suitable to low-power 1T DRAM applications.

Table 1. Summary of operation bias schemes

 $V_{RGS}$ [V] $V_{CGS}$ [V] $V_{DS}$ [V] Time [ns] Energy [J] Program 0 -0.5 1.6 10 1.94×10-10 Erase 0.5 0.5 -0.3 10 8.62×10-12 Read 1 0.5 0 0.2 10 8.30×10-13 Read 0 0.5 0 0.2 10 3.08×10-19 Hold 0 0 0 10 0

In order to optimize the performances of the proposed 1T DRAM device, barrier length and voltage conditions have been controlled. Junction leakage and recombination near the source junction can be reduced by increasing the barrier length[11,12]. Therefore, the longer the barrier length, the better the transient characteristics including retention time and sensing margin are expected.

Fig. 5(a) depicts the retention time depending on barrier length. Since the barrier inhibits recombination in the source and body regions, the longer the barrier length, the longer the retention time is obtained. However, Fig. 5(b) shows that the hole concentration in the channel region is not dependent on barrier length. Since GLDI is employed as the program operation mechanism and the holes are removed from the drain area, the barrier does not affect the program and erase operations. Therefore, only the retention characteristics are influenced by the barrier length. In this work, a double-gate structure is applied to operate the 1T DRAM and the distance between two gates has a significant influence on electrical characteristics[14]. Shorter distance between double gates enhances the gate controllability over the channel. Thus, dependences of retention time and physical quantities on channel width have been investigated to study the effects on 1T DRAM.

Fig. 5. Effects of barrier length on memory characteristics (a) Retention time, (b) Hold concentration in the channel region after program and erase operations as a function of barrier length.

Fig. 6(a) shows the retention time vs. channel width. Here, the channel can be termed as channel thickness, more specifically. As the channel width increases, the excess hole generation by GIDL is reduced[18]. As the channel width increases, the average channel charge (net value) shows a monotonic decrease as depicted in Fig. 6(b) but the decrease is not a significant amount. Contrary to the retention characteristics, the current ratio is improved as the channel width increases as shown in Fig. 6(c). Over the erase operation, holes are removed to the drain junction by the forward bias on pn junction between channel and drain. Decreasing the channel width leads to reduction in electric field, which determines the erase efficiency and reduces the current ratio eventually. Fig. 6(d) shows the vertical electric field at the drain side under erase operation condition at different channel widths. According to Fig. 6(d), the vertical field increases as the channel width increases. Increase of vertical electrical field near the drain edge induces low hole concentration at state 0. Therefore, the read current at state 0 decreases and the current ratio increases as channel width increases. From the results in Fig. 6(a) and Fig. 6(c), channel width can be optimized for both current ratio and retention time.

Fig. 6. Dependence of memory characteristics and physical quantities on channel width (a) Retention time vs. channel width, (b) Average hole concentration in the channel vs. channel width (inset: cutline over the region where the results are obtained), (c) Read current ratio vs. channel width, (d) Vertical electric field vs. channel width ($W_{ch}$ = 15 and 55 nm) (inset: cutline over the region where the results are obtained).

Fig. 7(a) shows the read 1 current and current ratio as a function of program voltage. As $V_{DS}$ increases, more drastic band bending takes place and BTBT probability gets higher. It is revealed that he sensing margin becomes larger as $V_{DS}$ increases and is saturated at $V_{DS}$ = 1.6 V. Therefore, $V_{DS}$ can be kept no higher than 1.6 V for low-voltage operation. Fig. 7(b) demonstrates the optimization conditions for erase bias. As the negative $V_{DS}$ gets larger in magnitude, read 0 current decreases and current ratio increases monotonically. $V_{DS}$ = -0.3 V is a permissible read bias and $V_{DS}$ does not have to go below -0.5 V where the state 0 current and current ratio are saturated, for sufficiently large sensing margin and low-power operation.

Fig. 7. Read current and ratio vs (a) program, (b) erase bias.

## IV. CONCLUSION

In this work, we proposed a double-gate 1T DRAM with MPI structure for enhancements of data retention and low-power operation capabilities, and optimally designed using TCAD device simulation. The proposed 1T DRAM utilizing GIDL program method demonstrates significant reduction in power consumption compared with the previous 1T DRAM device operated by impact ionization. The increase in dielectric layer length between the channel and the source junction improves the retention time of the proposed 1T DRAM device. When it comes to channel width, the retention capability is enhanced while the current ratio is decreased as the channel width decreases. Also, it has been confirmed that there are upper limits in the magnitudes of program and erase voltages considering the read current ratio and sensing margin. The proposed 1T DRAM has the strong potential for next-generation DRAM technology featuring higher integration density with truncation of capacitor, elongated retention time, and low-power operation capability.

### ACKNOWLEDGMENTS

This work was supported by the 2018 research fund of Myongji University in Korea and by the Ministry of Trade, Industry and Energy (MOTIE) and the Korean Semiconductor Research Consortium (KSRC) through the Development of Next-Generation Semiconductor Devices Program (Grant No. 10080513).

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## Author

##### Jong Min Ha

was born in Gumi, Korea, in 1991.

He received the B. S. degree in electronic engineering from Myongji University, Yongin, Korea, in 2017.

He is currently working towards the M. S. degree at the same university.

##### Jae Yoon Lee

received the B. S. degree in electronic engineering from Gachon University, Seongnam, Korea, in 2018, where he is currently pursuing the M. S. degree.

His research interests include 1T DRAM, resistive-switching random-access memory (ReRAM) and its array architecture, and device-circuit co-optimization of emerging memory devices.

He is a Student Member of the Institute of the Electronics and Information Engineering of Korea (IEIE).

##### Myeongseon Kim

received the B. S. degree in electronic enigineering from Mynogji University, Yongin, Korea, in 2018.

She is currently working towards the M. S. degree at the same university.

##### Seongjae Cho

received the B. S. and the Ph.D. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 2004 and 2010, respectively.

He worked as a Postdoctoral Researcher at Seoul National University in 2010 and at Stanford University, CA, USA, from 2010 to 2013.

He is currently working as an Assistant Professor at the Department of Electronic Enigineering and at the Department of IT Convergence Engineering, Gachon University, Seongnam, Korea.

His research interests include nanoscale CMOS devices, emerging memory technologies, optical devices, and CMOS-photonic integrated circuits.

##### Il Hwan Cho

received the B. S. degree in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2000, and the M. S. and the Ph.D. degrees in electrical engi-neering from Seoul National Univer-sity, Seoul, Korea, in 2002 and 2007, respectively.

He worked as a Postdoctoral Researcher at Seoul National University from 2007 to 2008.

In 2008, he joined the Department of Electronic Engineering at Myongji University, Yongin, Korea, where he is currently a Professor.

His research interests include improvement, characterization, and measurement of memory and nanoscale transistor devices.