I. INTRODUCTION

Amorphous oxide semiconductor thin film transistors (TFTs) have been proposed as the main elements for various large-area electronic devices because of their outstanding characteristics such as high field-effect mobility, low off-current, and low fabrication temperature^[1-4]. Among the various compositions of oxide semiconductors, amorphous indium-gallium-zincoxide (a-IGZO) has been one of the most attractive materials used for the TFT applications^[5]. Meanwhile, nonvolatile memory (NVM) is also an important device element for large-area electronic systems to achieve functionality for both information storage and low-power consumption^[6,7]. Incidentally, the IGZO-based oxide TFTs can also be exploited as promising NVM devices. Thus, the main objective of this study is to provide useful methodologies and device concepts of NVMs for future consumer electronics established on various large-area substrates, such as glass and plastic. In previous work, we have reported the properties of the charge-trap assisted memory TFTs (CTM-TFTs) and demonstrated the excellent nonvolatile memory characteristics using a ZnO charge-trap and IGZO channel layers^[8,9]. However, the proposed CTM-TFTs with conventional single-gate (SG) configurations have major drawbacks; higher program/erase (P/E) voltages are required to guarantee sound memory device operations, such as high on/off ratios and high P/E speeds. The drawbacks are directly related to the fact that the position of the memory window (MW) cannot be easily designed for the SG CTM-TFTs. Notwithstanding, the read-out voltage (V_R) conditions and the transfer characteristics, including the position of the MW, are the most important parameters for optimizing the memory performance of the CTM-TFTs^[9]. As a result, the introduction of a double-gate configuration has the potential to be a powerful solution to resolve the technical limitations of the SG CTM-TFTs.

For the conventional oxide TFTs, DG configurations have been enormously proposed to effectively modulate the threshold voltage (V_TH) and to enhance the current drivability^[10,11]. Moreover, remarkable improvements in channel mobility was also accomplished due to the formation of bulk-accumulation^[12]. Therefore, the DG TFTs exhibited great potentials to further improve the device characteristics of the conventional SG devices ^[13], even though the deposition and patterning process are added to the full fabrication process. Despite of these benefits supported by the DG configuration, there have been few studies on the DG CTM-TFTs using the oxide semiconductors except for Si-channel charge-trap flash memory devices^[14,15].

In this work, we propose and fabricate the DG CTMTFTs using the oxide semiconductors for the charge-trap and active channel layers to realize higher NVM performance even with lower P/E voltages. Especially, the effects of capacitance coupling between the top and bottom gate insulators (GIs) on the memory device characteristics are examined by the thickness variations in GIs. The device performance of the DG CTM-TFTs can be expected to be remarkably improved by effectively controlling the transfer characteristics at given conditions of fixed bottom-gate biases, compared to our previous works^[16,17], especially from the viewpoint of low-voltage operation. Furthermore, we examine main control parameters and appropriate design strategies to optimize the device performance for our proposed DG CTM-TFTs.

II. DEVICE FABRICATION

Fig. 1(a) and Fig. 1(b) show an optical microscopic image and a schematic cross-sectional view of our proposed CTM-TFT with DG configuration employing the oxide semiconductor channel and charge trap layer (CTL). First, indium-tin-oxide (ITO)-coated glass substrate was patterned into the bottom gate (BG) electrodes. Al₂O₃ thin films were then formed at 200 ℃ as bottom gate insulators (BGI) via atomic layer deposition (ALD), where trimethylaluminium [TMA, (CH₃)₃Al] and water vapor (H₂O) were used as the aluminum and oxygen precursors, respectively. The film thicknesses of the BGIs were controlled during the film formation; BGIs of 100 and 50 nm thicknesses were fabricated in order to examine the effect of BGI thickness on memory device operations. 150-nm-thick ITO thin films were deposited by DC sputtering and patterned for the formation of source/drain (S/D) electrodes. Prior to performing the patterning process for the S/D electrodes, a thermal treatment was performed at 250 ℃ in a vacuum to control the film crystallinity and electrical conductivity of the sputtered ITO film. Then, 20-nm-thick IGZO active channel layers were formed using RF magnetron sputtering with a single IGZO (In:Ga:Zn=2:1:2) target at room temperature (RT). Al₂O₃ (5 nm) was formed as the first tunneling layer by ALD at 180 ℃. After the patterning process of the IGZO channel and the first tunneling layers, 5-nm Al₂O₃, 30-nm ZnO, and 3-nm Al₂O₃ layers were successively deposited by ALD at 200, 100, and 150 ℃ as the second tunneling, charge-trap, and top-protection layer, respectively. The deposition processes were all performed in the same chamber without removing a vacuum in order to ensure higher qualities of the interfaces between the layers. The use of a ZnO CTL was one of the main features for our proposed DG CTM-TFTs. The double-layered tunneling layer and top-protection layers were strategically designed to prevent damage induced to the IGZO channel from wet-etching during the CTL patterning process and to protect the surface of the ZnO CTL during the lithography process, respectively^[16]. After the trilayered structure was patterned using one-step wetetching process with diluted hydrofluoric acid (HF:H2O=1:200), 50-nm-thick Al₂O₃ thin films were formed as top gate insulators (TGI) by ALD at 150 ℃. The contact holes to electrically connect the S/D electrodes with probing pads were formed by opening through the blocking oxide with phosphoric acid at 120 ℃. Finally, a 150-nm-thick ITO top gate (TG) electrode was deposited using DC sputtering at RT and patterned via a lift-off process to minimize the chemical damage to the layers underneath. For convenience, the DG CTMTFTs using the BGIs with thicknesses of 100 and 50 nm were termed as Dev. 1 and Dev. 2, respectively.

Fig. 1. (a) Optical microscopic image, (b) schematic crosssectional view of the fabricated CTM-TFT with DG configuration.

Device characteristics were evaluated using a semiconductor parameter analyzer (Keithley 4200) and a pulse generator (HP 8110A) in a dark box at RT. At SG mode operations, only three terminals were used, correspond to the source, drain, and TG electrodes. The BG was oated when the electrical characteristics of the TG device were measured. On the other hand, for the DG mode operations, four terminals corresponding to source, drain, TG, and BG electrodes were used, in which both gate electrodes (TG and BG) were connected, and the transfer characteristics were measured with DG configuration^[18]. The BG electrode was also utilized for introducing the fixed bias in order to examine the effect of fixed voltage at BG ($V_{BG}$) on the device characteristics. In the evaluations of the memory operations, P/E voltage pulses were applied to the TG ($V_{TG}$), and the drain voltage ($V_{DS}$) was set as 0.1 V. The read-out operations were measured at a $V_{TG}$ of 0 V with a given amplitude of the fixed $V_{BG}$. For our proposed CTM-TFTs, the memory off- and on-states could be stored with the program and erase operations, respectively.

III. MEMORY DEVICE CHARACTERIZATION

Fig. 2(a) shows the transfer characteristics for Dev. 1 at a $V_{DS}$ of 0.1 V and compares them with those obtained after the repeated P/E operations using pulse signals, in which ±20-V pulses with 1-s duration were repeatedly applied with 10³ cycles. For the DG mode operation, the gate voltage was applied to both electrodes of the TG and BG and was incrementally varied from -20 V to 20 V in both the forward and reverse directions. Clear clockwise hysteretic behavior in the transfer curves were observed because the turn-on voltage ($V_{on}$) was shifted due to charge-trap and detrap operations. The MW, which was defined as the width of the hysteresis in the transfer curve, was 13.8 V. The hysteresis in $I_{D}$-$V_{GS}$ curve can also originated from the undesirable charge-injection into the interface trap states as well as the designed chargetrap/de-trap events during the P/E operations. However, the obtained transfer characteristics and the MW supported by the charge-trap mechanism were already found to be very stable in our previous publications ^[8,16,23]. The width and location of the MW are important device parameters for CTM-TFTs because they determine operating conditions, such as the P/E and readout voltages. The MW obtained for Dev. 1 was located near at 0 V as the center in x-axis. It is highly desirable for the CTM-TFTs to read-out the programmed memory states close to 0 V for the purpose of symmetrically choosing the P/E voltages and effectively avoiding the additional field effects during the read-out operations. Furthermore, the MW and transfer characteristics did not show any remarkable changes even after the repetition of the P/E operations, which suggests that the evaluated device does not experience undesirable variations in basic memory characteristics during P/E operations. Otherwise, numerical analyses for the programmed current values obtained for the P/E operations could not be guaranteed. Concerning the high-temperature transfer characteristics and retention characteristics of the CTMTFTs with the same gate-stack structure, stable operations were previously confirmed^[19]. The photoresponses of the fabricated CTM-TFTs were also examined at various wavelength of light sources. Even under the light-illumination conditions, the memory device operations including the MW and program speed exhibited good memory characteristics and did not exhibit any specified dependence of wavelength^[20].

Fig. 2(b) shows the P/E characteristic for the same device when the pulse width of the P/E voltages were varied from 1 s to 1 μs. For this experiment, the amplitude of P/E voltage and $V_{DS}$ were set as ± 20 V and 0.1 V, respectively; the programed currents were readout at 0 V; the memory on/off ratio was defined as the current ratio between the on- and off-programmed states at the given read-out conditions. While measuring the memory operations, the BG electrode was grounded. Since the on- and off-programmed currents provide meaningful information on nonvolatile memory behavior of the fabricated CTM-TFTs, the P/E characteristics were evaluated using the memory on/off ratio rather than shifts in the $V_{TH}$. In other words, (1) the absolute levels of the on- and off-programmed currents and their variations with respect to changes in the P/E and read-out conditions practically reflect the program performance of the transistor-type memory device, and (2) the current ratio between the programed states at given read-out conditions can be helpful in creating a practical design for the memory applications. In practical applications, the modulations in channel conductance can be important to operate given circuits and/or systems embedded with the proposed CTM-TFTs, even though it is the case that the $V_{TH}$ is more sensitive to the changes in the number of trapped charges. The maximum memory on/off ratio was obtained as 5.8×10⁶ when the P/E pulse duration was 1 s. The $I_{D}$ value (3.6×10^-7 A) of the on-state programmed with a 1-s-duration and +20-V-amplitude pulse was obtained to be almost the same as the $I_{D}$ value (6.1×10^-7 A) of the on-state at a $V_{R}$ of 0 V from the transfer characteristics obtained in Fig. 2(a). Even though the memory on/off ratio showed a tendency to decrease as the P/E voltage pulse duration decreased, a memory on/off ratio as high as 1.5×10⁵ was measured at a pulse duration of 10 μs. Furthermore, another noteworthy characteristic was observed in the device; the nonvolatile memory operations could be confirmed to be available even at a pulse duration of 1 μs. As shown in Fig. 2(a), we can say that the variations in the programmed currents accurately reflected the program speed characteristics of the evaluated memory TFT, considering that there were no remarkable variations between the initial and post-P/E transfer curves. Thus, the fabricated DG CTM-TFTs were confirmed operate well at high speeds as nonvolatile memory elements. The P/E speed is closely related to the charge-trap and detrap efficiency for the CTM-TFTs. As illustrated in Fig. 2(b), the off-state was more vulnerable to the erase operations with a shorter pulse duration compared to the on-state. The P/E characteristics could be remarkably varied with the voltage condition of read-out operations ($V_{R}$) and the location of the MW. Read-out operations performed at a $V_{R}$ that deviated from 0 V could deteriorate the P/E performance, especially for one of the memory states (on- or off-states), due to undesirable field applications into the gate stack. From these viewpoints, the DG configuration has beneficial effects for accurately controlling the memory performance of the CTM-TFTs because the back-channel potential and the MW location could be strategically controlled by adjusting the suitable $V_{BG}$.

Fig. 2. (a) Drain current – gate voltage transfer characteristics and gate leakage currents of Dev. 1 at the DG mode operation, in which the gate voltage was simultaneously applied to TG and BG. The measurements were repeated after the number of P/E operations, (b) Variations in programmed currents during the P/E operations as a function of P/E voltage pulse width.

The ability to have control over the $V_{TH}$ is one of the most important features expected for the DG TFTs. Fig. 3(a) and Fig. 3(b) show the variations in the transfer characteristics for each device when the fixed $V_{BG}$ was varied to 5, 0, -5, -10, and -15 V. The $V_{GS}$ was swept in the same ranges from -20 to 20 V for each measurement to demonstrate the $V_{TH}$ controllability. As expected, when the negative and positive biases were fixed at the BGs, the values of $V_{TH}$ for both devices were clearly modulated in positive and negative directions in the $V_{GS}$ axis, respectively. Even though the values of $V_{on}$ (and $V_{TH}$) and the location of the MW can also be controlled via the electronic nature of the IGZO active channel, the application of a fixed $V_{BG}$ can be effectively exploited as one of the benefits of the DG configuration, because the location and width of the MW can be intrinsically determined by the charge-trap/detrap events during the memory operations. These $V_{TH}$ modulations can be generally explained by the accumulation-depletion transitions within the IGZO active channels, which were controlled by the amplitudes and polarities of the $V_{BG}$ biases^[3,10,12]. The channel layer could be easily formed using a smaller $V_{TG}$ with the application of a positive $V_{BG}$; hence, the TFT was turned on at a lower $V_{TH}$. On the other hand, for the application of a negative $V_{BG}$, a larger $V_{TG}$ was required to form the conductive channel, owing to the formation of a depletion layer near the BGI interface region. In the negative $V_{BG}$ case, the TFT was eventually turned on, but at a higher $V_{TH}$. For further clarification of the $V_{TH}$ characteristics, the effect of different BGI thicknesses were examined. When the BGI thickness was reduced from 100 (Dev. 1) to 50 nm (Dev. 2), the field effect induced by the $V_{BG}$ is expected to result in increased sensitivity. Therefore, a decrease in the BGI thickness should be able to improve the $V_{TH}$ tunability. However, current drivability is limited at strong negative $V_{BG}$ conditions due to the formation of full-depletion in the active channel, as illustrated in Fig. 3(b). The $V_{TH}$ tunability can be explained by the capacitance coupling ratio of $C_{BGI}$/$C_{TGI}$, in which $C_{BGI}$ and $C_{TGI}$ correspond to the capacitance per unit area of the BGI and TGI, respectively. Assuming that the $C_{dep}$, or the capacitance per unit area of depletion layer within the active channel, is much larger than the $C_{BGI}$ and $C_{TGI}$, the $V_{TH}$ of the TG device can be determined as follows:

Fig. 3. Sets of transfer characteristics of the (a) Dev. 1, (b) Dev. 2 when the fixed $V_{BG}$ was controlled to 5, 0, -5, -10, and -15 V, respectively.

where $V_{TT0}$ and $V_{BT0}$ correspond to the threshold voltages when the top and bottom gates were employed for the SG mode operations, respectively^[21]. The threshold voltage of the device with TG configuration at a fixed $V_{BG}$ bias is directly related to the capacitance coupling ratio of $C_{BGI}$/$C_{TGI}$. Thus, the $V_{TH}$ tunability of Dev. 2 should be enhanced compared to that of Dev. 1. Consequently, the coupling ratio of $C_{BGI}$/$C_{TGI}$ should be carefully designed such that a compromise is reached for the characteristics of $V_{TH}$ tunability and current drivability in the DG CTM-TFTs. The ability to control the $V_{TH}$ with DG configurations in CTM-TFTs can enhance the program performance by easily allowing suitable value of $V_{R}$ for the DG CTM-TFT to be set, which is one of the most important benefits supported by the DG configuration for CTM-TFT applications over the conventional SG configuration^[22].

The effects of the fixed $V_{BG}$ on the memory operations were examined in detail for the fabricated DG CTMTFTs. Fig. 4(a) shows the P/E operation speeds for the fabricated devices as a function of the applied $V_{BG}$, where the P/E speed was defined as the voltage pulse width when the memory on/off ratio exceeded 3-ordersof magnitude for conveniences in evaluating the effects of applied fixed $V_{BG}$ on the P/E characteristics of the proposed CTM-TFTs with DG configuration. The applied voltages for the P/E operations were set at ± 20 V. The P/E speed was found to be remarkably enhanced as the $V_{BG}$ decreased. When the $V_{BG}$ was set at -3 V, the P/E speeds for Dev. 1 and Dev. 2 were estimated to be approximately 10 and 1 μs, respectively. However, the P/E speeds for both devices slowed down to longer than 1 s when the $V_{BG}$ was set at 3 V. Generally speaking, the $V_{R}$ should be changed depending on the threshold voltage and the location of MW. Thus, the P/E speeds can be mainly controlled by the charge-trap and detrap efficiencies for the CTM-TFTs fabricated with given gate-stack structures. Thus, it can be the case that the P/E speeds are not directly related to the $V_{R}$ conditions. However, the memory P/E operations of the proposed CTM-TFTs are also influenced by the P/E and $V_{BG}$ conditions. Furthermore, the read-out operations can desirable to be performed at a $V_{GS}$ of 0 V from the viewpoints of the removal of unexpected internal field as well as simple set-up’s for memory operations. Therefore, the width of MW and its location are eventually important to determine and improve the P/E speeds of the proposed CTM-TFTs. In other words, when the fixed $V_{BG}$ with a suitable bias was not introduced, the on- and off-memory states of the CTM-TFTs could not be readout at the same $V_{R}$. As discussed in Fig. 3, the $V_{TH}$ tunability is a strong benefit supported by the DG configuration. Consequently, the DG configuration can be a simple but effective method to solve the problem of the CTM-TFTs with SG configuration. Thus, for the memory array composed of DG CTM-TFTs, we have much more degree of freedom in designing the memory array operation scheme, because the MW locations can also be controlled for the array structure.

Fig. 4(b) shows the variations in the memory on/off ratios for Dev. 1 and Dev. 2 when the widths of P/E voltages were fixed at 100 μs. The P/E voltages were set at ± 20 V and the $V_{BG}$ was varied between -3, 0, and 3 V. The memory on/off ratio obtained while using a $V_{BG}$ of - 3 V was higher than 5-orders-of magnitude for both devices; however, the devices did not exhibit nonvolatile memory operations at a $V_{BG}$ of 3 V. These results suggest that the fixed $V_{BG}$ bias plays critical roles in guaranteeing the high performance of the memory characteristics for the fabricated DG CTM-TFT devices. Similarly, the optimum $V_{BG}$ conditions were examined to maximize the memory on/off ratio for Dev. 1 and Dev. 2, as shown in Fig. 4(c) and Fig. 4(d), respectively. For the device using the BGI with a thickness of 100 nm, the P/E operations could be completely performed at a $V_{BG}$ of -3 V, and a maximum memory on/off ratio could be obtained due to appropriate control in the locations of the MWs and the read-out condition at a $V_{R}$ of 0 V. On the other hand, when the $V_{BG}$ decreased to -10 V, the on-currents obtained by erase operations were observed to sharply decrease, owing to the excessive formation of a depletion region within the active channel. For the device using a BGI with a thickness of 50 nm, the maximum on/off ratio could also be obtained at a $V_{BG}$ of -3 V. However, we found that the erase operation could not be performed, even when using a $V_{BG}$ of -5 V. In other words, our results suggest that the effects of the fixed $V_{BG}$ could be improved by reducing the BGI thickness. However, the memory device performance improvements, including higher memory on/off ratios and P/E speed, were not impressive for the device with a BGI thickness of 50 nm. Consequently, in order to effectively benefit from effects of using a fixed $V_{BG}$ for the DG CTM-TFTs, the BGI thickness must be carefully optimized, considering the fact that a significant decrease in the BGI thickness can deplete the active channel, even when using a smaller $V_{BG}$ due to higher field sensitivity.

Fig. 4. (a) Variations in the P/E speed, (b) the memory on/off ratio for Dev. 1 and Dev. 2 as a function of fixed $V_{BG}$ bias. The P/E voltages were set as ±20 V. For comparisons, the drain currents programmed by P/E operations were examined for the (c) Dev. 1, (d) Dev. 2, respectively, in which P/E voltage pulse width was fixed at 100 μs.

For the nonvolatile memory operations using our proposed DG CTM-TFTs, it was important to investigate the feasibility of reducing the P/E voltages for the lowvoltage operations by appropriately choosing the $V_{BG}$ bias conditions. Changes in the memory on/off ratios for Dev. 1 and Dev. 2 as a function of P/E voltage when the fixed $V_{BG}$ was varied to 3, 0, and -3 V are shown in Fig. 5(a) and Fig. 5(b), respectively. The duration of the voltage pulses for the P/E operations were set at 1 s. When the $V_{BG}$ bias was fixed at 3 V, the obtained memory on/off ratios were lower than 10 and significantly decreased with decreasing the P/E voltages. Furthermore, even when the $V_{BG}$ bias was fixed at 0 V, the memory on/off ratio obtained at a P/E voltage of ± 20 V drastically decreased to be only 100 for both devices as the P/E voltage decreased. On the other hand, it was noteworthy that the memory on/off ratio of Dev. 1 was observed to be as high as 10⁶, even with the P/E voltage of ±15 V at a fixed $V_{BG}$ bias of -3 V (Fig. 5(a)). For Dev. 2, an on/off ratio higher than 10⁴ was obtained using the same conditions (Fig. 5(b)). These results clearly suggest that the P/E voltages could be remarkably reduced for the proposed DG CTM-TFTs by selecting suitable fixed $V_{BG}$ bias conditions. For both devices, the memory on/off ratios were improved by decreasing the $V_{BG}$ bias from 3 to -3 V. It is interesting to note that even with a P/E voltage of ±15 V, the memory on/off ratio of Dev. 1 could be pushed as high as 3.1×10⁶. Similarly, the memory on/off ratio of Dev. 1 also did not experience any notable degradation, while the on/off ratio of Dev. 2 remarkably decreased by decreasing the P/E voltage. Consequently, the BGI thickness was also found to be a critical design parameter from the viewpoint of lowvoltage operation. Dev. 1, using the BGI with a thickness of 100 nm, was evaluated to be more effective at reducing the P/E voltages compared to Dev. 2 with a BGI thickness of 50 nm. As discussed in Fig. 4, while a $V_{BG}$ of -3 V was at an optimum condition to maximize the on/off ratio for Dev. 1, the memory off-state for Dev. 2 could not be fully programmed at a $V_{BG}$ of -3 V due to higher field sensitivity. These effects were more remarkably reflected through changes in the device characteristics (e.g. by decreasing the P/E voltages). Thus, the reduction margin in P/E voltages for Dev. 2 with a thinner BGI thickness became smaller than those for Dev. 1 with a thicker BGI. These observations suggest that our proposed DG CTM-TFTs could be operated using lower P/E voltages by adjusting the optimum operation conditions in order to effectively reduce the power consumption.

Fig. 5. Variations in the memory on/off ratio for the (a) Dev. 1, (b) Dev. 2 as a function of P/E voltages when the fixed $V_{BG}$ was modulated to -3, 0, and 3 V, respectively. The P/E voltage pulse width was fixed at 1 s.

The memory retention characteristics were evaluated for the DG CTM-TFTs (not shown here). The fixed $V_{BG}$ bias was simultaneously applied during the P/E and readout operations; however, during the retention period, the fixed $V_{BG}$ was removed from the gate terminal. The memory retention time, especially for the off-current, was improved when the negative fixed $V_{BG}$ bias was introduced. Contrarily, when the positive fixed $V_{BG}$ was applied, the memory on/off ratio drastically decreased due to the increase in off-current with a lapse of retention time. These results provide evidence that the retention characteristics of the DG CTM-TFTs could be sensitive response to the fixed $V_{BG}$ bias conditions. For example, we observed that the memory off-current state deteriorated in time, even at a small positive $V_{BG}$ value. As discussed previously, during the program and readout operations, the location of the MW is important, as it promotes stable off-current levels. Therefore, the offcurrent programmed at a negative fixed $V_{BG}$ (-3 V in this work) also exhibited more reliable behavior, with a lapse of retention time, than the off-current programmed at a positive fixed $V_{BG}$. Furthermore, the memory off-current programmed at a positive fixed $V_{BG}$ might show the increasing trend with a lapse of retention time. Ideally, the trapped charge should be stably located within the CTL and the off-programmed current should keep its value with time evolution. However, the trapped charge can be gradually de-trapped from the CTL and/or overlap regions of S/D and active layers and then the $V_{TH}$ is gradually returned because of unstable program event at a positive fixed $V_{BG}$. Intrinsically, the retention performance is to be determined by the charge-trap efficiency into the ZnO CTL. On the other hand, for the DG CTM-TFTs, the retention time can be improved by using strategies supported by the device design: (1) the optimum read-out condition (around at 0 V) can be determined by tuning the location of the MW for the DG configuration, and (2) the fourth terminal of the DG configuration provides a meaningful degree of freedom for memory operations. In other words, the effect of fixed $V_{BG}$ bias can be controlled by appropriately designing the capacitance coupling ratio between the bottom and top gate insulators, which was designed by varying the BGI thickness in this work. Consequently, the memory retention time can be remarkably influenced by suitably controlling the fixed $V_{BG}$ condition when using the DG configuration. Although the test time was only long enough for a comparison between the two test conditions, the memory retention time of the proposed DG CTM-TFTs could be expected to be far longer than 10³ s and to satisfy the given requirements for NVM operations.

Finally, our characterization experiments allowed us to determine the device operation mechanisms for our proposed DG CTM-TFTs. When the $V_{BG}$ is grounded, the device operations were found to be mainly influenced by the $V_{TG}$, similar to SG configuration. The basic operations of the CTM-TFTs with SG configuration was extensively discussed in our previous publication^[23]. For the program operation of off- states, the positive $V_{TG}$ is introduced, and hence, the electrons accumulated within the IGZO channel are injected and trapped into the ZnO CTL. Then the $V_{TH}$ is shifted to the positive direction. Although the charge trap/de-trap events for the electrons are supposed to be dominated by the Fowler-Nordheim (F-N) tunneling, the areal geometry effects of a ZnO CTL should also be considered as one of the process-dependent parameters influencing on the device characteristics of the CTM-TFTs^[24]. The device with a larger overlapped region between the CTL and active channel exhibited a larger MW and faster program speed, which could be explained by modulations in the number of trap sites within the ZnO CTL and the field concentration at the edge area of the overlapped region.

On the other hand, for the CTM-TFTs with DG configuration, when a negative $V_{BG}$ is introduced, electrons in the active layer accumulate at the interface near the tunneling layer due to the formation of depletion region at the interface between the IGZO and BGI. Thus, the MW can be shifted at an application of appropriate fixed $V_{BG}$. This relationship explains that more stable P/E operations could be obtained with the application of a larger negative $V_{BG}$, as discussed in Fig. 3 and Fig. 4. However, when an excessively large $V_{BG}$ is applied, the IGZO channel is fully depleted; therefore, the P/E characteristics deteriorate. In a similar fashion, when a positive $V_{BG}$ is introduced, the number of electrons, which can be trapped into the CTL via F-N tunneling, significantly decrease near the tunneling layer due to the electron accumulation at the interface between the IGZO and BGI. As a result, the memory off-state cannot be stable and the observed current level becomes relatively high. Therefore, it would be difficult to guarantee quality performance of the P/E characteristics under positive $V_{BG}$ conditions, even when the same P/E voltages are applied during the P/E operations with suitable control over the $V_{R}$. These observations can be one of the main reasons why the nonvolatile memory operations of the DG CTMTFTs were degraded during the application of a positive $V_{BG}$. The fixed $V_{BG}$ conditions required for the formation of fully-depleted regions can be modulated by the BGI thickness. As such, the BGI thickness control can be concluded as one of the most important design parameters for the improvements in device characteristics of the proposed DG CTM-TFTs. Actually, considering the device design parameters such as thickness values of tunneling and blocking oxides, the memory operation behaviors cannot be suitably explained by the F-N tunneling mechanism. Thus, it would be more desirable to quantitatively analyze the operation mechanism for the proposed DG CTM-TFTs by means of numerical simulations including the processand device structure-dependent parameters as future works.

IV. CONCLUSIONS

CTM-TFTs with DG configurations were fabricated and evaluated, where IGZO and ZnO thin films were used as the active and charge trap layers, respectively. We also used two BGI thicknesses (50 and 100 nm) to examine the effect that capacitance coupling between two GIs has on the memory device characteristics of the DG CTM-TFTs. The fabricated devices exhibited a wide MW of 13.8 V in DG mode operation as well as fast P/E speeds. By introducing a proper fixed V_BG, the V_TH could be modulated as designed, and hence, the V_R could be easily set for improving the nonvolatile memory performance. The improvement in the nonvolatile memory performance illustrates the first benefit of the DG configuration for the CTM-TFTs. Furthermore, the effect of fixed V_BG bias could be controlled by appropriately designing the capacitance coupling ratio of C_BGI/C_TGI, which was determined by the variations in the BGI thickness in this work. A larger coupling ratio was found to be more desirable for effective tuning control of the V_TH, whereas an excessively large coupling ratio was examined to reduce the operating margin of the fixed V_BG for obtaining sound P/E operations, due to higher field sensitivity. Similarly, for low-voltage operations, the capacitance coupling ratio and the fixed V_BG conditions could be synergistically designed for the DG CTM-TFTs, which serves as the second benefit of the DG configuration. For the fabricated device with a BGI thickness of 100 nm, a memory on/off ratio of 3.1×10⁶ could be successfully obtained with P/E voltages of ± 15 V and a fixed V_BG of -3 V. The memory retention time was also confirmed to be remarkably influenced by controlling the fixed V_BG condition as a result of using the DG configuration. We can conclude that the chargetrap/detrap events for the DG CTM-TFTs could be strategically designed to enhance the nonvolatile memory characteristics compared to the conventional SG CTMTFTs by controlling the fixed V_BG and the capacitance coupling ratio. Especially, our results strongly suggested that the DG configuration can act as an effective solution to meet the requirements of both higher performance and lower-voltage operations for the next generation NVM.