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Authors Han-Yeol Lee; Eunji Youn; Young-Chan Jang
Page pp.378-387
ISSN 1598-1657
Keywords Pipelined SAR ADC ; redundancy generation ; dynamic amplifier ; input range calibration ; digital error correction ;
Abstract A 10-bit 100-MS/s pipelined SAR ADC which consists of a 5-bit coarse SAR ADC with 1-bit redundancy, a dynamic amplifier for a residue amplifier, a 6-bit fine SAR ADC, and a digital error correction is proposed. One-bit redundancy generation for a digital error correction is designed using a capacitor-based DAC used in the 5-bit coarse SAR ADC for a sub-ADC of a pipelined ADC. The input range calibration and dynamic amplifier with gain compensation circuit are proposed to improve the linearity of the pipelined SAR ADC. The proposed pipelined SAR ADC has been implemented using a 65-nm 1-poly 8-metal CMOS process with a 1.2-V supply voltage. Its active area and power consumption are 410 μm × 425 μm and 4.35 mW, respectively. The measured SNDR are approximately 53.47 dB for a 2.4 Vpp differential sinusoidal input with a frequency of 9.99 MHz.