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The Journal of Semiconductor Technology and Science (JSTS) is an international, peer-reviewed, and open-access journal that is published bimonthly.
- Scope: semiconductor processes, devices, circuits, and MEMS.
- Editor-in-Chief: Prof. Woo Young Choi (ECE, Seoul National University)
- Indexed within Science Citation Index Expanded (SCIE), SCOPUS, Korea Citation Index (KCI), and other databases.

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  3. 2026-08 (Vol.26 No.04)
  4. 10.5573/JSTS.2026.26.4.272
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REFERENCES

1 
T. Hamamoto, S. Sugiura, and S. Sawada, “On the retention time distribution of dynamic random access memory (DRAM)”, IEEE Transactions on Electron Devices, vol. 45, no. 6, pp. 1300-1309, 1998.DOI
2 
S. K. Park, “Technology scaling challenge and future prospects of DRAM and NAND flash memory”, 2015 IEEE International Memory Workshop (IMW), pp. 1-4, 2015.DOI
3 
K. Kim, U. I. Chung, Y. Park, J. Lee, J. Yeo, and D. Kim, “Extending the DRAM and FLASH memory technologies to 10 nm and beyond”, Optical Microlithography XXV, vol. 8326, pp. 46-56, 2012.DOI
4 
K. Saino, “Progress and issues in dielectric materials for sub-100 nm DRAM technology”, 1st International Symposium on Dielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing, p. 159, 2004.Google Search
5 
S. Okhonin, M. Nagoga, J. M. Sallese, and P. Fazan, “A capacitor-less 1T-DRAM cell”, IEEE Electron Device Letters, vol. 23, no. 2, pp. 85-87, 2002.DOI
6 
D. I. Moon, S. J. Choi, J. W. Han, S. Kim, and Y. K. Choi, “Fin-width dependence of BJT-based 1T-DRAM implemented on FinFET”, IEEE Electron Device Letters, vol. 31, no. 9, pp. 909-911, 2010.DOI
7 
E. Yoshida, and T. Tanaka, “A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory”, IEEE Transactions on Electron Devices, vol. 53, no. 4, pp. 692-697, 2006.DOI
8 
H. J. Wann, and C. Hu, “A capacitorless DRAM cell on SOI substrate”, Proceedings of IEEE International Electron Devices Meeting, pp. 635-638, 1993.Google Search
9 
R. Ranica, A. Villaret, C. Fenouillet-Beranger, P. Malinge, P. Mazoyer, P. Masson, D. Delille, C. Charbuillet, P. Candelier, and T. Skotnicki, “A capacitor-less DRAM cell on 75 nm gate length, 16 nm thin fully depleted SOI device for high density embedded memories”, IEDM Technical Digest. IEEE International Electron Devices Meeting, pp. 277-280, 2004.DOI
10 
M. Bawedin, S. Cristoloveanu, and D. Flandre, “A capacitorless 1T-DRAM on SOI based on dynamic coupling and double-gate operation”, IEEE Electron Device Letters, vol. 29, no. 7, pp. 795-798, 2008.DOI
11 
G. Giusi, and G. Iannaccone, “Junction engineering of 1T-DRAMs”, IEEE Electron Device Letters, vol. 34, no. 3, pp. 408-410, 2013.DOI
12 
H. Duan, “From MOSFET to FinFET to GAAFET: The evolution, challenges, and future prospects”, Applied and Computational Engineering, vol. 50, no. 1, pp. 113-120, 2024.DOI
13 
D. Nagy, G. Indalecio, A. J. Garcia-Loureiro, M. A. Elmessary, K. Kalna, and N. Seoane, “FinFET versus gate-all-around nanowire FET: Performance, scaling, and variability”, IEEE Journal of the Electron Devices Society, vol. 6, pp. 332-340, 2018.DOI
14 
M. Ertosun, M. G. Guenhan, and K. C. Saraswat, “Investigation of capacitorless double-gate single-transistor DRAM: With and without quantum well”, IEEE Transactions on Electron Devices, vol. 57, no. 3, pp. 608-613, 2010.DOI
15 
M. Moore, “International Roadmap for Devices and Systems (IRDS)”, IRDS, 2021.Google Search
16 
P. Bal, B. Ghosh, P. Mondal, and M. W. Akram, “A laterally graded junctionless transistor”, Journal of Semiconductors, vol. 35, no. 3, p. 034003, 2014.DOI
17 
L. Yang, J. R. Watling, R. C. Wilkins, M. Borici, J. R. Barker, A. Asenov, and S. Roy, “Si/SiGe heterostructure parameters for device simulations”, Semiconductor Science and Technology, vol. 19, no. 10, p. 1174, 2004.DOI
18 
Synopsys TCAD Sentaurus, Sentaurus Device User Guide. Mountain View, CA, USA: Synopsys TCAD Sentaurus, 2013.Google Search
19 
M. S. Kavrik, et al., “Ultralow defect density at sub-0.5 nm HfO$_2$/SiGe interfaces via selective oxygen scavenging”, ACS Applied Materials & Interfaces, vol. 10, no. 36, pp. 30794-30802, 2018.DOI
20 
Q. Yao, et al., “Investigate on the mechanism of HfO$_2$/Si$_{0.7}$Ge$_{0.3}$ interface passivation based on low-temperature ozone oxidation and Si-Cap methods”, Nanomaterials, vol. 11, no. 4, p. 955, 2021.DOI
21 
J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'Neill, A. White, and A. M. Kelleher, “Nanowire transistors without junctions”, Nature Nanotechnology, vol. 5, no. 3, pp. 225-229, 2010.DOI
22 
E. O. Kane, “Theory of tunneling”, Journal of Applied Physics, vol. 32, no. 1, pp. 83-91, 1961.DOI
23 
C. Rivas, R. Lake, G. Klimeck, W. R. Frensley, M. V. Fischetti, P. E. Thompson, S. L. Rommel, and P. R. Berger, “Full-band simulation of indirect phonon assisted tunneling in a silicon tunnel diode with delta-doped contacts”, Applied Physics Letters, vol. 78, no. 6, pp. 814-816, 2001.DOI
24 
M. V. Fischetti, and S. E. Laux, “Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys”, Journal of Applied Physics, vol. 80, no. 4, pp. 2234-2252, 1996.DOI
25 
J.-H. Bae, et al., “Characterization of a capacitorless DRAM cell for cryogenic memory applications”, IEEE Electron Device Letters, vol. 40, no. 10, pp. 1614-1617, 2019.DOI
26 
J. K. P. Bhamidipati, G. Bhattarai, and A. N. Caruso, “Effect of proton irradiation induced localized defect clusters on recovery time and leakage current in silicon photoconductive semiconductor switches”, AIP Advances, vol. 13, no. 10, 2023.DOI
27 
S. T. Chang, C. W. Liu, and S. C. Lu, “Base transit time of graded-base Si/SiGe HBTs considering recombination lifetime and velocity saturation”, Solid-State Electronics, vol. 48, no. 2, pp. 207-215, 2004.DOI
28 
D. K. Schroder, “Carrier lifetimes in silicon”, IEEE Transactions on Electron Devices, vol. 44, no. 1, pp. 160-170, 2002.DOI
29 
B. Yang, K. D. Buddharaju, S. H. G. Teo, N. Singh, G. Q. Lo, and D. L. Kwong, “Vertical silicon-nanowire formation and gate-all-around MOSFET”, IEEE Electron Device Letters, vol. 29, no. 7, pp. 791-794, 2008.DOI
30 
S. Ye, K. Yamabe, and T. Endoh, “Ultimate vertical gate-all-around metal-oxide-semiconductor field-effect transistor and its three-dimensional integrated circuits”, Materials Science in Semiconductor Processing, vol. 134, p. 106046, 2021.DOI