I. INTRODUCTION

Dynamic random-access memory (DRAM), consisting of a single transistor and capacitor, has been widely adopted for its high performance and integration density ^{[1, 2]}. However, as device dimensions continued to shrink, sustaining or improving memory performance became increasingly difficult ^{[3, 4]}. To overcome these limitations, one-transistor DRAM (1T-DRAM) has emerged as a potential successor to conventional DRAM ^{[5- 11]}. 1T-DRAM is a capacitorless memory device that operates using the floating body effect, enabling data storage without a dedicated capacitor and allowing higher integration density than conventional DRAM.

Gate-all-around (GAA) transistors have demonstrated superior electrostatic control compared to planar and FinFET structures, leading to enhanced device performance. The progression from planar to FinFET and ultimately to GAA architectures reflects the continual improvement in channel control required for advanced scaling ^{[12, 13]}.

In this study, a 1T-DRAM based on a GAA junctionless field effect transistor (GAA-JLFET) was proposed, incorporating a vertically stacked SiGe storage layer and partial structural modifications to enhance memory performance. SiGe is selected as the storage material due to its favorable band alignment and superior hole retention characteristics ^[14]. Furthermore, by partially removing the Si$_{0.8}$Ge$_{0.2}$ storage layer near the source region, recombination in that area is effectively suppressed. This optimization improves the retention time (RT) beyond the International Roadmap for Devices and Systems (IRDS) standard of 64 ms while maintaining the sensing margin (SM) ^[15]. The proposed device was designed and evaluated through three-dimensional (3D) technology computer-aided design (TCAD) simulations, demonstrating its potential as a next-generation memory technology.

II. DEVICE STRUCTURE AND SIMULATION METHOD

Fig. 1 shows the 3D schematic and cross-sectional view of the proposed 1T-DRAM. The device parameters are summarized in Table 1. The n-type silicon (Si) nanowire has a radius ($R$) of 10 nm, with the source, body, and drain regions doped at concentrations of $5\times 10^{19}\text{ cm}^{-3}$, $1\times 10^{18}\text{ cm}^{-3}$, and $5\times 10^{19}\text{ cm}^{-3}$, respectively. These concentrations were chosen to minimize series and contact resistance with heavily doped source/drain and to set a lower body doping that is fully depleted due to the gate work function of 5.0 eV, thereby suppressing off-state leakage ^[16]. The body length was designed to be relatively long to improve memory performance, as an extended body enhances the effective charge storage capacity. The storage layer consisted of p-type Si$_{0.8}$Ge$_{0.2}$, with a doping concentration of $1\times 10^{18}\text{ cm}^{-3}$ and a thickness ($T_{\rm st}$) of 2 nm. SiGe exhibited a higher valence band offset than Si, which enhances hole storage capability. A Ge fraction of 0.2 was selected to improve charge retention while minimizing lattice mismatch that could compromise structural stability ^[17]. The gate dielectric was composed of HfO$_2$ with a thickness ($T_{\rm ox}$) of 2 nm, which is a high-$k$ material to achieve low Equivalent Oxide Thickness (EOT), while the gate length ($L_{\rm g}$) and thickness ($T_{\rm g}$) are 70 and 3 nm, respectively. An underlap length ($L_{\rm underlap}$) of 15 nm was introduced to reduce the electric field at the body/drain and source/body interfaces. The body length ($L_{\rm body}$) and source/drain length ($L_{\rm gs,gd}$) were 100 and 65 nm, respectively.

Fig. 1. 3D schematic and cross-sectional view of the proposed GAA-JLFET 1T-DRAM.

Sentaurus technology computer-aided design was employed to evaluate the performance of the proposed device ^[18]. Advanced physical models, including Fermi-Dirac statistics, Shockley-read-hall (SRH) recombination, non-local band-to-band tunneling (BTBT), bandgap narrowing, and quantum confinement were incorporated to accurately capture carrier transport and recombination behavior. Interface effects were modeled with an HfO$_2$/SiGe interface trap density of $D_{\rm it} = 4\times 10^{11}\text{ cm}^{-2}\text{eV}^{-1}$, consistent with the commonly reported $10^{11}$ to $10^{12}\text{ cm}^{-2}\text{eV}^{-1}$ range ^{[19, 20]}.

III. RESULTS AND DISCUSSION

Fig. 2 shows the $I_{\rm D}$-$V_{\rm G}$ transfer characteristics at 300 K as the room-temperature baseline and at 358 K as the standard DRAM high-temperature condition for retention and refresh evaluation. The low off-current ($I_{\rm off}$) of $1.1\times 10^{-12}\text{ A}/\mu\text{m}$ and the high threshold voltage ($V_{\rm th}$) of 0.306 V at $V_{\rm GS} = 0\text{ V}$ indicate that the body region is fully depleted, which is achieved with a high work function gate metal ^[21]. A fully depleted body region is crucial for enhanced memory performance, as partial depletion increases the SRH recombination rate, reducing RT. Furthermore, at 358 K, $I_{\rm off}$ increased to $3.9\times 10^{-11}\text{ A}/\mu\text{m}$ and $V_{\rm th}$ decreased to 0.252 V due to the higher carrier generation rate at elevated temperatures.

Fig. 2. Transfer characteristics of the proposed 1T-DRAM at 300 K and 358 K.

Fig. 3. Transient characteristics of the proposed GAA-JLFET 1T-DRAM.

Fig. 3 shows the transient characteristics of the 2 nm vertically stacked storage layer and 15 nm underlap structure at $T = 358\text{ K}$. The corresponding bias conditions are summarized in Table 2. The operation sequence begins with an initial read phase lasting 10 ns. During the write ‘1’ operation, gate and drain voltages of -1 and 1.5 V were applied, respectively, creating a steep energy band that facilitates BTBT. In the write ‘0’ operation, the potential barrier is lowered, allowing holes to drift toward the drain region and creating a distinct difference in hole densities between the two states. This charge disparity resulted in different read ‘1’ and read ‘0’ currents, defining the SM. The proposed device achieved an SM of 1.13 $\mu$A/$\mu$m.

During the write ‘1’ operation, the applied bias induces strong band bending at the body-drain junction, leading to BTBT. The tunneling probability is analyzed using the nonlocal BTBT model, expressed as Eq. (1) ^{[22, 23]}:

where $F$ denotes the electric field, $F_0 = 1\text{ V/cm}$, and $P$ is set to 2.0 for direct tunneling and 2.5 for phonon-assisted tunneling. The corresponding prefactors are given in Eqs. (2) and (3), respectively:

where $m_{\rm c}$, $m_{\rm v}$, $m_{\rm r}$, $g$, $N_{\rm op}$, $D_{\rm op}$, $\rho$, $\varepsilon_{\rm op}$, $E_{\rm g}$, and $\Delta_{\rm c}$ represent the conduction and valence band effective masses, reduced mass, degeneracy factor, optical phonon occupation number, deformation potential, mass density, phonon energy, bandgap, and conduction band offset, respectively. The dominant factor influencing the BTBT term in this equation lies within the exponential component, which is primarily governed by the bandgap, effective mass, and electric field.

During the write ‘1’ operation, BTBT is predominantly activated in the SiGe region due to its higher valence band offset compared to Si. The BTBT generation rate is considerably higher in Si$_{0.8}$Ge$_{0.2}$ than in Si (Fig. 4(a)). To quantify the tunneling path, energy band diagrams and BTBT profiles were evaluated along the X-X$^\prime$ and Y-Y$^\prime$ directions in Figs. 4(b) and 4(c). The peak tunneling distances are found to be 4.61 nm for Si$_{0.8}$Ge$_{0.2}$ and 5.12 nm for Si, indicating that the SiGe storage layer provides a shorter tunneling path. Furthermore, the carrier effective mass in SiGe decreases with increasing Ge content ^[24].

Fig. 4. (a) BTBT distribution during write ‘1’ operation, (b) Energy band diagram along X-X$^\prime$, (c) Energy band diagram along Y-Y$^\prime$.

Fig. 5. (a) Electric field distribution during write ‘1’ operation, (b) Electric field and BTBT generation along X-X$^\prime$.

Fig. 5(a) shows the cross-sectional electric field distribution during the write ‘1’ operation, showing a concentrated field at the body-drain junction. Fig. 5(b) plots the electric field and BTBT generation rate along the X-X$^\prime$ line. Compared with the Si center region, the Si$_{0.8}$Ge$_{0.2}$ edge exhibits an electric field more than $10^2$ times stronger. This enhancement results from the shorter effective gate-to-drain spacing near the SiGe edge, which confines the potential drop ($\Delta V$) over a smaller distance ($d$), increasing the electric field ($F$) and promoting a higher BTBT rate.

Consequently, the combined effects of a shorter tunneling distance, reduced effective mass, and stronger electric field result in a significantly higher BTBT rate in SiGe compared to Si. This confirms that the SiGe region plays a critical role in enabling an efficient BTBT process in the proposed device.

Fig. 6(a) shows the hole density distribution in the device during the hold ‘1’ operation, showing that holes are primarily concentrated beneath the gate region. Fig. 6(b) shows the energy band diagram along the X-X$^\prime$ direction, where the energy band directly beneath the gate is observed to be higher than that in the underlap region. This behavior results from the applied voltage conditions during the hold ‘1’ operation, with a gate voltage of -0.5 V and a drain voltage of 0 V.

Fig. 6. (a) Hole density distribution during the hold ‘1’ operation, (b) Energy band profile along the X-X$^\prime$.

These voltage conditions are deliberately configured to retain the generated holes for an extended duration, improving memory performance. Consequently, most of the holes are stored in the storage layer beneath the gate. As previously discussed, the high gate work function induces a fully depleted body region; however, the accumulated holes beneath the gate locally neutralize this depletion. During the read ‘1’ operation, the presence of these holes leads to a higher drain current compared to the read ‘0’ state, defining the SM.

Fig. 7. (a) Cross-sectional view of hole and electron density during the hold ‘1’ operation, (b) Hole and electron density profile along the X-X$^\prime$ direction.

Fig. 7(a) shows the cross-sectional electron and hole density distributions for a storage-layer thickness of 2 nm, while Fig. 7(b) shows the corresponding electron and hole density profiles along the X-X$^\prime$ direction. During the write operation, a significant accumulation of holes occurred in the body region, while electrons remained concentrated in the n-type source and drain regions, resulting in carrier diffusion and increased recombination in localized areas.

Fig. 8(a) shows the SRH recombination distribution during the hold ‘1’ operation, while Fig. 8(b) shows the SRH recombination profile along the Y-Y$^\prime$ direction. The SRH recombination rate is expressed in Eq. (4):

where $n$ and $p$ denote the electron and hole concentrations, $n_{\rm i}$ represents the intrinsic carrier concentration, $\tau_{\rm n}$ and $\tau_{\rm p}$ indicate the electron and hole lifetimes, and $E_{\rm t}$ refers to the defect level measured from the intrinsic level $E_{\rm i}$. The intrinsic carrier concentration is evaluated at $T = 358\text{ K}$. For simplicity, we assume $E_{\rm t} \approx E_{\rm i}$ which corresponds to the case where a midgap defect most strongly affects SRH recombination ^[25].

Fig. 8. (a) SRH recombination distribution during the hold ‘1’ operation, (b) SRH recombination profile along Y-Y$^\prime$.

SRH recombination is the dominant mechanism in indirect bandgap materials, such as Si ^[26]. Analysis of the numerator indicates that the product $pn$ remains approximately similar at both the center and the edges. However, the denominator is predominantly influenced by the electron density term, making electron density the rate-determining factor. The electron density at the device center is roughly $10^3$ times higher than at the edges (Fig. 7(b)). Additionally, the electron and hole carrier lifetimes in Si$_{0.8}$Ge$_{0.2}$ are $5\times 10^{-6}\text{ s}$ and $5\times 10^{-7}\text{ s}$, respectively ^[27]. Moreover, the electron and hole carrier lifetimes in Si are $1\times 10^{-5}\text{ s}$ and $3\times 10^{-6}\text{ s}$, respectively ^[28]. Since the hole lifetime in SiGe is approximately ten times shorter than in Si, the denominator in SiGe becomes about $10^4$ times larger than that in Si. Along the Y-Y$^\prime$ direction in Fig. 8(b), the SRH recombination rate is observed to be roughly $10^4$ times higher. These results quantitatively confirm that the reduced carrier lifetime in SiGe significantly influences charge retention and, consequently, overall device performance. Therefore, a partial cut-off of the SiGe region is analyzed to suppress recombination and enhance charge retention.

Fig. 9. Fabrication process of the partially cut-off 1T-DRAM.

Fig. 9 shows the fabrication process of the partially cut-off 1T-DRAM. The process begins with the preparation of an n-type Si substrate through phosphorous (P) implantation, which was chosen to establish a uniform and thermally stable n-type background. As the body region requires a lower doping concentration compared to the source and drain, an initial n-type doping is performed to achieve the appropriate body doping level. Subsequently, pillar formation and protection steps are conducted to enable selective doping. Ion implantation is then applied to the lower portion of the pillar to adjust the doping concentration, forming the drain region ^[29]. After forming the drain region, an isolation layer is deposited to provide structural and electrical separation. The SiGe storage layer is then grown using chemical vapor deposition (CVD) and subsequently etched. This is followed by the deposition of HfO$_2$ through atomic layer deposition to form the gate dielectric. To define the underlap region near the drain, the isolation layer is selectively patterned. Finally, the gate material is deposited using physical vapor deposition to complete the gate structure. The gate etching process is subsequently carried out to define the gate region while preserving the designed underlap characteristics. Following gate formation, the source electrode is deposited to establish efficient electrical contact. Finally, vias for the source, drain, and gate are patterned and etched, completing the fabrication of the proposed device ^[30].

To maintain hole density while enhancing RT, a partial structural modification of the storage layer was analyzed. The SRH recombination rate was found to be most prominent in the SiGe storage layer near the source and drain regions. Therefore, the SiGe adjacent to the source was selectively removed, ensuring that the overall hole storage capability remained unaffected. The SiGe near the drain was retained, as it plays a crucial role in hole generation during the write ‘1’ operation. If the SiGe near the drain is also removed, the Si/SiGe band offset and local electric-field concentration near the drain are reduced, so the tunneling-driven hole injection near the drain is strongly suppressed. As a result, the sensing margin is markedly reduced and the memory operation can even be disabled under the same bias conditions. Fig. 10(a) compares the hole density distributions of devices with and without the source-adjacent SiGe cut-off, while Fig. 10(b) shows the hole density profile along the X-X$^\prime$ direction. The results show that the hole density in the storage layer directly beneath the gate remains nearly unaffected by the cut-off process. This confirms that the modification did not affect the overall hole density in the storage layer and successfully preserves the charge storage characteristics of the device.

Fig. 10. (a) Hole density distribution for the conventional and partially cut-off structures, (b) Hole density along X-X$^\prime$.

Fig. 11. (a) SRH recombination distribution for the conventional and the partially cut-off structures, (b) SRH recombination profile along X-X$^\prime$, (c) SRH recombination profile along Y-Y$^\prime$.

Fig. 11(a) compares the SRH recombination rates of devices with and without the SiGe cut-off near the source, while Figs. 11(b) and 11(c) demonstrate the SRH recombination profiles along the X-X$^\prime$ and Y-Y$^\prime$ directions, respectively. SRH recombination in the SiGe layer along the X-X$^\prime$ direction is significantly reduced due to the removal of the source-adjacent SiGe region, where recombination was most pronounced (Figs. 11(a) and (b)). Similarly, Fig. 11(c) indicates that SRH recombination near the source-adjacent body region is also suppressed along the Y-Y$^\prime$ direction. The results confirm that removing the SiGe region near the source effectively reduces recombination. Electrically, this partial cut-off is expected to introduce minor side effects in the $I_{\rm D}$-$V_{\rm G}$ characteristics, such as a slight reduction in drain current at low gate voltage and a minor decrease in $I_{\rm on}$ due to a small source-side band hump. However, these effects are not expected to significantly affect memory performance. Consequently, this structural modification minimizes charge loss, resulting in improved retention characteristics while maintaining the hole density in the storage layer.

Fig. 12. SM and RT for the conventional and partially cut off structures.

Fig. 12 shows the variations in SM over the hold time for both the original device and the device with the SiGe cut-off. The results indicated that, with the SiGe cut-off, the RT increased from 50.7 to 106.53 ms, meeting the IRDS roadmap requirement of 64 ms. Additionally, the SM increased from 1.13 to 1.24 $\mu$A/$\mu$m, further enhancing the device’s performance.

IV. CONCLUSIONS

A capacitorless 1T-DRAM based on a GAA-JLFET with a vertically stacked Si$_{0.8}$Ge$_{0.2}$ storage layer was proposed and investigated in this study. The Si$_{0.8}$Ge$_{0.2}$ layer enhanced hole confinement through valence band offset; however, the initial device exhibited an RT of 50.7 ms, which did not satisfy the 64 ms IRDS requirement at 358 K due to retention loss near the source-side Si$_{0.8}$Ge$_{0.2}$ region caused by short carrier lifetime. A partial cut-off of the source-adjacent Si$_{0.8}$Ge$_{0.2}$ layer was introduced to suppress localized recombination. Consequently, the RT increased from 50.7 to 106.53 ms, and the SM increased from 1.13 to 1.24 $\mu$A/$\mu$m. These results demonstrated the high suitability of the optimized GAA-JLFET structure for high-density next-generation memory applications.