| Title |
Design of Capacitorless Dynamic Random-Access Memory based on GAA JLFET with Vertically Stacked Storage Layer and Underlapped Gate Structure |
| Authors |
(Won Suk Koh) ; (Jin Park) ; (Gang San Yun) ; (Soo Bean Song) ; (Kyeong Min Lim) ; (Sang Ho Lee) ; (Young Jun Yoon) ; (In Man Kang) |
| DOI |
https://doi.org/10.5573/JSTS.2026.26.4.272 |
| Keywords |
One transistor dynamic random-access memory (1T-DRAM); gate-all-around junctionless field effect transistor (GAA-JLFET); Si0.8Ge0.2; sensing margin (SM); retention time (RT) |
| Abstract |
This study proposed and analyzed a capacitorless one-transistor dynamic random-access memory (1TDRAM) based on a gate-all-around junctionless field effect transistor (GAA-JLFET) featuring a vertically stacked storage layer and an underlapped gate structure. The device incorporated a 2 nm Si0.8Ge0.2 storage region with a higher valence band offset than silicon (Si), enabling stronger hole confinement and improved storage potential.
A negative hold bias of -0.5 V was applied to extend hole retention and suppress diffusion during the program operation. At 358 K, the design achieved a sensing margin (SM) of 1.13 μA/μm and a retention time (RT) of 50.7 ms, which did not satisfy the International Roadmap for Devices and Systems (IRDS) requirement of 64 ms. Since the baseline design did not meet the target, the retention loss was attributed to recombination concentrated near the source-side Si0.8Ge0.2 region. By partially removing the Si0.8Ge0.2 layer adjacent to the source to suppress the recombination rate in that area, the SM and RT were improved to 1.24 μA/μm and 106.53 ms, respectively. |