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The Journal of Semiconductor Technology and Science (JSTS) is an international, peer-reviewed, and open-access journal that is published bimonthly.
- Scope: semiconductor processes, devices, circuits, and MEMS.
- Editor-in-Chief: Prof. Woo Young Choi (ECE, Seoul National University)
- Indexed within Science Citation Index Expanded (SCIE), SCOPUS, Korea Citation Index (KCI), and other databases.

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  3. 2026-08 (Vol.26 No.04)
  4. 10.5573/JSTS.2026.26.4.249
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REFERENCES

1 
S. Shiraki, S. Takahashi, A. Yamada, M. Yamamoto, K. Senda, Y. Ashida, A. Hiruma, and N. Tokura, “High voltage and high reliability silicon-on-insulator power IC technologies and their application to 750 V 4.5 A micro-inverter IC”, Japanese Journal of Applied Physics, vol. 51, no. 4S, pp. 2-6, 2012.DOI
2 
S. K. Jha, P. Verma, and M. Taleja, “Design of low power CMOS based Schmitt trigger in 180 nm technology”, Proc. of 2019 4th International Conference on Internet of Things: Smart Innovation and Usages (IoT-SIU), pp. 1-5, 2019.DOI
3 
S. W. Chang, J. H. Li, M. K. Huang, Y. C. Huang, S. T. Huang, H. C. Wang, Y. J. Huang, J. Y. Wang, L. W. Yu, Y. F. Huang, F. K. Hsueh, P. J. Sung, C. T. Wu, W. C. Y. Ma, K. H. Kao, Y. J. Lee, C. L. Lin, R. W. Chuang, K. P. Huang, S. Samukawa, Y. Li, W. H. Lee, T. Y. Chu, T. S. Chao, G. W. Huang, W. F. Wu, J. Y. Li, J. M. Shieh, W. K. Yeh, Y. H. Wang, D. D. Lu, C. J. Wang, N. C. Lin, C. J. Su, S. H. Lo, and H. F. Huang, “First demonstration of CMOS inverter and 6T-SRAM based on GAA CFETs structure for 3D-IC applications”, Proc. of IEEE International Electron Devices Meeting (IEDM), pp. 254-257, 2019.DOI
4 
W. Bae, “CMOS inverter as analog circuit: An overview”, Journal of Low Power Electronics and Applications, vol. 9, no. 3, 2019.DOI
5 
Y. Berg, O. Mirmotahari, J. G. Lomsdalen, and S. Aunet, “High speed ultra low voltage CMOS inverter”, Proc. of IEEE Computer Society Annual Symposium on VLSI, pp. 122-127, 2008.DOI
6 
Q. Xing, Y. Su, J. Lai, B. Li, B. Li, J. Bu, and G. Zhang, “Investigation of self-heating effects in UTBB FD-SOI MOSFETs by a modified thermal conductivity model”, IEEE Transactions on Electron Devices, vol. 69, no. 8, pp. 4129-4137, 2022.DOI
7 
S. S. Suryagandh, M. Garg, and J. C. S. Woo, “A device design methodology for sub-100-nm SOC applications using bulk and SOI MOSFETs”, IEEE Transactions on Electron Devices, vol. 51, no. 7, pp. 1122-1128, 2004.DOI
8 
V. Kilchytska, B. K. Esfeh, C. Gimeno, B. Parvais, N. Planes, M. Haond, J. P. Raskin, and D. Flandre, “Comparative study of non-linearities in 28 nm node FDSOI and bulk MOSFETs”, Proc. of Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), pp. 128-131, 2017.DOI
9 
C. Lee, A. T. Putra, K. Shimizu, and T. Hiramoto, “Threshold voltage dependence of threshold voltage variability in intrinsic channel silicon-on-insulator metal-oxide-semiconductor field-effect transistors with ultrathin buried oxide”, Japanese Journal of Applied Physics, vol. 49, no. 4S, pp. 2-6, 2010.DOI
10 
J. Makipaa, and O. Billoint, “FDSOI versus bulk CMOS at 28 nm node: Which technology for ultra-low power design?”, Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 554-557, 2013.DOI
11 
M. Godara, C. Madhu, and G. Joshi, “Comparison of electrical characteristics of 28 nm bulk MOSFET and FDSOI MOSFET”, Proc. of IEEE Electron Devices Kolkata Conference (EDKCON), pp. 413-418, 2018.DOI
12 
A. Karel, “Comparative study of FinFET and FDSOI nanometric technologies based on manufacturing defect testability”, 2017.Google Search
13 
O. Weber, “FDSOI vs FinFET: Differentiating device features for ultra low power & IoT applications”, Proc. of IEEE International Conference on IC Design and Technology (ICICDT), pp. 1-3, 2017.DOI
14 
T. B. Hook, “Fully depleted devices for designers: FDSOI and FinFETs”, Proc. of IEEE Custom Integrated Circuits Conference (CICC), pp. 1-7, 2012.DOI
15 
T. Chaves De Albuquerque, D. Issartel, R. Clerc, P. Pittet, R. Cellier, W. Uhring, A. Cathelin, and F. Calmon, “Body-biasing considerations with SPAD FDSOI: Advantages and drawbacks”, Proc. of European Solid-State Device Research Conference (ESSDERC), pp. 210-213, 2019.DOI
16 
F. Arnaud, S. Clerc, S. Haendler, R. Bingert, P. Flatresse, V. Huard, and T. Poiroux, “Enhanced design performance thanks to adaptative body biasing technique in FDSOI technologies”, Proc. of IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), pp. 1-5, 2017.DOI
17 
G. Tochou, A. Cathelin, A. Frappe, A. Kaiser, and J. Rabaey, “Impact of forward body-biasing on ultra-low voltage switched-capacitor RF power amplifier in 28 nm FD-SOI”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 1, pp. 50-54, 2022.DOI
18 
J. Chen, M. B. Alawieh, Y. Lin, M. Zhang, J. Zhang, Y. Guo, and D. Z. Pan, “Automatic selection of structure parameters of silicon on insulator lateral power device using Bayesian optimization”, IEEE Electron Device Letters, vol. 41, no. 8, pp. 1288-1291, 2020.DOI
19 
M. Y. Kao, F. Chavez, S. Khandelwal, and C. Hu, “Deep learning-based BSIM-CMG parameter extraction for 10-nm FinFET”, IEEE Transactions on Electron Devices, vol. 69, no. 8, pp. 4765-4768, 2022.DOI
20 
J. S. Yoon, S. Lee, H. Yun, and R. H. Baek, “Digital/analog performance optimization of vertical nanowire FETs using machine learning”, IEEE Access, vol. 9, pp. 29071-29077, 2021.DOI
21 
T. Dobashi, H. Kobayashi, Y. Okuyama, and T. Ohmori, “Effect of initial-learning dataset on etching profile optimization using machine learning in plasma etching”, Japanese Journal of Applied Physics, vol. 62, 2023.DOI
22 
H. Liu, S. Wang, R. Zhao, H. Ma, L. Ma, S. Liu, S. Chen, and H. Liu, “Prediction of single event effects in FinFET devices based on deep learning”, IEEE Journal of the Electron Devices Society, vol. 11, pp. 539-545, 2023.DOI
23 
K. Shiba, N. Miyashita, Y. Okada, and T. Sogabe, “Inverse design of intermediate band solar cell via a joint drift-diffusion simulator and deep reinforcement learning scheme”, Japanese Journal of Applied Physics, vol. 62, 2023.DOI
24 
H. Yamano, A. Kovacs, J. Fischbacher, K. Danno, Y. Umetani, T. Shoji, and T. Schrefl, “Efficient optimization approach for designing power device structure using machine learning”, Japanese Journal of Applied Physics, vol. 62, 2023.DOI
25 
H. Yang, J. Lee, C. Park, C. Lee, M. Jin, J. Kim, J. C. Shin, S. Hwang, E. Lee, and Y. S. Kim, “Simultaneous improvement of multiple electrical characteristics in ultrathin a-IGZO TFTs using machine learning optimization”, ACS Applied Materials & Interfaces, 2025.DOI
26 
J. W. Park, and D. Suk, “Designing neuromorphic processor with on-chip learning”, vol. 6, 2020.DOI
27 
T. Y. Yoon, and J. H. Kim, “Optimization of CMOS inverter design using deep learning algorithm”, Proc. of Korean Conference on Semiconductors, 2025.Google Search
28 
N. Planes, O. Weber, V. Barral, S. Haendler, D. Noblet, D. Croain, M. Bocat, P. O. Sassoulas, X. Federspiel, A. Cros, A. Bajolet, E. Richard, B. Dumont, P. Perreau, D. Petit, D. Golanski, C. Fenouillet-Beranger, N. Guillot, M. Rafik, V. Huard, S. Puget, X. Montagner, M. A. Jaud, O. Rozeau, O. Saxod, F. Wacquant, F. Monsieur, D. Barge, L. Pinzelli, M. Mellier, F. Boeuf, F. Arnaud, and M. Haond, “28 nm FD-SOI technology platform for high-speed low-voltage digital applications”, Proc. of Symposium on VLSI Technology, pp. 133-134, 2012.DOI
29 
C. Fiegna, Y. Yang, E. Sangiorgi, and A. G. O’Neill, “Analysis of self-heating effects in ultrathin-body SOI MOSFETs by device simulation”, IEEE Transactions on Electron Devices, vol. 55, no. 1, pp. 233-244, 2007.DOI
30 
D. Vasileska, K. Raleva, and S. M. Goodnick, “Self-heating effects in nanoscale FD SOI devices: The role of the substrate, boundary conditions at various interfaces, and the dielectric material type for the BOX”, IEEE Transactions on Electron Devices, vol. 56, no. 12, pp. 3064-3071, 2009.DOI
31 
S. Makovejev, N. Planes, M. Haond, D. Flandre, J.-P. Raskin, and V. Kilchytska, “Comparison of self-heating and its effect on analogue performance in 28 nm bulk and FDSOI”, Solid-State Electronics, vol. 115, pp. 219-224, 2016.DOI
32 
T. Takahashi, T. Matsuki, T. Shinada, Y. Inoue, and K. Uchida, “Comparison of self-heating effect (SHE) in short-channel bulk and ultra-thin BOX SOI MOSFETs: Impacts of doped well, ambient temperature, and SOI/BOX thicknesses on SHE”, Proc. of IEEE International Electron Devices Meeting (IEDM), pp. 7.4.1-7.4.4, 2013.DOI
33 
J. Sun, X. Li, Y. Sun, and Y. Shi, “Impact of geometry, doping, temperature, and boundary conductivity on thermal characteristics of 14-nm bulk and SOI FinFETs”, IEEE Transactions on Device and Materials Reliability, vol. 20, no. 1, pp. 119-127, 2020.DOI
34 
S. J. Kang, J. H. Kim, Y. S. Song, S. Go, and S. Kim, “Investigation of self-heating effects in vertically stacked GAA MOSFET with wrap-around contact”, IEEE Transactions on Electron Devices, vol. 69, no. 2, pp. 910-914, 2022.DOI
35 
A. Ambarwari, Q. J. Adrian, and Y. Herdiyeni, “Analysis of the effect of data scaling on the performance of the machine learning algorithm for plant identification”, Jurnal RESTI (Rekayasa Sistem dan Teknologi Informasi), vol. 4, no. 1, pp. 117-122, 2020.DOI
36 
A. F. Agarap, “Deep learning using rectified linear units (ReLU)”, 2018.DOI
37 
J. He, L. Li, J. Xu, and C. Zheng, “ReLU deep neural networks and linear finite elements”, 2018.DOI
38 
D. P. Kingma, and J. Ba, “Adam: A method for stochastic optimization”, 2014.DOI
39 
M. D. Zeiler, “Adadelta: An adaptive learning rate method”, 2012.DOI
40 
T. Chilimbi, Y. Suzue, J. Apacible, and K. Kalyanaraman, “Project Adam: Building an efficient and scalable deep learning training system”, Proc. of 11th USENIX Symposium on Operating Systems Design and Implementation (OSDI), pp. 571-582, 2014.Google Search
41 
S. Salman, and X. Liu, “Overfitting mechanism and avoidance in deep neural networks”, 2019.DOI
42 
H. Li, J. Li, X. Guan, B. Liang, Y. Lai, and X. Luo, “Research on overfitting of deep learning”, Proc. of 2019 15th International Conference on Computational Intelligence and Security (CIS), pp. 78-81, 2019.DOI
43 
H. Lim, “A study on dropout techniques to reduce overfitting in deep neural networks”, Advanced Multimedia and Ubiquitous Engineering. Springer, pp. 133-139, 2021.DOI
44 
N. Srivastava, G. Hinton, A. Krizhevsky, I. Sutskever, and R. Salakhutdinov, “Dropout: A simple way to prevent neural networks from overfitting”, Journal of Machine Learning Research, vol. 15, pp. 1929-1958, 2014.Google Search
45 
I. Salehin, and D.-K. Kang, “A review on dropout regularization approaches for deep neural networks within the scholarly domain”, Electronics, vol. 12, no. 14, 2023.DOI
46 
D. Zhang, “A coefficient of determination for generalized linear models”, The American Statistician, vol. 71, no. 4, pp. 310-316, 2017.DOI